JPS63133269A - Dma controller - Google Patents

Abstract

PURPOSE:To decrease the issuing frequency of transfer commands by operating successively plural index registers while switching said registers and equalizing the number of commands between the reception side and the transmission side. CONSTITUTION:Plural index registers RI1-In are provided to a register file 1 and the contents of the index register designated by a counter a2 are outputted to an address bus 3 and a + or -1 adder 5. The counters a2 and b8 are compared with a maximum column length register 9 and the registers RI1-In are switched at N intervals to secure the coincidence of the number of transfer commands between the reception side and the transmission side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a DMA control device that performs data transfer between a storage device and an input/output port of an external device and exchanges the transferred data according to a certain format. It is related to.

Conventional technology There is a numerical simulation of large-scale scientific and technical calculations (
Science Inc.: Science Library Information Computer Series “Iterative solution of large matrices by computer JP184-21
9).

A system configuration has been proposed to efficiently execute this ADI method (Tohoku University Research Institute Symposium "New Computer Architecture" 1985.7 P5
3 to 67 N 〇In the above system configuration, NXN
It is equipped with a two-dimensional parallel processing array (NXNXN) and a three-dimensional data transfer network (NXNXN), and can easily perform data interchange operations in the ADI method.

This replacement operation will be explained below using figures.

FIG. 2 is a system configuration diagram showing a connection between a two-dimensional parallel processing array and a data transfer network.

In Figure 2, I is a parallel operation array composed of NXN two-dimensionally arranged operation units, and ■ is an NXNX parallel operation array.
A parallel processing array T is a storage device arranged in three dimensions of
and a data transfer network capable of accessing the one-dimensional direction of input B.

Each arithmetic unit of the parallel arithmetic array arranged two-dimensionally and the storage device of the data transfer network 2 arranged three-dimensionally are the characters rFJ written on the surface λBFIC and the characters rFJ written on the surface BCGF. Parallel processing array 1
The letters rFJ above are connected in a one-to-one correspondence. Therefore, the plane BCGF is connected directly, and the plane BFE is connected rotatably by 90 degrees.

N 1XNj XNk (Ii
, N3.

When solving the problem (Nk≦N) using the ADI method, data transfer is completed by using the data transfer network shown in FIG. 2 once in each direction.

The data arrangement in one direction in each arithmetic unit is
It can be treated as a one-dimensional array as shown in the figure.

Data transfer at this time can be completed by one access on either the sending side or the receiving side.

Next, JXNjXNk (N4≧N) as shown in FIG.

In the problem where Nj≧N or Hk≧N), we construct a data transfer network of NXNXN in each three-dimensional direction by
(niX N≧Ni≧(ni −1)XN),
nj (njX N≧Nj≧(nj-1)XN) and nk
Multiple use is required (nkxN≧Nk≧(nk-1)xN) times.

Multiplicity in each calculation unit ni, nj, nk
The data array in each direction represented by can be handled as a one-dimensional array of ni, nj, and nk pieces, as shown in FIG. The data transfer at this time can be treated as one-dimensional continuous data in each direction on the transmitting side, but on the receiving side it becomes one-dimensional data that is discontinuous at the boundaries of N, Ni, Nj, and Nk.

Conventional DMA controllers (eg Intel 8257) are used in such systems.

In this case, transfer commands to the DMA control device are required at discontinuous portions of data transfer.

In the above example, on the sending side, n1Xnj+njXnk+nkXni or 3
A transfer command for the DM device is required,
On the receiving side, 3 x n4 x nj x nk or 3 x n3 (in the case of n1=nj=nk=n) transfer commands are required.

Problems to be Solved by the Invention In the conventional DMA control device, the D
As the multiplicity n of transfer commands to the MA control device increases, n3 times as many transfer commands are required for n2 transfer commands on the transmitting side.

In view of the above conventional problems, the present invention provides a plurality of index registers and includes side leg means for switching the index registers in N increments, so that the number of transfer commands on the receiving side is equal to the number of transfer commands on the transmitting side. It is an object of the present invention to provide a DMA control device that can have the same number.

Means for Solving the Problems A DMA control device of the present invention includes a plurality of index registers for specifying a plurality of array data in a storage device, a ±1 adder for incrementing or decrementing all of the index registers, and a ±1 adder for incrementing or decrementing all of the index registers; a number register indicating the number of index registers to be used; a first counter that sequentially specifies the index register; a first comparison circuit that compares the number register and the first counter; and the storage device. an array length register that indicates the length of the array data in the storage device; and a second counter that counts the number of times the transfer process of the array data in the storage device is repeated;
a second comparison circuit that compares the array length register with the first and second counters; and a command register that stores an operating mode and controls the ±1 adder and the first and second counters. and a timing control circuit for controlling reading and writing of data in the storage device, and first and second comparison circuits are provided between a plurality of array data in the storage device and an input/output port for an external device. Based on the result, the index registers are sequentially switched and the order of the transferred data is changed while data is being transferred.

Effects According to the present invention, the number of transfer commands on the receiving side can be made the same as the number on the transmitting side by switching the index register in N increments with the above-described configuration.

To summarize the gist of the present invention, by sequentially switching a plurality of index registers according to the output result of a counter and transferring data, the receiving side for the 5DMA system cape device can change the order of the transferred data. The number of transfer commands is the same as the number of transfer commands on the sending side.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention.

In Figure 1, 1 is a register file with multiple index registers, and 2 is a register file 1.
A counter that sequentially selects the index registers of &,
3 is an address bus (which outputs the output of the selected index register as an address).
(DDRESSBUS), 4 is a command register that stores the operating mode, and 6 is an address bus 8 of 3? , ±1 adder that increments or decrements according to command register 4, 6 is register file 1
7 is a comparison circuit that compares the outputs of counter a2 and number register 6 and, if they match, clears all counter holes 2. 8 is a counter b that counts the number of DMA operations. ,9
10 is an array length register that specifies the length of data to be transferred at one time in one array, and 10 is a comparison circuit b111 that compares counter b8 and array length register 9 to check whether data transfer is complete. A timing circuit 12 generates the timing for access, and 12 is a data bus (DATA BUS) for setting data in the register file 11 number register 6 and array length register 9.
, 13 are internal data buses for writing data from the ±1 adder 6 or the data bus 12 into the register file 1.

The three-dimensional problem shown in Figure 4 can be solved using DMA in Figure 1.
A case in which a transfer operation is performed in a system using a control device will be described below. FIG. 5 shows the data arrangement in FIG. 4. Regarding the sending side data, see (a) in Figure 5.
), if you have the one-dimensional data array shown in ), you can complete the process by issuing a single command. If the data on the receiving side is arranged in the same way as in (a), taking into consideration all subsequent transfers, it will be as shown in (b) in Figure 5, but the order in which the data is received is complicated as shown in the figure. become.

The operating procedure of the DMA control device at this time will be explained using the flow diagram of FIG.

(1) To set the initial value, the length of the data array in one direction is determined in advance in the index register of register file 1 of the DMA control device, and an offset value is set in accordance with the degree of multiplicity. The number of index registers to be used simultaneously is set in number register 2, and the data array length is set in array length register 8.

(2) Set the command register operating mode and start the DMA control device.

(3) The DMA controller transfers the contents of the index register specified by counter 2L2 from register file 1 to address bus (DDRKSSBUS) 3 and ±1
Output to adder 6. Address bus (MUDDRKSS)
BUS) 3 is output as an address of an external storage device, and the memory is accessed according to the timing circuit 11.

(4) On the other hand, the ±1 adder 6 increments the input value by +1 or -1 according to the operation mode of the command register 4,
Write again to the index register of register file 1 via internal data bus 12. At the same time that the index register is processed by the ±1 adder 5, the counter b8 is incremented.

(6) If the counter b8 is N or smaller than the array length in the final cycle of transfer, return to (3) and output the address successively.

(6) If they are equal or larger, increment counter a2.

(7) Compare counters a and b with the array length register.

(8) If it is smaller, set the counter b8 by returning the value by N, return to (3), and output the address successively. If they are equal or greater, a signal is sent to timing circuit 11 to terminate the transfer operation.

Effects of the Invention As explained in detail above, the DMA control device of the present invention can make the number of DMA transfer commands equal to that on the sending side by sequentially switching and operating a plurality of index registers. This has the effect of reducing the number of command issuing operations.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the first embodiment of the present invention, FIG. 2 is a configuration diagram of a parallel processing array and data transfer network, FIG. 3 is a configuration diagram showing data arrays on the transmitting side and receiving side, and FIG. The figure is an explanatory diagram when the data transfer network in Figure 2 is used multiplexed, and Figure 6 is a configuration diagram of the data arrangement in Figure 4.
FIG. 6 is a flowchart explaining the operation of FIG. 1. 1...Register file, 2...Counter &, 3...Address bus (person DDRI
C8S BUS), 41. . ...Command register, 6... Adder,
6...Number register, 7...Comparison circuit a, 8...Counter b, 9...Array length register, 1o...Comparison Circuit b, 11...
...Timing circuit, 12...Data bus (
DATA BUS), 13... Internal data
bus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure KrV/WKL I C/'11/KmωSen 5
1JM l Hassa Fig. 2 Fig. 3 ((L) Sending section 1 (b)

Claims (1)

[Claims] a plurality of index registers that specify a plurality of array data in a storage device; a ±1 adder that increments or decrements the index register;
a number register indicating the number of index registers used; a first counter sequentially specifying the index register; a first comparison circuit comparing the number register and the first counter; and the memory. an array length register that indicates the length of the array data in the device; a second counter that counts the number of times the transfer process of the array data in the storage device is repeated; and the array length register and the first and second counters. a second comparison circuit that compares the
A storage device, comprising a command register that stores an operation mode and controls the ±1 adder and the first and second counters, and a timing control circuit that controls reading and writing of data in the storage device. The index registers are sequentially switched between the plurality of array data and the input/output port for the external device according to the results of the first and second comparison circuits, and the order of the transferred data is changed while data is being transferred. A DMA control device characterized by: