JPH02265316A - Comparator circuit - Google Patents

Abstract

PURPOSE:To arrange the duty ratio of an output waveform by inputting or outputting to a signal to/from an SCF LPF at a 1st clock, inputting and outputting a reference voltage at a 2nd clock so as to use the LPF in time division multiple and inputting each output to a post-stage of operational amplifier. CONSTITUTION:A signal is inputted from a 1st input terminal 1A at a clock phi1 and outputted via a 1st sample and hold circuit 3, while a reference voltage is inputted from a 2nd input terminal 1B at a clock phi2 and outputted via a 2nd sample and hold circuit 4. Time division multiplex is realized in the inside of the SCF LPF 2 by driving the LPF with clocks phi3, phi4 having the frequency twice the frequency of the clocks phi1, phi2. Thus, the signal path for the inputs 1A, 1B is the same as that of an operational amplifier being in the inside of the SCF LPF 2. That is, the same DC offset voltage is generated to both the input terminals 1A, 1B. That is, the input signal at the clock phi1 is compared with the input reference voltage at the clock phi2, then the effect by the offset voltage of the operational amplifier being the component of the pre-stage SCF LPF 2 is eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a comparator circuit, and in particular to an SCF type LPF.
The present invention relates to a comparator circuit having a comparator circuit.

[Conventional technology]

Conventionally, this type of comparator circuit is connected to an input terminal 1 as shown in FIG. 2(a), and connected to a first clock φ1 and this first clock φ1 as shown in FIG. 2(b). is an SCF type LPF 2 controlled by a second clock φ2 that does not overlap with each other, and this SCF! ! ! LPF
A switch S6 is connected to the output of the switch S6 and is controlled to be turned on and off by the first clock φ1, and a switch S6 is connected between the other terminal of this switch S6 and ground and controlled to be turned on and off by the second clock φ2. switch S7 and capacitor 5
and an operational amplifier 6 whose one (+) input terminal is connected to the other end of the capacitor 5 and whose (+) input terminal is grounded.
A switch S3 is connected between the output terminal of the operational amplifier 6 and the (-) input terminals and is controlled to be turned on and off by the second clock φ2, and an even number switch S3 is connected in series to the output terminal of the operational amplifier 6. Inverter 7 and the output of inverter 7 as D input, the opposite phase clock T1 of the first clock φ1.
The flip-flop 8 has a clear input and a Q output connected to an output terminal 9.

In such a conventional comparator circuit, the SCF type L
Since the reference voltage of PF2 is fixed, SCF type LP
A DC offset voltage is generated in an operational amplifier (not shown) provided inside F2. Conventionally, even if this DC offset voltage occurs, it is supplied to the capacitor 5 and the operational amplifier 6 as is.

[Problem to be solved by the invention]

The conventional comparator circuit described above is an SCF type LPF2.
Since the reference voltage in is fixed, such SCF type L
When the DC offset voltage generated in PF2 etc. increases,
There is a drawback that the duty ratio of the output waveform is distorted.

An object of the present invention is to provide a comparator circuit that can adjust the duty ratio of such an output waveform.

[Means to solve the problem]

The comparator circuit of the present invention includes a first switch connected to a first input terminal for inputting a signal and controlled by a first clock, and a first switch connected to a grounded second input terminal and controlled by a first clock. a second switch controlled by a second clock that does not overlap with the first clock; and a second switch connected to the first and second switches and controlled by the first and second clocks and the first and second clocks. an SCF type low-pass filter controlled by third and fourth clocks having twice the frequency of the clock; and an output of the filter is sampled and held by the first clock and the second clock, respectively. first and second sample-and-hold circuits, and first and second sample-and-hold circuits;
third and fourth switches connected to a hold circuit and controlled by the first and second clocks, respectively; a capacitor having one end commonly connected to the third and fourth switches; an operational amplifier whose other end is connected to one input end and whose other input end is grounded; and a fifth switch connected to the output end of the operational amplifier and the one input end and controlled by the second clock. , an even number of inverters connected in series to the operational amplifier output terminal, and data holding means having the inverter output as an input and an output terminal connected to an output terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are block diagrams of comparator circuits for explaining one embodiment of the present invention, respectively.

As shown in FIG. 1(a), this embodiment is connected to a first input terminal IA for inputting a signal, and is connected to a first clock φ1.
a first switch S1 controlled by a second clock S1 connected to a grounded second input terminal IB and controlled by a second clock φ2 that does not overlap with the first clock φ1; , these first and second switches Sl.

S2 and the first and second clocks φ1, φ
2 and third and fourth clocks φ3.2 having twice the frequency of the first and second clocks φ1°φ2. An SCF-type LPF2 controlled by φ4, and first and second SCFs that sample and hold the output of this LPF2 using a first clock φ1 and a second clock φ2, respectively.
/H circuit 3.4 and first and second S/H circuits 3.4
and the first and second clocks φ1
．． Third and fourth switches S3., respectively controlled by φ2. S4 and third and fourth switches S3. S
4, an operational amplifier 6 whose other ends are connected to (-) input terminals and whose (+) input terminals are grounded, and an output terminal of this operational amplifier 6. an even number of inverters 7 connected in series to the output terminal of the operational amplifier 6; It has a data holding flip-flop 8 whose output is connected to an output terminal 9.

In such a comparator circuit, the SCF type LPF 2 is time-division multiplexed. That is, at clock φ1, the signal from the first input terminal IA is input and outputted via the sample-and-hold circuit 3, while at clock φ2, the reference voltage is input from the second input terminal IB and the signal is output from the sample-and-hold circuit 4. It is output via.

Here, inside the SCF type LPF 2, as shown in FIG. 1(b), the clock φ1. Clock φ3 with twice the frequency of φ2. Time division multiplexing is realized by driving with φ4. Therefore, the signal path of input IA and the signal path of input IB are both operational amplifiers (
(not shown) are the same. That is, input terminal I
The same DC offset voltage can be generated for both A and input terminal IB.

In short, if the input signal at clock φ1 is compared with the input reference voltage of the clock waveform diagram, as in the comparator circuit shown in FIG. The duty ratio of the output waveform in the comparator circuit can be adjusted.

〔Effect of the invention〕

As explained above, the comparator circuit of the present invention has S
The SCF type LPF is constructed by time-division multiplexing the CF type LPF by inputting and outputting a signal at clock φ1 and inputting and outputting a reference voltage at clock φ2, and inputting the respective outputs to the subsequent operational amplifier. This has the effect of being able to cancel the DC offset voltage of the operational amplifier and adjusting the duty ratio of the output waveform.

8...Flip-flop (FF), 9...Output terminal, 81-S5...Switch, φ1-φ4. T1・
··clock.

Claims (1)

[Claims] A first switch connected to a first input terminal for inputting a signal and controlled by a first clock, and a first switch connected to a grounded second input terminal and said first clock do not overlap with each other. a second switch controlled by a second clock, connected to the first and second switches and having a frequency twice that of the first and second clocks and the first and second clocks; SCF-type low-pass filters controlled by third and fourth clocks, and first and second sample filters that sample and hold the outputs of the filters by the first and second clocks, respectively. a hold circuit; third and fourth switches connected to the first and second sample-and-hold circuits and respectively controlled by the first and second clocks; and the third and fourth switches. an operational amplifier whose other end is connected to one input terminal and whose other input terminal is grounded; a fifth switch controlled by a second clock; an even number of inverters connected in series to the output terminal of the operational amplifier; and data holding means having the inverter output as an input and having an output terminal connected to the output terminal. A comparator circuit characterized by: