JP2762542B2 - Comparator circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly, to a comparator circuit having an SCF (Switched Capacitor Filter) type LPF (Low Pass Filter).

[Conventional technology]

Conventionally, this kind of comparator circuit is connected to an input terminal 1 as shown in FIG. 2 (a), and has a first clock φ1 and a first clock φ1 as shown in FIG. 2 (b). Is a SCF type LPF2 controlled by a second clock φ2 which does not overlap each other, a switch S6 connected to the output of the SCF type LPF2 and controlled on / off by the first clock φ1, and a switch S6. A switch S7 which is connected between the other terminal and the ground and whose on / off control is performed by the second clock φ2; a capacitor 5; one (-) input terminal is connected to the other end of the capacitor 5; An operational amplifier 6 whose input terminal on the (+) side is grounded; a switch S3 connected between the output terminal of the operational amplifier 6 and the input terminal on the (-) side and whose on / off control is performed by the second clock φ2; , Connected in series to the output terminal of operational amplifier 6 And a flip-flop 8 having an output of the inverter 7 as a D input, a reverse phase clock 1 of the first clock φ1 as a clear input, and a Q output connected to an output terminal 9. I have.

In such a conventional comparator circuit, an SCF type LPF
Since the reference voltage of No. 2 is fixed, a DC offset voltage is generated by an operational amplifier (not shown) provided inside the SCF type LPF 2. Conventionally, even if this DC offset voltage is generated, it is supplied to the capacitor 5 and the operational amplifier 6 as it is.

[Problems to be solved by the invention]

The conventional comparator circuit described above has a drawback that the duty ratio of the output waveform is degraded when the DC offset voltage generated in the SCF LPF2 or the like becomes large because the reference voltage in the SCF LPF2 is fixed.

An object of the present invention is to provide a comparator circuit capable of adjusting the duty ratio of such an output waveform.

[Means for solving the problem]

The comparator circuit of the present invention is connected to a first input terminal to which an input signal is applied and controlled by a first clock to input the input signal when turned on, and a second switch grounded. A second switch that is connected to an input terminal and is controlled by a second clock that does not overlap with the first clock and that inputs a ground voltage when on, and is connected to the first and second switches; The SCF type low-pass filter controlled by the first and second clocks and third and fourth clocks having twice the frequency of the first and second clocks, and the low-pass filter First and second sample-and-hold circuits for sampling and holding an output with the first clock and the second clock, respectively; and the first and second sample-and-hold circuits. Third and fourth switches respectively connected to the first and second clocks and respectively controlled by the first and second clocks; a capacitor having one end commonly connected to the third and fourth switches; An operational amplifier having the other end connected to one input terminal and the other input terminal grounded, a fifth switch connected to the output terminal of the operational amplifier and the one input terminal and controlled by the second clock; An even number of inverters connected in series to the output terminal of the operational amplifier, and data output from the inverter as a data input and an output terminal connected to the output terminal, and cleared by a reverse phase clock of the first clock. Holding means, wherein the SCF type low-pass filter passes the input signal at the time of the first clock and the ground at the time of the second clock. By time division used to input and output pressure, configured to cancel the DC offset voltage at the operational amplifier.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are block diagrams of a comparator circuit for explaining one embodiment of the present invention.

As shown in FIG. 1 (a), this embodiment is connected to a first input terminal 1A for inputting a signal and receives a first clock φ1.
And a second switch S2 connected to a grounded second input terminal 1B and controlled by a second clock φ2 that does not overlap with the first clock φ1. , These first and second switches S1, S2
And controlled by first and second clocks φ1, φ2 and third and fourth clocks φ3, φ4 having twice the frequency of the first and second clocks φ1, φ2.
An SCF type LPF2 and an output of the LPF2 are supplied to a first clock φ1.
And the first and second S / H circuits 3, 4 respectively connected to the first and second S / H circuits 3, 4 for sampling and holding by the The third and fourth switches S3 and S4 controlled by the second clocks φ1 and φ2 respectively, the capacitor 5 having one end commonly connected to the third and fourth switches S3 and S4, and the other end of the capacitor 5 Connect to the (-) side input terminal and (+)
An operational amplifier 6 whose input terminal is grounded, and an operational amplifier 6
A fifth switch S5 connected to the output terminal of the operational amplifier 6 and the (−) side input terminal and controlled by the second clock φ2; an even number of inverters 7 connected in series to the output terminal of the operational amplifier 6; A data holding flip-flop 8 having an output as a D input and a Q output connected to an output terminal 9 is provided.

In such a comparator circuit, the SCF type LPF2 is time-division multiplexed. That is, at the time of the clock φ1, the signal from the first input terminal 1A is input and output via the sample and hold circuit 3, while at the time of the clock φ2, the reference voltage is input from the second input terminal 1B and the sample and hold circuit 4 Output through.

Here, as shown in FIG. 1 (b), the inside of the SCF type LPF2 has clocks φ3,
Time-division multiplexing is realized by driving with φ4. Therefore, both the signal path of input 1A and the signal path of input 1B are SCF type LPF2
Are the same as each other in the operational amplifier (not shown). That is, the input terminal is also
The same DC offset voltage can be generated for 1B.

In short, if the input signal at the clock φ1 is compared with the input reference voltage at the clock φ2 as in the comparator circuit shown in FIG. 1 (a), the influence is affected by the offset voltage of the operational amplifier constituting the preceding stage SCF type LPF2. The duty ratio of the output waveform in the comparator circuit can be adjusted.

〔The invention's effect〕

As described above, the comparator circuit of the present invention
A signal is input / output at the time of clock φ1 and the reference voltage is input / output at the time of clock φ2, and the SCF type LPF is used for time division multiplexing,
By inputting each output to the subsequent operational amplifier, the DC offset voltage of the operational amplifier constituting the SCF type LPF can be canceled, and the duty ratio of the output waveform can be adjusted.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are block diagrams and clock waveform diagrams of a comparator circuit for explaining an embodiment of the present invention, respectively, and FIGS. 2 (a) and 2 (b) are each a conventional example. FIG. 3 is a block diagram and a clock waveform diagram of a comparator circuit for performing the operation. 1A, 1B ... input terminal, 2 ... SCF type LPF, 3, 4 ... sample and hold circuit (S / H), 5 ... capacitor, 6 ... operational amplifier, 7 ... inverter, 8 ... flip-flop (FF), 9 ... output terminal, S1 to S5 ... switch, φ1 to
φ4, 1 ... clock.

Claims (1)

(57) [Claims] 1. A first switch connected to a first input terminal to which an input signal is applied and controlled by a first clock to input the input signal when turned on, and a second input terminal grounded A second switch that is connected to the first clock and that is controlled by a second clock that does not overlap with the first clock to input a ground voltage at the time of ON, and that is connected to the first and second switches and SCF controlled by first and second clocks and third and fourth clocks having twice the frequency of the first and second clocks
(Switched capacitor filter) type low-pass filter, and first and second sample-and-hold circuits for sampling and holding the output of the low-pass filter with the first clock and the second clock, respectively. Third and fourth switches respectively connected to the first and second sample and hold circuits and controlled by the first and second clocks, respectively;
A capacitor having one end commonly connected to the third and fourth switches, an operational amplifier having the other end of the capacitor connected to one input terminal, and the other input terminal grounded; an output terminal of the operational amplifier; A fifth switch connected to the input terminal of the operational amplifier and controlled by the second clock; an even number of inverters connected in series to an output terminal of the operational amplifier; an output of the inverter as a data input; Connected to a terminal, and including a data holding means that is cleared by a reverse phase clock of the first clock, wherein the SCF type low-pass filter passes the input signal at the time of the first clock, and By inputting / outputting the ground voltage at the time of the second clock and using time division,
A comparator circuit for canceling a DC offset voltage in the operational amplifier.