JPH0671194B2 - Switched Capacitor Filter - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a switched capacitor filter, more specifically, a switched capacitor filter added with the function of a prefilter without increasing the number of operational amplifiers. It is about.

[Technical background of the invention and its problems]

Since the switched capacitor filter is a kind of sampled data filter, a signal aliasing component is generated due to sampling, and this appears as a pseudo signal in the overband of the filter. In order to prevent this pseudo signal from occurring, it is necessary to remove the input signal having a frequency equal to or more than 1/2 of the sampling frequency in advance. Therefore, in the conventional switched capacitor filter, analog filters such as LC filter and RC active filter are added as pre-filters.

In this case, as the pass band of the switched capacitor filter approaches 1/2 of the sampling frequency, a pre-filter with a sharper cutoff characteristic is needed, but the LC filter has a large shape and can be integrated into an IC. Poor compatibility with switched capacitor filters, which are easy to replace. In addition, the RC active filter that can be integrated into an IC has a problem in terms of economical efficiency because the achievable accuracy of the RC element for obtaining a sharp cutoff characteristic is not sufficient with the current technology. Therefore, how to construct a switched capacitor filter that can simplify the analog prefilter is a serious problem.

To solve this problem, the clock signal frequency of the switched capacitor filter can be increased, but the time required to transfer the charge of the sampling capacitor to the integrating capacitor by the operation of the operational amplifier is reduced accordingly. Need to do so. For this purpose, the bandwidth of the operational amplifier must be increased in proportion to the increase of the clock signal frequency, which is not preferable in terms of circuit design and economically. Also, an increase in the clock signal frequency also requires an increase in the capacitance ratio of the capacitors used in the switched capacitor filter, so in order to maintain the required precision of the capacitance ratio, it is necessary to compare Requires a large capacitor and is economically unfavorable when integrated.

Conventionally, as a switched capacitor filter proposed to solve such a problem, there is one called a cosine filter that does not change a clock signal.
(Roubic Gregorian et al; “Switched-Capacitor De
cimation and Interpolation circuits "IEEE Trans.on
Circuits and Systems, Vo1.CAS-27, No.6, June 1980PP.5
09-514, JP-A-55-158725, and Roubic Greg
orian et al; “An Integrated Single-Chip PCM Voice
Codec With Filters, "IEEE Jour.of Solid-State Cirui
ts, Vol. SC-16 , No4August1981 P.327) The switched capacitor filters described in these documents are all equivalent to the ones in which a prefilter represented by the following equation is inserted.

H (Z) = [1 + Z ^−1/2 ] / 2 (1) Here, Z is a variable of conversion, and by ^setting Z = e ^jωT , H (Z) is a frequency for a sine wave with an angular frequency ω. Give a response. However, T is a sampling period. When this is calculated, | H (e ^{j ωT} ) | [{1 + _cos (ωT / 2)} ² +
_sin ² (ωT / 2)] ^1/2 / 2 ＝ ｜ _cos (ωT / 4) ｜… (2), It is a prefilter having an attenuation pole at a frequency of (n = 1,3,5,7 ...), That is, a frequency near an odd multiple of the sampling frequency. Therefore, by providing this pre-filter, the analog pre-filter provided in the preceding stage has only to sufficiently remove the input signal component having a frequency equal to or more than twice the sampling frequency, which simplifies the configuration. . However, in order to further simplify the configuration of the analog pre-filter, it is desired to remove folding components centered on not only an integer multiple of the sampling frequency but also an integer multiple of the frequency including even multiples. .

[Object of the Invention]

It is an object of the present invention to remove a folding component centered on an integer multiple frequency including not only a multiple of the sampling frequency but also an even multiple, and a switch which can greatly simplify an analog prefilter for removing the folding component. To provide a de-capacitor filter.

[Outline of Invention]

A switched capacitor filter according to the present invention includes an input stage in which four switched capacitors each having a capacitor of the same capacity, a sampling switch and a transfer switch are provided in parallel, a capacitor and a charging for the capacitor. Switched with a feedback circuit consisting of a discharge switch and a discharge switch
In order to sequentially sample the input signal charges in the capacitor integrator and each capacitor of the switched capacitors forming the input stage, the switch is performed by the first clock signal of four phases with a period T and a phase shift of T / 4. Means for operating the sampling switch of the switched capacitor, and a first clock for transferring the input signal charge sampled by each capacitor of the switched capacitors forming the input stage to the switched capacitor integrator. Means for operating the transfer switch of the switched capacitor, which does not operate the sampling switch, by means of the second clock signal having a cycle that is approximately 1/2 of the signal cycle T; and switching by means of the second clock signal.・ Operating the charging and discharging switches that make up the feedback circuit of the capacitor integrator ; And a stage, characterized by being configured to have a stop band in the first of said clock an integer multiple of the vicinity of the frequency of the frequency other than integral multiple of 4 times the frequency of the clock frequency of the clock signal.

This switched capacitor filter is typically A function equivalent to adding a prefilter represented by the transfer function is realized. Where N is the input stage switched
Since the number of capacitors is N = 4, the equation (3) is Becomes

Further, αk (k = 0 to 3) is a capacitance ratio between the capacitors of the input stage switched capacitors and the capacitors for integration of the switched capacitor integrators, and in this case, all have the same value.

〔The invention's effect〕

According to the present invention, it is possible to remove an integer multiple frequency excluding a specific integer of a sampling frequency and a component in the vicinity of the alias component due to sampling of an input signal, and an analog prefix for removing the alias component is that much. The filter structure is simplified.

Specifically, according to the switched capacitor filter of the present invention, an effect equivalent to that of the addition of the filter having an attenuation pole at a frequency that is an integral multiple of fs except 4 mfs (m is an integer) can be obtained. In this case, the analog pre-filter used in the preceding stage only needs to attenuate the aliasing component of the frequency of 4fs or more, which is very simple. Therefore, it is extremely effective in terms of filter structure and economical efficiency.

Furthermore, according to the present invention, the transfer of the signal charge from the input stage switched capacitor filter to the switched capacitor integrator is performed by a clock signal (second clock signal) having the same frequency as the operating frequency of the switched capacitor integrator. )
It is not necessary to increase the bandwidth of the operational amplifier used in the switched capacitor integrator.

Example of Invention

FIG. 1 is a circuit diagram showing the configuration of a switched capacitor filter according to an embodiment of the present invention. In the figure,
Reference numeral 10 is an input terminal, and 11 , 12 , 13 , and 14 are input stage switched capacitors provided in parallel for sampling the input signal to the input terminal 10. Each of the switches 1a to 1d is composed of a MOSFET or the like. , 2a to 2d, 3a to 3d, 4a to 4d, and MOS capacitors 1, 2, 3, and 4.

Incidentally, the switches 1a, 1d, 2a, 2d, 3a, 3d, 4a, 4d are sampling switches for sampling the input signal charges to the capacitors 1, 2, 3, 4 and also the switches 1b, 1c, 2b, 3c, 3
Reference numerals b, 3c, 4b, 4c are transfer switches for reading the input signal charges sampled in the capacitors 1, 2, 3, 4 and transferring them to the switched capacitor integrator in the subsequent stage.

These input stage switched capacitors 11 , 12 , 13 , 14
In the subsequent stage, a feedback switched capacitor 15 including switches 5a to 5d and a capacitor 5, and an integrating capacitor 6 are provided.
A switched capacitor integrator 16 constituted by the operational amplifier 7 is arranged, and the output of the integrator 16 is led to the output terminal 17.

The switches 5a and 5c are charging switches for charging the capacitor 5 with electric charges, and the switches 5b and 5d are discharging switches for discharging the electric charge of the capacitor 5.

The clock generator 18 is an input stage switched capacitor 11 ,
For transferring the first clock signals φ ₁ , φ ₂ , φ ₃ , φ ₄ for sampling 12 , 13 , 14 and the sampled input signal charge to the switched, capacitor integrator 16,
A second clock signal φ ₅ for operating the integrator 16,
₅ is generated.

That is, the switches 1a and 1d are driven by the clock signal φ ₁ .
The switches 2a and 2d are switched by the clock signal φ ₂ to the switch 3a.
And 3d by the clock signal φ ₃ and switches 4a and 4d by the clock signal φ ₄ by the switches 1b, 1c, 2b, 2c, 5b, 5d.
Is controlled by the clock signal φ5, and the switches 3b, 3c, 4b,
Opening and closing of 4c, 5a and 5c are controlled by a clock signal φ5. Here, as shown in the clock signal waveform in FIG. 2, the first clock signals φ ₁ , φ ₂ , φ ₃ , φ ₄ have a cycle of T, and the phases are sequentially shifted by T / 4. Also, the second
The clock signals phi _{5, 5} first clock signal phi _1, phi _2,
It has a cycle equal to φ ₃ and φ ₄ and is synchronized with them, but its duty is 1/2.

Next, the operation of this embodiment will be described. The input signal νin given to the input terminal 10 has a 1/4 cycle of the clock signal cycle T, and the switched capacitor 14 first supplies the clock signal φ ₄
Sampled by the
The capacitor 13 samples the clock signal φ ₃ . During this 1/2 cycle B, the clock signals φ ₂ and φ are switched by the switched capacitors 12 and 11 during the first 1/4 cycle and the latter 1/4 cycle of the preceding 1/2 cycle A, respectively. _The input signal charges sampled by ₁ are transferred to the integrating capacitor 6 by the clock signal ₅ , and at the same time, the feedback signal is switched by the clock signal _5.
The capacitor 5 of 15 is discharged. Then, during the subsequent 1/2 cycle C, the input signal charges sampled by the clock signals φ ₄ and φ ₃ by the switched capacitors 14 and 13 during the preceding 1/2 cycle B. integrating capacitor 6 between but is transferred by the clock signal phi ₅ to the integrating capacitor 6, and the capacitor 5 of the feedback switched capacitor 15 by the clock signal phi ₅ is an output terminal and the non-inverting input of the operational amplifier 7 Connected in parallel with. At the same time, as described above, in the 1/2 cycle C, the input signal charges are sampled by the switched capacitors 12 and 11 during the first 1/4 cycle and the latter 1/4 cycle, respectively.・
The capacitor 5 of the capacitor 15 is discharged. Thus 1
The operation in the clock signal cycle is completed.

In the above operation process, sampling or charge transfer is performed at the falling edge (shown by ↓) of the clock signal shown in FIG. Therefore, when the cycle of the clock signal is T, sampling is performed every T / 4.

The above operation of the switched capacitor filter of FIG. 1 can be expressed by the following equation.

C ₆ V _out = C ₆ Z ^-1 V _out -C ₅ V _out + [C ₁ Z ^-1 + C ₂ Z ^-5/4 + C ₃ Z
^−1/2 + C ₄ Z ^−3/4 ] V _in (4) Here, Z = e ^jωT , T is the period of the clock signal, and ω
Is the angular frequency, and C _{1 to} C ₆ are the electrostatic capacities of the capacitors 1 to 6, respectively. By rearranging the equation (4), the following equation is obtained.

V _out / V _in = Z ^−1/2 [C ₃ + C ₄ Z ^{− / 4} + C ₁ Z ^−1/2 + C ₂ Z
^−3/4 ] / [(C ₆ + C ₅ ) −C ₆ Z ⁻¹ ] (5) In FIG. 1, the switched capacitors 12 , 13 , and 14 are removed, and the switches 1a and 1d are replaced by the clock signal ₅ . ,switch
The circuit modified so that 1b and 1c are controlled to be opened and closed by the clock signal φ ₅ has the same configuration as a normal switched capacitor filter.

FIG. 3 is a circuit diagram showing the configuration of a normal switched capacitor filter obtained by modifying FIG. 1 as described above. In the same figure, each symbol represents the same as in FIG.

The transfer function of the switched capacitor filter of FIG. 3 can be expressed by the following equation.

V _out / V _in = Z ⁻¹ / ² · C ′ ₁ Z ^−1/2 [(C ₆ + C ₅ ) −C
₆ Z ⁻¹ ] (6) where C ′ ₁ is the capacitance of the capacitor 1 in FIG.

Equation (6) shows a low-pass characteristic. In equation (5)
When C ₁ = C ₂ = C ₃ = C ₄ = C _0/4 , and C ′ ₁ = C _{0 in the} equation (6), the following equations are obtained.

Therefore, under this condition, the switched
The transfer function of the capacitor filter multiplied by the transfer function K (Z) K (Z) = [Z ^1/2 + Z ^1/4 + 1 + Z ^−1/4 ] / 4 (7) This is the transfer characteristic of the switched capacitor filter obtained by this embodiment. The attenuation characteristic represented by the equation (7) is the clock signal frequency s of 4
It has an attenuation pole at an integer multiple of frequencies excluding the multiples of, and its vicinity is the stop band, near zero frequency and 4s, 8s, 12s, ...
The vicinity is the pass area. Therefore, such an attenuation characteristic can be utilized as a prefilter for removing the aliasing component of the switched capacitor filter as described above. That is, an ordinary switched capacitor of clock signal frequency s
If the input stage of the filter is replaced with a filter having the attenuation characteristic of equation (7), the frequency ks (k is an integer other than a multiple of 4) and the frequency components in the vicinity thereof are removed from the pass band. it can.

As is clear from the equation (5), in the configuration shown in FIG. 1, the values of the capacitors 5 and 6 do not appear in the numerator of the transfer function. That is, according to this embodiment, the conventional switched
It is possible to add the attenuation characteristics represented by the numerator of the equation (5) without impairing the characteristics of the capacitor filter.

Further, in this embodiment, the first clock signal, that is, the second clock signal
Since the charge of the switched capacitor, which has been sampled in advance, is simultaneously transferred to the integrating capacitor 6 by the second clock signal every 1/4 cycle of the clock signal of, the gain bandwidth product of the operational amplifier 7 is It may be the same as when the invention is not carried out.

As described above, the switched capacitor
It can be seen that the filter is equivalent to the filter shown in FIG. 3 to which the prefilter represented by the equation (7) is added. That is, in the ordinary switched capacitor filter shown in FIG.
Simply replace the capacitor with 4 pairs of capacitors whose capacitance value is 1/4, and change the clock signal for controlling the opening and closing of each switch to the above-mentioned first clock signal.
The apparent sampling frequency is quadrupled, and the sampling frequency of the original switched-capacitor filter does not change, and the prefilter having the characteristic of the transfer function expressed by the equation (7) is shown in FIG. It is obtained by superimposing on the characteristics of the switched capacitor filter of. Capacity value is 1/4
The reason for this is that the input signal is sampled four times in one cycle of the clock signal.

FIG. 4 shows the attenuation characteristics of the switched capacitor filter of the present invention obtained as described above. The figure shows the attenuation characteristics of a normal switched capacitor filter represented by the equation (6) ', and the low-pass characteristics are repeated at the same period as the frequency of the clock signal. This figure shows the attenuation characteristic of the prefilter expressed by equation (7).
Repeated every s. Is the attenuation characteristic of the switched capacitor filter according to the present invention shown in FIG. 1. Since this is the characteristic represented by the equation (5) ′,
Of the clock signal frequency s (= 1/1 / due to the effect of the prefilter described above.
T) 1,2,3,5,6,7,9,10 ... (sequence of integers excluding multiples of 4)
Since the doubled and near signals are rejected, their aliasing components do not occur in the passband.

As described above, the switched capacitor
According to the filter, the aliasing elimination analog filter placed before it is sufficient to provide sufficient attenuation to a signal having a frequency four times or more the clock signal frequency. Therefore, in the conventional switched capacitor filter, the clock frequency is reduced. As compared with the case where the above signal needs to be attenuated, the analog pre-filter for removing the aliasing component can be remarkably simplified. Moreover, since the necessary operational amplifiers can be those of the input part of the conventional switched capacitor filter, it is not necessary to substantially increase the number of operational amplifiers. Furthermore, in the present embodiment, the charge transfer from the modified input section is different from the conventional switched capacitor.
Since it is performed at the timing of the clock signal of the filter, that is, the second clock signal described above, it is not necessary to increase the bandwidth of the operational amplifier.

FIG. 5 is a circuit diagram showing the configuration of a switched capacitor filter according to another embodiment of the present invention. In this embodiment, the input stage switched capacitors 21 , 22 , 23 , 24 are two switches 1a, 1b, 2a, 2b, 3a, each of capacitors 1, 2, 3, 4 being provided.
It differs from the embodiment of FIG. 1 in that it is constructed by combining 3b, 4a and 4b. Here, the switch 1a uses the clock signal φ
₁ , the switch 2a is controlled by the clock signal φ ₂ , the switch 3a is controlled by the clock signal φ ₃ , and the switch 4a is controlled by the clock signal φ ₄ . The switches 1b and 2b are controlled by the clock signal ₅ , and the switches 3b and 4b are controlled by the clock signal φ ₅ . Furthermore,
The switches 5a, 2b, 5c and 5d are opened and closed in the same manner as in the embodiment shown in FIG. When the input stage switched capacitor is constructed as shown in FIG. 5, the polarities of the charges transferred to the integrating capacitor 6 are all opposite to those in the case of FIG. 1, so that the switch shown in FIG. The transfer function of the de-capacitor filter is the same as that of the equation (5) with a negative sign. Therefore, in the embodiment of FIG. 5, except that the phase of the output signal is opposite to that of the embodiment of FIG.
The effect is the same. Therefore, when the phase relationship between the input signal and the output signal is predetermined, it can be dealt with by properly using the embodiment of FIG. 1 and the embodiment of FIG. 5, which increases the degree of freedom in design. I can do things.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of a switched capacitor filter according to an embodiment of the present invention, FIG. 2 is a diagram showing the timing of each clock signal, and FIG. FIG. 4 is a circuit diagram of a switched capacitor filter of FIG. 4, FIG. 4 is a diagram showing an attenuation characteristic of the switched capacitor filter of the same embodiment, and FIG. 5 is a switched capacitor filter according to another embodiment of the present invention. It is a circuit diagram which shows the structure of a filter. 1,2,3,4,5,6 ... Capacitor, 1a, 1b, 1c, 1d, 2a, 2b, 2c, 2
d, 3a, 3b, 3c, 3d, 4a, 4b, 4c, 4d, 5a, 5b, 5c, 5d ... switch, 7 ... operational amplifier, 10 ... input terminal, 11 , 12 , 13 ,
14 , 21 , 22 , 23 , 24 …… Input stage switched capacitor, 15 …… Feedback switched capacitor, 16 …… Switched capacitor integrator, 17 …… Output terminal.

Claims (1)

[Claims] 1. An input stage in which four switched capacitors each having a capacitor of the same capacity, a sampling switch and a transfer switch are provided in parallel, a capacitor, a charging switch and a discharging switch for the capacitor. Switched with a feedback circuit consisting of
In order to sequentially sample the input signal charges in the capacitor integrator and each capacitor of the switched capacitors forming the input stage, the switch is performed by the first clock signal of four phases with a period T and a phase shift of T / 4. Means for operating the sampling switch of the switched capacitor, and a first clock for transferring the input signal charge sampled by each capacitor of the switched capacitors forming the input stage to the switched capacitor integrator. Means for operating the transfer switch of the switched capacitor, which does not operate the sampling switch, by means of the second clock signal having a cycle that is approximately 1/2 of the signal cycle T; and switching by means of the second clock signal.・ Operating the charging and discharging switches that make up the feedback circuit of the capacitor integrator A switched capacitor having a stop band near a frequency that is an integral multiple of the clock frequency other than an integral multiple of the four times the clock frequency of the first clock signal. ·filter.