JPH01253899A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To obtain a sample-hold circuit with comparatively good precision by using a voltage follower with high offset voltage. CONSTITUTION:The input of the voltage follower 6 is connected to a switch 1 and a capacitor 4, and the other end of the capacitor 4 is connected to reference potential and the output of other voltage follower 5 to which the reference potential is inputted through switches 2, 3. During a period I that the switch SW2 is ON and the switch SW3 is OFF, the switch SW1 is opened and closed so as to hold a signal to be impressed to an input terminal 7 in the capacitor 4. At that time, the voltage that the portion of the offset voltage of the voltage follower 5 is added to the reference potential is impressed to other end of the capacitor 4, and is held. Next, in the period II, SW2 turns to OFF, and SW3 turns to ON, and the SW3 side of the capacitor 4 comes to be the reference potential, and the voltage that the offset voltage of the voltage follower 5 is subtracted from an intrinsic input signal hold potential is impressed to the input of the voltage follower 6. By equalizing the offset voltage of the voltage followers 5, 6, the voltage of the intrinsic input signal is obtained from the voltage follower 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit that compensates for the offset voltage of a buffer circuit.

[Conventional technology]

An example of a conventional sample and hold circuit is a circuit as shown in FIG. An input signal from an input terminal 7 is held in a capacitor 4 through a switch 1, and is outputted from an output terminal 8 through a buffer circuit of a voltage follower circuit 6.

[Problem to be solved by the invention]

In the conventional sample and hold circuit described above, in order to accurately output the potential held by the capacitor 4,
An operational amplifier with negative feedback is required as the voltage follower circuit 6 of the buffer circuit. This circuit has the problem of oscillation when the load is capacitive, and the problem of increased power loss due to the flow of bias current. Such problems become particularly important when an integrated circuit is constructed by arranging a large number of sample and hold circuits in parallel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sample and hold circuit that can solve these problems and compensate for offset voltage.

[Means to solve the problem]

The configuration of the present invention is such that one end of the capacitor and the input end of the first voltage follower are connected through a first switch circuit that connects and disconnects the input signal, and an output signal is taken out from the first voltage follower. In the hold circuit, a reference potential is input to compensate for the offset voltage of the first voltage follower, and a second voltage follower having the same characteristics as the voltage follower, and an output of the second voltage follower and the reference It is characterized by comprising second and third switch circuits connected to the other end of the capacitor by alternately switching the potential.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the input of the voltage follower 6 is connected to one end of the switch 1 and the capacitor 4, and the other end of the capacitor 4 is connected to the reference potential and the output of another voltage follower 5 to which the reference potential is input through the switch 2.3. It is connected.

This circuit is controlled by a timing diagram as shown in FIG. During timing period ■, switch 2 is turned on.
, the switch 3 is OFF, and the signal applied to the input terminal is held in the capacitor 4 by turning the switch 1 ON-OFF during this period. At this time, a voltage added to the reference potential by the offset voltage of the voltage follower circuit 5 is applied to the other end of the capacitor 4 and held.

Next, during the timing period ■, the switch 2 is turned off and the switch 3 is turned on. At this time, the potential on the switch 3 side of the capacitor 4 becomes the reference potential, and a voltage obtained by subtracting the offset voltage of the voltage follower 5 from the original input signal hold potential is applied to the input of the voltage follower 6.

Therefore, voltage follower 5 and voltage follower 6
If the offset voltage characteristics are made equal, the voltage follower 6 outputs the potential of the original input signal.

FIG. 3 is a circuit diagram of a specific example of this embodiment, in which switches 1 to 3
is constructed from MOS transistors, and voltage followers 5 and 6 are constructed from MOS transistors Q+ and Q+o and low current sources rl and IIO.

FIG. 4 shows another specific example of this embodiment, in which a plurality of hold circuits 2
This is an example in which 1 to 2n are configured. In this case, a buffer amplifier 10 is used for the output of the switch 2.3, and this buffer amplifier 10 consists of a capacitor C41~4°, a switch Stt~S+-, a transistor Qtl"-Qln+low current source 111~I1t+ n hold circuits 2
1 to 2a are connected.

FIG. 5 is a circuit diagram of another embodiment of the present invention, in which the output of a voltage follower for offset voltage correction is input to an inverting amplifier 11, inverted with respect to the reference potential, and then passed through a switch 3 to a capacitor 4. It is designed to connect to.

With this configuration, one end of the capacitor 4 is connected to a reference potential with low impedance during the sampling period (temporary operation), so it is possible to hold the sample even if the sampling period is short, and high-speed operation is possible. It has characteristics.

〔Effect of the invention〕

As explained above, the present invention can configure a relatively accurate sample and hold circuit using a voltage follower with a large offset voltage. Therefore, especially when using a large number of sample and hold circuits in parallel, the operational amplifier is used as a voltage follower as in the past.

Compared to using a
Since the configuration of each voltage follower is much simpler, the circuit can be configured compactly.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams and waveform diagrams of one embodiment of the sample hold circuit of the present invention, FIGS. 3 and 4 are circuit diagrams showing two specific examples of the present embodiment, and FIG. 5 is a circuit diagram of a second embodiment of the present invention, and FIG. 6 is a circuit diagram of an example of a conventional sample and hold circuit. 1-3...Switch, 4...Capacitor, 5,6...
... Voltage follower, 7... Input terminal, 8...
Output terminal, 9...Load low current source, 10...Buffer amplifier, 11...Inverting amplifier, 21-2n...Hold circuit.

Claims (1)

[Claims] In the sample hold circuit, which connects one end of the capacitor and the input end of the first voltage follower through a first switch circuit that connects and disconnects the input signal, and takes out the output signal from the first voltage follower, A second voltage follower is inputted so as to compensate for the offset voltage of the first voltage follower and has the same characteristics as this voltage follower, and the output of this second voltage follower and the reference potential are alternately switched. and second and third switch circuits connected to the other end of the capacitor.