JPH0149056B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an improvement of a cascade type A/D converter.

[Prior art]

FIG. 1 shows a 1-bit A/D converter used in a conventional cascade type A/D converter. Input signal V _IN
is applied to input terminal 1, sample and hold circuit (hereinafter referred to as S/H circuit) 2 samples and holds the signal.
The held voltage V _H (V _IN ) and the reference voltage V _R /2 are compared in a comparator circuit 3 . V _H
When <V _R /2, the output V _OD of the comparison circuit 3 becomes a low level (L), and the switch S1 is closed and switch S2 is opened, and the operational amplifier 4 outputs V _OA =2V _H =2V _IN .
When V _H > V _R /2, the output V _OD of the comparator circuit 3 becomes high level (H), the switch S1 is opened, the switch S2 is closed, and the operational amplifier 4 outputs V _OA = 2V _H −V _R = 2V _IN −V _R
Output. FIG. 2 illustrates the relationship between the residual output V _OA from the operational amplifier 4 and the input signal V _IN . That is, the input signal V _IN is compared with the reference voltage V _R /2, 1-bit conversion is performed, and the "remainder" from the comparison voltage is output. If multiple stages of 1-bit A/D converters shown in Figure 1 are connected in cascade and the remainder output of the previous stage is used as the input of the latter stage, the combination of 1-bit outputs (comparison outputs) from each stage will be the A/D converter of multiple bits. /D
Configure conversion output.

However, in the case of a 1-bit A/D converter as shown in Figure 1, the offsets of the S/H circuit 2, comparator circuit 3, and operational amplifier 4, and the on-resistances of switches S1 and S2 are all dependent on the A/D converter. This is a factor that limits accuracy. For this reason, it has the disadvantage that good performance cannot be obtained without using complex and expensive components, and it is difficult to implement it into an IC. /D converters have not been put into practical use until now.

〔the purpose〕

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to realize a cascade type A/D converter with a simple configuration, good performance, and easy integration into an IC.

[Summary] In order to achieve the above object, the first gist of the present invention is to provide an A/D converter that compares an input voltage with a reference voltage and generates a comparison output and a residual output. is applied to one end of the first switch, a first capacitor to which the other end of the first switch is connected to one end;
The second terminal connected between the other end of the capacitor and the common
a third switch connected between one end of the first capacitor and a reference voltage; a second capacitor, one end of which is connected in relation to one end of the first capacitor; an inverting amplifier whose input terminal is connected to the other end of the capacitor;
a fourth switch connected between the input terminal and the output terminal of the inverting amplifier; a fifth switch connected between the output terminal of the inverting amplifier and one end of the second capacitor; and an output terminal of the inverting amplifier. a sixth capacitor connected between the terminal and the other end of the first capacitor;
The switch sequentially generates three sections using a clock signal, and in the first section, the first and fourth switches are turned on to charge the second capacitor with a voltage corresponding to the input voltage, and the second capacitor is charged with a voltage corresponding to the input voltage. 2nd in the section of
A third switch is turned on to charge the first capacitor with a reference voltage to generate a comparison output from the inverting amplifier, and in a third period, a fifth switch is generated corresponding to the comparison output.
Alternatively, the present invention resides in a 1-bit A/D converter characterized in that the sixth switch is turned on to generate a residual output from an inverting amplifier.

The second gist of the present invention is that, in an A/D converter that compares an input voltage with a reference voltage and generates a comparison output and a residual output, a first switch to which the input voltage is applied to one end; , a first capacitor to which the other end of the first switch is connected to one end; a second switch connected between the other end of the first capacitor and the common; and one end of the first capacitor; a third switch connected between the reference voltages; a second capacitor, one end of which is connected in relation to one end of the first capacitor, and an input terminal of the second capacitor connected to the other end of the second capacitor; an inverting amplifier; a fourth switch connected between the input terminal and the output terminal of the inverting amplifier; a fifth switch connected between the output terminal of the inverting amplifier and one end of the second capacitor; a sixth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor; the switch generates three sections in sequence according to the clock signal; Turn on the switch and charge the second capacitor with a voltage corresponding to the input voltage,
In the second period, the second and third switches are turned on to charge the first capacitor with the reference voltage to generate a comparison output from the inverting amplifier, and in the third period, the fifth or third switch is turned on corresponding to the comparison output. A plurality of 1-bit A/D conversion circuits configured to generate a residual output from an inverting amplifier by turning on the sixth switch are connected in cascade, and the residual output of each stage is used as the input voltage of the next stage.
The present invention relates to an A/D converter characterized in that it is configured to generate a multi-bit digital output based on comparison outputs generated from each stage.

[Explanation of Examples]

The present invention will be explained below using the drawings. FIG. 3 is an electrical circuit diagram showing one embodiment of the present invention, which is a 1-bit A/D converter. 11 is analog input signal
An input terminal to which V _IN is applied, S11 is a first switch whose one end is connected to this input terminal 11, C
1 is a first capacitor whose one end is connected to the other end of this switch S11, S12 is a second switch whose one end is connected to the other end of this capacitor C1, and whose other end is connected to a common, and S13 is the above-mentioned switch. One end is connected to the other end of S11, and the other end is the reference voltage.
A third switch is connected to terminal 12 to which V _R /2 is applied, C2 is a second capacitor whose one end is connected to the other end of the switch S11, and 13 is a second capacitor whose other end is connected to its input terminal. For example, a CMOS inverter can be used as an inverting amplifier. S14 is the inverting amplifier 13
a fourth switch connected to the output terminal and the input terminal of the inverting amplifier 13; R1 and R2 are resistors of equal value connected to the output terminal of the inverting amplifier 13 to divide the output; S16 is the resistor R1 and R2; A sixth switch S15 is a fifth switch connected to the connection point of the resistors R1 and R2 and one end of the capacitor C1. 14 is switch S11, S14
15 is a clock input terminal to which clock CP2 for controlling switches S12 and S13 is applied. 16 is a clock input terminal to which clock CP3 is applied. 17 is the clock input terminal for this clock CP3. A D-type flip-flop (hereinafter referred to as D-type F.F.) takes the comparison output from the inverting amplifier 13 as its D input, and 18 receives the inverted output of this D-type F.F and the clock CP3 as its input and outputs it. 19 is the non-inverting output of this D-type FF and the above-mentioned clock.
Use CP3 as input and add output to switch S16
It is an AND circuit. 20 is an output terminal for sending the output from the inverting amplifier to the outside.

In addition, the above switches S11 to S16, D type F.
F17 and AND circuits 18 and 19 constitute a switch means for switching the connection state of the 1-bit A/D conversion circuit.

Next, the operation of this circuit will be explained. The entire circuit is the fourth
It is driven by three-phase clocks CP1 to CP3 shown in the figure.

In the first period T1 in which the clock CP1 becomes H, the switches S11 and S14 are closed and the other switches are open. When the switch S14 is closed, the input and output terminals of the inverting amplifier 13 have a constant value V _OFF.
(Offset voltage of operational amplifier, threshold voltage of inverter, etc.) Therefore, capacitor C2 is charged with voltage V _IN -V _OFF between terminals.

In the second period T2 when the clock CP2 goes high, only the switches S12 and S13 are closed. At this time, C1 is charged to the reference voltage V _R /2, and the input voltage Vx of the inverting amplifier 13 becomes Vx = V _R /2 - V _IN +V _OFF . Since the switch S14 is open, the inverting amplifier 13 acts as a comparator and the input voltage
When Vx is higher than V _OFF , that is, if V _R /2>V _IN , the comparison output of the inverting amplifier 13 becomes L, and in the opposite case, it becomes H, and a 1-bit A/D conversion output is obtained.

In the third period T3 when the clock CP3 goes high, only one of the switches S15 and S16 is closed. The comparison output from the operational amplifier 13 in section T2 is transferred to the output side of the D-type F/F17 at the rising edge of the clock CP3, and when the comparison output is L, S15 is closed and when the comparison output is H, S16 is closed. In both cases, Vx
= V _OFF and equilibrium is reached. That is, when the comparison output is L, the output Vo of the inverting amplifier 13 becomes Vo=2V _IN because Vx=Vo/2-(V _IN -V _OFF )=V _OFF . On the other hand, when the comparison output is H, Vx=Vo/2+V _R /2-(V _IN -V _OFF )=V _OFF , so Vo=2V _IN -V _R and a remainder output is obtained.

As is clear from the relationship shown above, by adopting such a configuration, it is possible in principle to eliminate the influence of offset on the A/D conversion output and the remainder output. Furthermore, since the system uses a capacitor, no current flows in a balanced state, so there is no error caused by the on-resistance of the switch. Also S/
The configuration is simple because the H circuit, comparison circuit, arithmetic operation circuit, etc. are implemented with a single inverting amplifier.
Furthermore, the main parts of the circuit are just an analog switch, an inverter, a small capacitor, and a pair of resistors with the same resistance value, so it does not require any particularly high-performance elements, making it suitable for IC implementation.

In the circuit shown in FIG. 3, when the capacitor C2 is charged by the input signal, the charging time becomes longer if the signal source impedance is high. In order to improve this point, a buffer B (not shown) may be inserted at point P in FIG. 3 and its output may be applied to the capacitor C2. In this case, the offset of buffer B can be considered similar to the offset of inverting amplifier 13, and the advantages of offset cancellation can be maintained.

FIG. 5 shows a second embodiment of the present invention, in which four A/D converters shown in FIG. 3 are connected in series to form a 4-bit A/D converter. That is, 31 to 34 are the 1-bit A/D converters shown in FIG. 3, and the signal input V _IN is added as the input V _IN1 of the A/D converter 31 in the first stage, and the remainder of the A/D converters in each stage is The output is the signal input for the next stage. 6th
As shown in the figure, by applying the clocks CP1 to CP3 to the A/D converters 31 to 34 with their phases shifted, high-speed traveling wave conversion is possible. 41-5
0 is a D-type FF for holding and transferring the A/D conversion output from each stage, and 1 from the A/D converter 31.
The bit A/D conversion output is D at CP3 timing.
D is held by each clock.
The data is transferred to the F/F42, 44, and 47 one after another. A/D conversion outputs from A/D converters 32, 33, and 34 in other stages are transferred in the same manner, and finally outputs D3, D2, 4 bits A/ as D1 and D0
A D-converted output can be obtained.

By adopting such a configuration, in addition to producing the same advantages as in the case of FIG. 3, it is possible to increase the number of bits of the A/D conversion output, that is, the accuracy.

Although the above embodiment shows the case where four stages of 1-bit A/D converters are used, the present invention is not limited to this, and it is also possible to further increase the number of stages.

In addition, the accuracy of A/D conversion in this case is 2 for each stage.
Since it is determined only by matching two resistors (R1 and R2 in FIG. 3) and matching between each stage is not necessary, it is easy to improve accuracy.

In addition, D type F/F41, 43, 4 in Fig. 5
6 and 50 can also be used for the D-type F/F (for example, 17 in FIG. 3) included in the A/D converters 31 to 34 of each stage.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a cascade type A/D converter with a simple configuration, good performance, and easy integration into an IC.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing a conventional cascade type A/D converter, FIG. 2 is a time chart for explaining the operation of the circuit in FIG. 1, and FIG. 3 is an electrical circuit diagram showing an embodiment of the present invention. 4 is a time chart for explaining the operation of the circuit shown in FIG. 3, FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG.
The figure is a time chart for explaining the operation of FIG. 13...Inverting amplifier, 31-34...1 bit A/
D converter, C1, C2...capacitor, S11~S
16...Switch, V _IN , V _IN1 to V _IN4 ...Input signal,
V _R /2...Reference voltage, Vo, Vo ₁ ~ _{Vo 4} ...Remainder output,
Do~D ₃ ...1 bit output.

Claims (1)

[Claims] 1. In an A/D converter that compares an input voltage with a reference voltage and generates a comparison output and a residual output, the input voltage is applied to one end of a first switch; a first capacitor to which the other end of the switch is connected, a second switch connected between the other end of the first capacitor and common, and a voltage between one end of the first capacitor and a reference voltage; a second capacitor, one end of which is connected to one end of the first capacitor; an inverting amplifier, the input terminal of which is connected to the other end of the second capacitor; a fourth switch connected between the input terminal and the output terminal of the inverting amplifier; a fifth switch connected between the output terminal of the inverting amplifier and one end of the second capacitor; and an output terminal of the inverting amplifier. and a sixth switch connected between the other end of the first capacitor, the clock signal generates three sections in sequence, and in the first section, the first and fourth switches are turned on and input. A voltage corresponding to the voltage is charged to the second capacitor, and in the second period, the second and third switches are turned on to charge the reference voltage to the first capacitor, and a comparison output is generated from the inverting amplifier. 3
The fifth or sixth output corresponds to the comparative output in the interval of
1. A 1-bit A/D converter, characterized in that the 1-bit A/D converter is configured to generate a residual output from an inverting amplifier when a switch is turned on. 2. In an A/D converter that compares an input voltage with a reference voltage and generates a comparison output and a residual output, the input voltage is applied to one end of a first switch, and the other end of this first switch is connected to the first switch. a first capacitor connected to one end; a second switch connected between the other end of the first capacitor and common; and a third switch connected between one end of the first capacitor and a reference voltage. a second capacitor whose one end is connected to one end of the first capacitor; an inverting amplifier whose input terminal is connected to the other end of the second capacitor; and an input terminal of the inverting amplifier. a fourth switch connected between the output terminals of the inverting amplifier; a fifth switch connected between the output terminal of the inverting amplifier and one end of the second capacitor; and a fifth switch connected between the output terminal of the inverting amplifier and the first capacitor. and a sixth switch connected between the other ends of the switch, which sequentially generates three sections according to the clock signal, and turns on the first and fourth switches in the first section to generate a voltage corresponding to the input voltage. The second capacitor is charged, and in the second period, the second and third switches are turned on to charge the first capacitor with the reference voltage, and a comparison output is generated from the inverting amplifier.
The fifth or sixth output corresponds to the comparative output in the interval of
A plurality of 1-bit A/D conversion circuits configured to generate a residual output from an inverting amplifier by turning on a switch are connected in cascade, and the residual output of each stage is used as the input voltage of the next stage, which is generated from each stage. An A/D converter characterized in that it is configured to generate a multi-bit digital output based on a comparison output.