JPH02264458A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH02264458A
JPH02264458A JP1086015A JP8601589A JPH02264458A JP H02264458 A JPH02264458 A JP H02264458A JP 1086015 A JP1086015 A JP 1086015A JP 8601589 A JP8601589 A JP 8601589A JP H02264458 A JPH02264458 A JP H02264458A
Authority
JP
Japan
Prior art keywords
lead frame
soldering
heat dissipating
chip
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1086015A
Other languages
Japanese (ja)
Inventor
Yoshihiko Hirata
善彦 平田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1086015A priority Critical patent/JPH02264458A/en
Publication of JPH02264458A publication Critical patent/JPH02264458A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:Not only to protect a chip against cracks but also to enable the fixing of an external heat dissipating fin to a lead frame by a method wherein one or more partially bent leads are led out of a sealing resin just under a semiconductor chip. CONSTITUTION:Heat dissipating leads 7 and a soldering groove 6 are formed at a time by bending a monolithic lead frame. Therefore, a soldering part 8 becomes small in size, so that solder is prevented from spreading over all the semiconductor chip 2 even if solder molten by heating is applied onto the soldering part 8, and consequently partial soldering can be realized. By this setup, a chip is protected against cracks even if a copper lead frame is employed. Moreover, if the heat dissipating leads 7 are exposed out of a resin 5, they serve as a heat dissipating fin, whereby a package can be made low in thermal resistance.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はリードフレームの改良、特に、パッケージの
低熱抵抗化に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to improvements in lead frames, and particularly to lower thermal resistance of packages.

〔従来の技術〕[Conventional technology]

第4図は例えば実囲昭63−134552号に示された
リードフレームの載置台部付近の上面図であり、(1)
はチップ載置台、(8月よはんだ付は部である。チップ
載置台(1ンの材質としては銅合金、鉄合金などを使用
している。第5図は第4図のリードフレームを用いて完
成した半導体装置の側面図である。
FIG. 4 is a top view of the vicinity of the mounting table of the lead frame shown in, for example, No. 63-134552, and (1)
is a chip mounting table (August 2013). The material used for the chip mounting table (1) is copper alloy, iron alloy, etc. Figure 5 shows the lead frame shown in Figure 4. FIG.

図において、(2)は半導体チップ、(3)は配線用金
線、(4)は外部リード、(5)は樹脂である。
In the figure, (2) is a semiconductor chip, (3) is a gold wire for wiring, (4) is an external lead, and (5) is a resin.

次に動作について説明する。Next, the operation will be explained.

チップ載置台(1)上のはんだ付は部(8)に加熱溶融
したはんだをつけ、その上に半導体チップ(2)を載せ
はんだ付けを行い、半導体チップ(2)をチップ載置台
(1)に固定する。その後、半導体チップ(2)から外
部リード(4)への配線用金線(3)をボンディングし
、それを樹脂(5)により封止し製品を製作する。
For soldering on the chip mounting table (1), apply heated and melted solder to the part (8), place the semiconductor chip (2) on top of it, perform soldering, and place the semiconductor chip (2) on the chip mounting table (1). Fixed to. Thereafter, gold wires (3) for wiring are bonded from the semiconductor chip (2) to external leads (4), and this is sealed with resin (5) to produce a product.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のリードフレームは以上のように構成されていたの
で、半導体チップサイズが大きいときは銅合金リードフ
レームと半導体チップの熱膨張率が違い過ぎるためはん
だ付は時にチップ割れが生ずる問題があり、鉄合金リー
ドフレームしか使用できなかった。一方、鉄合金フレー
ムは、銅合金リードフレームと比べ高価であること、熱
伝導率が小さいため、半導体チップの消費電力による半
導体チップ温度上昇係数である熱抵抗が大きい問題があ
った。
Conventional lead frames were constructed as described above, but when the semiconductor chip size is large, the coefficient of thermal expansion between the copper alloy lead frame and the semiconductor chip is too different, which sometimes causes chip cracking during soldering. Only alloy lead frames could be used. On the other hand, since iron alloy frames are more expensive than copper alloy lead frames and have lower thermal conductivity, they have a problem in that they have a higher thermal resistance, which is the coefficient of temperature rise of the semiconductor chip due to the power consumption of the semiconductor chip.

この発明は上記のような問題点を解消するためになされ
たもので、チップ割れを防止し、外部放熱フィンを取り
付は可能にした安価な銅合金リードフレームを得ること
を目的とする。
This invention was made to solve the above problems, and aims to provide an inexpensive copper alloy lead frame that prevents chip cracking and allows attachment of external heat dissipation fins.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るリードフレームは1枚成形で部分はんだ
付は用の溝と放熱用のリードを同時に備えるようにした
ものである。
The lead frame according to the present invention is molded in one piece and is simultaneously provided with grooves for partial soldering and leads for heat dissipation.

〔作用〕[Effect]

この発明における放熱用リードにより、低熱抵抗化を実
現でき、部分はんだ付は用溝によりはんだ付けは中央部
分のみで行われるため、チップ割れを防止でき、大きい
半導体チップであっても低熱抵抗の銅合金リードフレー
ムを使用できる。
The heat dissipation leads of this invention can achieve low thermal resistance, and since partial soldering is done only in the center using grooves, chip cracking can be prevented, and even with large semiconductor chips, low thermal resistance Alloy lead frame can be used.

〔実施例〕 以下、この発明の一実施例を図について説明する。第1
図はリードフレームのチップ載置台部付近の上面図、第
2図は第1図の側面図、第3図は第1図のリードフレー
ムを用いて完成した半導体装置の側面図である。図にお
いて、(1)〜(5)、(8)は従来のものと同等であ
るので説明を省略する。(6)は部分はんだ付は用溝、
(7)は放熱用リードである。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
2 is a side view of FIG. 1, and FIG. 3 is a side view of a semiconductor device completed using the lead frame of FIG. 1. In the figure, (1) to (5), and (8) are the same as the conventional one, so their explanations will be omitted. (6) is a groove for partial soldering;
(7) is a heat radiation lead.

次に動作について説明する。Next, the operation will be explained.

リードフレームの放熱用リード(7)を第1図及び第2
図に示すように1枚構造のリードフレームから折り曲げ
ることにより放熱用リード(7)と部分はんだ付は用溝
(6)を同時に形成する。したがってはんだ付は部(8
)は小さくなり、ここに加熱溶融したはんだを付けても
半導体チップ(2)全体に広がらず、部分はんだ付けが
可能になる。これにより銅合金リードフレームであって
もチップ割れの問題が防止できる。
The heat dissipation leads (7) of the lead frame are shown in Figures 1 and 2.
As shown in the figure, heat dissipation leads (7) and partial soldering grooves (6) are simultaneously formed by bending a single lead frame. Therefore, the soldering is part (8
) becomes small, and even if heated and molten solder is applied thereto, it will not spread over the entire semiconductor chip (2), making partial soldering possible. This can prevent the problem of chip cracking even with copper alloy lead frames.

更に放熱用リード(7)を樹脂(5ンの外に出せば放熱
フィンとして利用でき、パッケージの低熱抵抗化が可能
になる。
Furthermore, if the heat dissipation leads (7) are exposed outside the resin (5), they can be used as heat dissipation fins, making it possible to lower the thermal resistance of the package.

また、この放熱用リード(7)はグランドピンに利用す
ることが可能である。
Further, this heat dissipation lead (7) can be used as a ground pin.

なお、上記実施例では部分はんだ付は用溝(6)が2個
所のものを示したが、これは1個又は3個以上設けても
よい。
In the above embodiment, the partial soldering grooves (6) are shown in two places, but one or more grooves (6) may be provided.

また、上記実施例では放熱用リード(7)をく(矩)形
に折り曲げた場合について説明したが、放熱用リード(
7)は樹脂(5)外に出ておればどのような形状でも、
上記実施例と同様の効果を奏する。
In addition, in the above embodiment, the heat dissipation lead (7) was bent into a rectangular shape, but the heat dissipation lead (7) was bent into a rectangular shape.
7) can be of any shape as long as it is outside the resin (5).
The same effects as in the above embodiment are achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば一枚構造のリードフレ
ームを折り曲げるように構成したので、安価で、パッケ
ージ熱抵抗の低いものが得られる効果がある。
As described above, according to the present invention, since the single-piece lead frame is configured to be bent, it is possible to obtain an inexpensive package with low thermal resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるリードフレームのチ
ップ載置台部付近の上面図、第2図は第1図の側面図、
第3図は第1図のリードフレームを用いて完成した半導
体装置の側面図、第4図は従来のリードフレームのチッ
プ載置台部付近の上面図、第5図は第4図のリードフレ
ームを用いて完成した半導体装置の側面図である。 図において、(1)はチップ載置台、(2)は半導体チ
ップ、(3)は配線用金線、(4)は外部リード、(5
)は樹脂、(6)は部分はんだ付は用溝、(7)は放熱
用リー〆、(8)ははんだ付は部である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a top view of the vicinity of a chip mounting table of a lead frame according to an embodiment of the present invention, FIG. 2 is a side view of FIG. 1,
FIG. 3 is a side view of a semiconductor device completed using the lead frame shown in FIG. FIG. 2 is a side view of a semiconductor device completed using the method. In the figure, (1) is a chip mounting table, (2) is a semiconductor chip, (3) is a gold wire for wiring, (4) is an external lead, and (5) is a semiconductor chip.
) is a resin, (6) is a groove for partial soldering, (7) is a heat dissipation lee, and (8) is a soldering part. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] チップ載置台上の搭載半導体チップ直下において、一部
を折り曲げたリードを少なくとも1つ以上有し、樹脂封
止後、該リードの少なくとも1つ以上が樹脂外部に出て
いることを特徴とするリードフレーム。
A lead having at least one partially bent lead directly below a mounted semiconductor chip on a chip mounting table, and at least one of the leads protruding outside the resin after resin sealing. flame.
JP1086015A 1989-04-04 1989-04-04 Lead frame Pending JPH02264458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1086015A JPH02264458A (en) 1989-04-04 1989-04-04 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1086015A JPH02264458A (en) 1989-04-04 1989-04-04 Lead frame

Publications (1)

Publication Number Publication Date
JPH02264458A true JPH02264458A (en) 1990-10-29

Family

ID=13874849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1086015A Pending JPH02264458A (en) 1989-04-04 1989-04-04 Lead frame

Country Status (1)

Country Link
JP (1) JPH02264458A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998013866A1 (en) * 1996-09-24 1998-04-02 Siemens Aktiengesellschaft Connecting frame of microelectronic component, manufacturing process, and the microelectronic component encompassing same
US6297074B1 (en) * 1990-07-11 2001-10-02 Hitachi, Ltd. Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297074B1 (en) * 1990-07-11 2001-10-02 Hitachi, Ltd. Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof
WO1998013866A1 (en) * 1996-09-24 1998-04-02 Siemens Aktiengesellschaft Connecting frame of microelectronic component, manufacturing process, and the microelectronic component encompassing same

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