JPH10200023A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH10200023A JPH10200023A JP9001104A JP110497A JPH10200023A JP H10200023 A JPH10200023 A JP H10200023A JP 9001104 A JP9001104 A JP 9001104A JP 110497 A JP110497 A JP 110497A JP H10200023 A JPH10200023 A JP H10200023A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- chip
- die pad
- semiconductor device
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スイッチング電源
用のパワーデバイスなどの用途に用いる半導体装置とし
て、リードフレームに２素子のパワー半導体素子を搭載
し、その周域を樹脂封止して組立てたデュアル素子のＳ
ＯＰ（Small Outline Package)モールド型半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a power device for a switching power supply or the like, in which two power semiconductor elements are mounted on a lead frame and the periphery thereof is sealed with a resin. Dual element S
The present invention relates to an OP (Small Outline Package) molded semiconductor device.
【０００２】[0002]
【従来の技術】まず、頭記した半導体装置として、パワ
ー半導体素子にＩＧＢＴ（絶縁ゲート型バイポーラトラ
ンジスタ）を用いたデュアル素子ＳＯＰモールド型半導
体装置の従来における組立構造を図２に示す。図におい
て、１はリードフレーム、２はリードフレーム１に搭載
したパワー半導体素子、３は内部配線用のボンディング
ワイヤ、４は樹脂パッケージである。ここで、リードフ
レーム１には、僅かな裁断間隙を隔てて左右に並ぶ一対
のダイパッド１ａと、左右に並ぶダイパッド１ａを挟ん
でその両側に配列した外部リード１ｂ（コレクタ端
子），１ｃ（エミッタ端子），１ｄ（ゲート端子）が形
成されている。なお、周知のように、リードフレームは
図示されていないタイバー，ガイドレールと組み合わせ
て前記したパターンをプレス加工により帯状の金属製リ
ボンに打ち抜いて形成される。2. Description of the Related Art First, as a semiconductor device described above, FIG. 2 shows a conventional assembly structure of a dual element SOP mold type semiconductor device using an IGBT (insulated gate bipolar transistor) as a power semiconductor element. In the figure, 1 is a lead frame, 2 is a power semiconductor element mounted on the lead frame 1, 3 is a bonding wire for internal wiring, and 4 is a resin package. Here, the lead frame 1 has a pair of die pads 1a arranged on the left and right with a slight cutting gap therebetween, and external leads 1b (collector terminals) and 1c (emitter terminals) arranged on both sides of the die pads 1a arranged on the left and right. ), 1d (gate terminal). As is well known, the lead frame is formed by stamping the above-described pattern into a band-shaped metal ribbon by press working in combination with a tie bar and a guide rail (not shown).
【０００３】そして、半導体装置を組立てるには、まず
リードフレーム１に形成した左右のダイパッド１ａの上
にコレクタ電極面を重ね合わせてパワー半導体素子２の
チップを１個ずつ振り分けて半田マウントし、続いてダ
イパッド１ａとコレクタ端子の外部リード１ｂとの間，
およびパワー半導体素子２とエミッタ端子の外部リード
１ｃ，ゲート端子の外部リード１ｄとの間にワイヤ３を
ボンディングし、さらにトランスファモールド法により
樹脂パッケージ４を成形した後、リードフレームをタイ
バーカットして製品が完成する。In order to assemble the semiconductor device, first, the collector electrode surfaces are superimposed on the left and right die pads 1a formed on the lead frame 1, the chips of the power semiconductor elements 2 are sorted and solder mounted one by one. Between the die pad 1a and the external lead 1b of the collector terminal,
A wire 3 is bonded between the power semiconductor element 2 and the external lead 1c of the emitter terminal and the external lead 1d of the gate terminal, and further, a resin package 4 is formed by a transfer molding method. Is completed.
【０００４】[0004]
【発明が解決しようとする課題】ところで、前記した従
来のパワー半導体装置では、ＩＣパッケージ用のリード
フレームと同様なリードフレームを採用しており、その
リードフレームは全面域が平坦面で、かつダイパッドと
各外部リードとの間が切り離されており、パワー素子の
チップ搭載したダイパッドとコレクタ外部リードとの間
をボンディングワイヤ接続している。そのために、組立
性，および放熱性の面で次記のような問題点がある。By the way, in the above-mentioned conventional power semiconductor device, a lead frame similar to a lead frame for an IC package is employed, and the lead frame has a flat surface over its entire surface and a die pad. And each external lead is separated, and a bonding wire connection is made between the die pad on which the power element chip is mounted and the collector external lead. Therefore, there are the following problems in terms of assemblability and heat dissipation.
【０００５】１）図３で示すように、左右のダイパッド
１ａに振り分けてパワー半導体素子２のチップを半田マ
ウントする際に、溶融半田がダイパッドの面上を流動し
て左右広がり、このために半田がダイパッド１ａの側縁
からはみ出して、左右に並ぶダイパッド１ａの間が半田
５でブリッジしてしまう欠陥が生じ易い。そこで、従来
ではチップを半田マウントする際に、半田量を少な目に
調整してダイパッド相互間での半田ブリッジの発生を防
ぐようにしているが、半田量を減らすとダイパッド／チ
ップ間の接合強度が弱くなり、ヒートサイクルなどで熱
応力が繰り返し加わると、チップの半田接合面が剥離す
るなどして製品の信頼性が低下する。1) As shown in FIG. 3, when the power semiconductor element 2 chip is solder-mounted while being distributed to the left and right die pads 1a, the molten solder flows on the surface of the die pad and spreads right and left. Is protruded from the side edge of the die pad 1a, and a defect in which the solder 5 bridges between the die pads 1a arranged on the left and right easily occurs. Therefore, in the past, when soldering a chip, the amount of solder was adjusted to a small amount to prevent the occurrence of solder bridges between the die pads. However, when the amount of solder is reduced, the bonding strength between the die pad and the chip is reduced. When the thermal stress is repeatedly applied in a heat cycle or the like, the reliability of the product is reduced due to the peeling of the solder joint surface of the chip.
【０００６】２）パワー半導体装置では、パワーチップ
の発生熱を効率よく放熱する必要があるが、従来のリー
ドフレーム１では、ダイパッド１ａと各外部リード１ｂ
との間が切り離されていて、両者間がボンディングワイ
ヤ３で相互接続されているだけであり、かつダイパッド
１ａの周域は樹脂パッケージ４で封止されているため
に、外部リード１ｂを通じての外部への放熱が殆ど期待
できない。2) In the power semiconductor device, it is necessary to efficiently radiate the heat generated from the power chip. In the conventional lead frame 1, the die pad 1a and each external lead 1b are required.
Are separated from each other, only the two are interconnected with the bonding wire 3, and the peripheral area of the die pad 1 a is sealed with the resin package 4. Heat can hardly be expected.
【０００７】本発明は上記の点にかんがみなされたもの
であり、リードフレームを用いて組立てた頭記したデュ
アル素子のＳＯＰモールド型半導体装置を実施対象に、
前記課題を解決して組立性，および放熱性の改善を図っ
た半導体装置を提供することを目的とする。The present invention has been made in view of the above points, and is intended to be applied to a dual element SOP molded semiconductor device described above assembled using a lead frame.
It is an object of the present invention to provide a semiconductor device which solves the above-mentioned problems and improves assemblability and heat dissipation.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、リードフレームに２素子のパワー
半導体素子を搭載して組立てた樹脂封止型の半導体装置
で、左右に並べてリードフレームに形成した一対のダイ
パッドにそれぞれパワー半導体素子のチップを半田マウ
ントしたものにおいて、次記のように構成するものとす
る。According to the present invention, there is provided a resin-encapsulated semiconductor device in which two power semiconductor elements are mounted on a lead frame and assembled. A power semiconductor element chip is solder-mounted on a pair of die pads formed on a lead frame, respectively, and has the following configuration.
【０００９】１）左右に並ぶ一対のダイパッドについ
て、各ダイパッドの対向側縁に沿ってチップマウント側
に向けて起立する側壁部を形成するものとし、その側壁
部を、リードフレームをプレス加工で打ち抜き形成する
際に同時形成する。上記構成のリードフレームを採用す
ることにより、リードフレームのダイパッドにチップを
半田マウントする際に、ダイパッドごとにその側縁に起
立形成した側壁部が溶融半田の広がりを阻止する仕切り
壁の役目を果たし、半田量を少な目に調整する必要なし
に、ダイパッド相互間で半田ブリッジが生じるのを確実
に防止することができる。1) With respect to a pair of die pads arranged on the left and right sides, side walls which stand toward the chip mount side are formed along opposing side edges of each die pad, and the side walls are punched by a lead frame by press working. Simultaneously formed when forming. By adopting the lead frame of the above configuration, when the chip is solder-mounted on the die pad of the lead frame, the side wall portion formed on the side edge of each die pad serves as a partition wall for preventing the spread of the molten solder. In addition, it is possible to reliably prevent the occurrence of a solder bridge between the die pads without having to adjust the amount of solder to a small amount.
【００１０】２）左右に並ぶ各ダイパッドごとにダイパ
ッドとその外部リードを一体に連結してリードフレーム
に形成する。この構成により、ダイパッド，およびダイ
パッドに連ねて樹脂パッケージから外方に引出した外部
リードを伝熱経路として、パワー半導体素子の発生熱を
外部へ効率よく放熱させることができる。2) For each die pad arranged on the left and right, the die pad and its external lead are integrally connected to each other to form a lead frame. With this configuration, the heat generated by the power semiconductor element can be efficiently radiated to the outside by using the die pad and the external lead drawn out of the resin package in connection with the die pad as a heat transfer path.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施例を図１(a),
(b) に基づいて説明する。なお、実施例の図中で図２に
対応する同一部材には同じ符号が付してある。すなわ
ち、図１の実施例では、リードフレーム１のダイパッド
１ａとその外部リード１ｂ（パワー半導体素子２がＩＧ
ＢＴである場合にはコレクタ端子の外部リード、ＭＯＳ
ＦＥＴである場合にはドレイン端子の外部リード）とが
一体に連結されており、かつ各ダイパッド１ａごとに、
互いに向かい合う側縁に沿ってチップマウント側に向け
て立ち上がる側壁部１ａ-1が形成されている。この側壁
部１ａ-1は、金属リボンからリードフレーム１を打ち抜
くプレス加工の際に、同時にプレス金型による剪断，押
し曲げ加工でダイパッド１ａの対向側縁に沿って形成す
るものとする。なお、側壁部１ａ-1の起立角度は、プレ
ス金型の打ち抜き角度に合わせて直角，ないし直角に近
い鋭角に形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to FIGS.
Explanation will be made based on (b). In the drawings of the embodiment, the same members corresponding to FIG. 2 are denoted by the same reference numerals. That is, in the embodiment of FIG. 1, the die pad 1a of the lead frame 1 and its external leads 1b (the power semiconductor element 2 is IG
If BT, external lead of collector terminal, MOS
In the case of an FET, an external lead of a drain terminal) is integrally connected, and for each die pad 1a,
Sidewall portions 1a-1 are formed along the side edges facing each other to rise toward the chip mount side. The side wall portion 1a-1 is formed along the opposing side edge of the die pad 1a by shearing and pressing with a press die at the same time when the lead frame 1 is punched from a metal ribbon. The upright angle of the side wall 1a-1 is formed at a right angle or an acute angle close to the right angle in accordance with the punching angle of the press die.
【００１２】かかる構成のリードフレーム１を採用する
ことにより、リードフレーム１のダイパッド１ａにパワ
ー半導体素子２のチップを半田マウントする際に、半田
５が前記した側壁部１ａ-1で側方への広がりが阻止され
る。これにより、図３で述べたようなダイパッド相互間
の半田ブリッジの発生が確実に防げる。また、半導体装
置の通電に伴う半導体チップの発生熱はダイパッド１
ａ，およびダイパッド１ａと一体に連なった外部リード
１ｂを伝熱して効率よく外部に熱放散される。By employing the lead frame 1 having such a configuration, when the chip of the power semiconductor element 2 is mounted on the die pad 1a of the lead frame 1 by solder, the solder 5 is directed laterally at the side wall 1a-1. Spread is prevented. Thereby, the occurrence of the solder bridge between the die pads as described with reference to FIG. 3 can be surely prevented. The heat generated by the semiconductor chip due to the energization of the semiconductor device is controlled by the die pad
a, and the external leads 1b integrated with the die pad 1a are transferred to the outside and heat is efficiently radiated to the outside.
【００１３】[0013]
【発明の効果】以上述べたように、本発明の構成によれ
ば、リードフレームにおける左右一対のダイパッドに対
して、その対向側縁に側壁部を起立形成したことによ
り、各ダイパッドにパワー半導体素子のチップを半田マ
ウントする際に不要な溶融半田の側方への広がりを阻止
して、ダイパッド間に半田ブリッジが生じるのを確実に
防ぐことができる。As described above, according to the structure of the present invention, the pair of left and right die pads in the lead frame are formed with the side walls standing on the opposite side edges, so that the power semiconductor element is provided in each die pad. When the chip is solder-mounted, unnecessary molten solder is prevented from spreading to the side, so that the occurrence of a solder bridge between the die pads can be surely prevented.
【００１４】また、各ダイパッドごとに、ダイパッドと
該ダイパッドに接続する外部リードを一体に連結したリ
ードフレームを用いることにより、ダイパッドと外部リ
ードを切り離した従来構造と比べてチップ素子の発生熱
に対する放熱性の向上が図れる。Further, by using a lead frame in which a die pad and an external lead connected to the die pad are integrally connected to each die pad, heat radiation to the heat generated from the chip element can be reduced as compared with the conventional structure in which the die pad and the external lead are separated. Performance can be improved.
【図１】本発明の実施例によるデュアル素子のＳＯＰモ
ールド型半導体装置の組立構成図であり、(a) は平面
図、(b) は(a) の矢視Ｘ−Ｘ断面図1A and 1B are assembly configuration diagrams of a dual-element SOP molded semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX of FIG.
【図２】デュアル素子のＳＯＰモールド型半導体装置を
対象とした従来構成の平面図FIG. 2 is a plan view of a conventional configuration for a dual-element SOP molded semiconductor device.
【図３】図２の構成でリードフレームのダイパッド上に
チップを半田マウントした際に生じる半田ブリッジの発
生状況を表した図FIG. 3 is a diagram showing a state of occurrence of a solder bridge generated when a chip is solder-mounted on a die pad of a lead frame in the configuration of FIG. 2;
１ リードフレーム １ａ ダイパッド １ａ-1 側壁部 １ｂ〜１ｄ 外部リード ２ パワー半導体素子 ４ 樹脂パッケージ ５ 半田 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Die pad 1a-1 Side wall part 1b-1d External lead 2 Power semiconductor element 4 Resin package 5 Solder
Claims (3)
子を搭載して組立てた樹脂封止型の半導体装置であり、
左右に並べてリードフレームに形成した一対のダイパッ
ドに振り分けてパワー半導体素子のチップを半田マウン
トしたものにおいて、前記ダイパッドの対向側縁に沿っ
てチップマウント側に向けて起立する側壁部を形成した
ことを特徴とする半導体装置。1. A resin-sealed semiconductor device in which two power semiconductor elements are mounted on a lead frame and assembled.
In the case where the chip of the power semiconductor element is solder-mounted by distributing it to a pair of die pads formed on the lead frame side by side, the side wall standing up toward the chip mount side is formed along the opposite side edge of the die pad. Characteristic semiconductor device.
パッドの側壁部を、リードフレームをプレス加工で打ち
抜き形成する際に同時形成したことを特徴とする半導体
装置。2. The semiconductor device according to claim 1, wherein the side wall of the die pad is formed simultaneously with the punching of the lead frame by press working.
イパッドごとにダイパッドとその外部リードを一体に連
結してリードフレームに形成したことを特徴とする半導
体装置。3. The semiconductor device according to claim 1, wherein a die pad and an external lead are integrally connected to each other for each die pad to form a lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00110497A JP3519229B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00110497A JP3519229B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10200023A true JPH10200023A (en) | 1998-07-31 |
| JP3519229B2 JP3519229B2 (en) | 2004-04-12 |
Family
ID=11492185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00110497A Expired - Lifetime JP3519229B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3519229B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7982293B2 (en) | 2006-11-06 | 2011-07-19 | Infineon Technologies Ag | Multi-chip package including die paddle with steps |
| US8304902B2 (en) | 2010-03-23 | 2012-11-06 | Sanken Electric Co., Ltd. | Semiconductor device |
| JP2017191895A (en) * | 2016-04-14 | 2017-10-19 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298723A (en) * | 2015-05-13 | 2017-01-04 | 无锡华润安盛科技有限公司 | A kind of twin islet lead frame framework |
-
1997
- 1997-01-08 JP JP00110497A patent/JP3519229B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7982293B2 (en) | 2006-11-06 | 2011-07-19 | Infineon Technologies Ag | Multi-chip package including die paddle with steps |
| US8304902B2 (en) | 2010-03-23 | 2012-11-06 | Sanken Electric Co., Ltd. | Semiconductor device |
| JP2017191895A (en) * | 2016-04-14 | 2017-10-19 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3519229B2 (en) | 2004-04-12 |
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