JPH02264455A - Semiconductor device - Google Patents

Abstract

PURPOSE:To secure a wiring region for the modification of a circuit so as to protect a functional block independent of the circuit modification against variation in characteristics by a method wherein two or more spare active element regions are disposed in an active element region, and a wiring is provided between the spare regions respectively. CONSTITUTION:A spare active element region composed of spare active element groups 50-55 is provided to an active element region composed of logically effective active elements 1-6. Wirings 201-203 between the element groups 50-55 are provided to the wiring region where wirings 101-104 of the effective active elements are built. By this setup, a wiring region required for the modification of a circuit can be secured, so that not only a design load induced by the substantial modification of a layout can be reduced but also a functional block directly independent of the modification of a circuit can be prevented from varying in characteristic.

Description

[Detailed description of the invention] [Industrial application field 1 The present invention relates to a semiconductor device.

[Summary of the Invention J] In the present invention, active elements having various logical functions are formed in a row? ! In a semiconductor integrated device comprising a number of active element regions and a wiring region interconnecting inputs and outputs of the active elements, a plurality of preliminary active element regions each consisting of a group of preliminary active elements are arranged within the active element region, By having wiring in the wiring area that connects the spare active element areas to each other, the wiring area is secured when changing the circuit, reducing various design loads caused by major layout changes, and further improving functions that are not directly related to circuit changes. This prevents changes in block characteristics.

[Prior Art] In a conventional semiconductor integrated device comprising a plurality of active element regions in which active elements having various logical functions are formed in rows, and a wiring region interconnecting inputs and outputs of the active elements, Active elements that are not actually logically used have been placed as spare active elements for various purposes. Typical examples of this purpose are to respond to circuit changes due to circuit defects after prototype evaluation in a short delivery time, and to create another semiconductor device by changing part of the circuit as a master slice. . For this purpose, a preliminary active element group is placed in an appropriate area, a transistor area is secured, and only the wiring layer is changed as necessary.

[Problems to be Solved by the Invention] In recent years, in the semiconductor device layout process, so-called automatic placement and wiring programs that automatically perform the placement and wiring of active elements have become mainly used. As the above-mentioned program progresses, the wiring efficiency increases, and the wasted area in the wiring area is significantly reduced. For this reason, even if only preliminary active elements are included, it has become extremely difficult to change the wiring area for actual use.

FIG. 4 shows a configuration diagram of a conventional embodiment.

11.12.13.14.15.16 are logical valid active elements, and 60.61.62.16 are indicated by hatching.
63, 64, and 65 are preliminary active element groups. In general, the preliminary active element group is arranged in a post-layout process, so it is often placed at the right or left end of the active element row.
, 112, 113, and 114 are wirings between effective active elements. In addition, an actual semiconductor device includes power supply wiring, an IO cell as an interface for signals with the outside, etc., but these are all omitted here. Since there is no wiring in the spare active element part, the wiring area will only have the necessary space for logically valid wiring, and as mentioned above, wiring between the spare active elements will be attempted later. becomes extremely difficult. For this reason, if you try to wire a spare active element, you will have to change the active wiring that has already been routed or move the position of the effective active element itself, and due to changes in wiring capacitance, etc., the characteristics will change and cause malfunction. It could also be the case.

[Means for Solving the Problems J] In the semiconductor integrated device of the present invention, a plurality of spare active element areas each consisting of a group of spare active elements are arranged within the active element area, and wiring between original active elements is automatically routed. At the same time, actually effective wiring and preliminary wiring are placed in the wiring area by automatically wiring wiring that interconnects the preliminary active element areas. In addition, here, spare active elements are expressed as active elements in the sense of contrasting with wiring areas, so even in areas that do not include transistors such as pull-up or pull-down elements, they can be arranged in the same row as the active element area. This shall include everything located in. Similarly, a stopper region (diffusion region) disposed in the active element region is also included.

[Implementation example 1] FIG. 1 is a block diagram of an embodiment of the present invention.

l, 2.3.4.5.6 are logically valid active elements. 50, 51, 52, 53, 54, 55 are preliminary active element groups, and each preliminary active element group includes one or more active elements therein. Here, the preliminary active element groups are placed at both ends of the array of active elements. 101, 102, 103, 104 show wiring between normal effective active elements, 201, 202, 203 show wiring between spare active element groups in the present invention, 203 shows an example of wiring on the same active element column 201 and 202 are examples of wiring in different active element columns. 201 and 202 use not only the wiring space in the horizontal direction but also the wiring possible area inside the effective active element to secure the wiring space in the vertical direction.

FIG. 2 is a block diagram of another embodiment of the present invention. 7
．． 8 is a logically effective active element, and 9 is a logically effective block cell such as a memory. 56.57.5
8 is a preliminary active element group similar to that in FIG. 1, and 205 is a group of 5
This is a spare wiring between the 6 spare active element groups and the invalid input/output of the 9 valid block cells. In this way, the method of the present invention can also be applied to setting temporary input/output terminals in valid block cells and wiring them in order to secure wiring space. Further, 105 is wiring between effective active elements and effective block cell input/output. Reference numeral 204 denotes a preliminary wiring between preliminary active element groups similar to that shown in FIG.

FIG. 3 shows an embodiment of the preliminary active element group according to the present invention, and 300, 301, 302, and 303 surrounded by broken lines are each cell of the preliminary active element group, and specifically, 300 is a pull-up resistor. , 301 is a NAND gate, 302 is a flip-flop circuit with reset, and 303 is a buffer, which are common active elements. 401 and 402 are wirings that connect the preliminary active elements. What should be noted here is that even in a bistable circuit like the 302, by keeping the reset terminal active, the internal state is uniquely determined just by the wiring between the preliminary active element groups, and the current is stable. There is no problem with sexuality either. In the conventional method of arranging spare active elements, the input gate would float and become unstable, and to prevent this, it was necessary to cut the wiring that serves as a path between the power supplies inside the active element cell.
In the method of the present invention, the input gate can be fixed, and troublesome processing inside the cell is not required. Also, in relation to FIG. 1 which is an embodiment of the present invention, the preliminary active element group of 52.53 corresponds to the preliminary active elements of 300.301° and 302.303, and as an example, 52 and 300 are 30 to 53 again
When 1,302.degree. 303 preliminary active element groups are made to correspond, the preliminary wiring 203 in FIG. 1 corresponds to 401 in FIG. 3. 402 and 403 are wiring lines within the 53 spare active element groups. In FIG. 1, the wiring within this spare active element group is not shown, but this wiring can also be used as a spare wiring to secure a space in the wiring area.

[Effects of the Invention 1 As described above, according to the above structure of the present invention, by providing the wiring that connects the spare active element regions to each other in the wiring region, it is possible to secure the wiring area when changing the circuit. Therefore, it is possible to reduce various design burdens caused by major layout changes associated with circuit changes, and to shorten delivery times by smoothly changing only the wiring layer.Furthermore, it is possible to reduce the design burden caused by major layout changes associated with circuit changes, and to shorten delivery times by smoothly changing only the wiring layer. It has the effect of preventing changes in characteristics.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention. FIG. 2 is a configuration diagram of another embodiment of the present invention. FIG. 3 is an embodiment diagram of a preliminary active element group according to the present invention. FIG. 4 is a configuration diagram of a conventional embodiment. that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (and 1 other person) Group

Claims (1)

[Claims] In a semiconductor integrated device consisting of a plurality of active element regions in which active elements having various logical functions are formed in rows, and a wiring region that interconnects inputs and outputs of the active elements, there is a pre-active element region within the active element region. 1. A semiconductor device, wherein a plurality of preliminary active element regions each consisting of a group of elements are arranged, and the wiring region has wiring for interconnecting the preliminary active element regions.