JPH02262356A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02262356A JPH02262356A JP1085017A JP8501789A JPH02262356A JP H02262356 A JPH02262356 A JP H02262356A JP 1085017 A JP1085017 A JP 1085017A JP 8501789 A JP8501789 A JP 8501789A JP H02262356 A JPH02262356 A JP H02262356A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- lead
- semiconductor chip
- semiconductor device
- shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 230000008054 signal transmission Effects 0.000 claims abstract description 5
- 239000012212 insulator Substances 0.000 claims abstract 3
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関するものであり、特に、半
導体チップの実装に用いられるリードの形状に特徴を持
たせた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the shape of a lead used for mounting a semiconductor chip has a characteristic feature.
(従来の技術〕
突起1極(以下バンプという)とリードを利用しT:、
半導体チップの従来の実装例を図を用いて説明する。(Conventional technology) Using one protruding pole (hereinafter referred to as bump) and a lead, T:
An example of conventional mounting of a semiconductor chip will be explained using the drawings.
第6図はTAB法により実装された半導体チップの斜視
図である。図中、1は能動機能を持つ半導体チップであ
り、該半導体チップl上にバンプ2が設けられている。FIG. 6 is a perspective view of a semiconductor chip mounted by the TAB method. In the figure, reference numeral 1 denotes a semiconductor chip having an active function, and bumps 2 are provided on the semiconductor chip l.
バンプ2は半導体チップlとリード3をI!電気的機械
的に接続するためのものである。バンプ2とリード3を
用いたこのような実装方法をT A B (Tape
ムutomated Bonding)と呼んでいる。Bump 2 connects semiconductor chip l and lead 3 to I! It is for electrical and mechanical connection. This mounting method using bumps 2 and leads 3 is called T A B (Tape
It is called mutomated bonding.
バンプ2とり−ド3とのボンディングを行なえば、半導
体チップ1の持つ能動機能をり一部3に取り出すことが
可能となる。従って、例えば外部端子と電気的に配線さ
れているパッドを有する絶縁基板上に、該リード3を例
えば半田付は等の方法により接続Tることによって、こ
の実装化された半導体チップは・半導体チップlの能動
機能を外部端子によって取り出すことのできる半導体装
置として取り扱うことが可能となる。By bonding the bumps 2 and the leads 3, it becomes possible to take out the active function of the semiconductor chip 1 in a portion 3. Therefore, by connecting the leads 3, for example, by soldering, on an insulating substrate having pads that are electrically wired to external terminals, the mounted semiconductor chip can be made into a semiconductor chip. It becomes possible to treat the device as a semiconductor device whose active function can be taken out by an external terminal.
最適の半導体チップにおいては、例えばゲートアレイ等
の論理LSI等の信号ビンが増加する傾向にある。従っ
て、それらの半導体チップは、信号ピンに相当するバン
プ数を増加するために、第7図イ、口に示すようにバン
プピンチを縮少しバンブ寸法を縮少するなどの手段をと
っていtoこのように第7図イのものから口のようにバ
ンプに対応するリードの幅やピッチも縮少下ることによ
り・第8図イから口のようにボンディングの状態もかわ
り、密度の高い半導体装置となる。In optimal semiconductor chips, the number of signal bins such as logic LSIs such as gate arrays tends to increase. Therefore, in order to increase the number of bumps corresponding to signal pins, these semiconductor chips take measures such as reducing the bump pinch and bump dimensions as shown in Figure 7A. As shown in Figure 7A, the width and pitch of the leads corresponding to the bumps are reduced, and the bonding conditions change, as shown in Figure 8A, resulting in higher density semiconductor devices. Become.
(発明が解決しようとする課題〕
ところが、リードピッチを縮少するのはリード間隔も小
さくなることになり、クロストーク2考慮すると困難な
面がある。丁なわち、リード間隔が小さいと隣接リード
の電流が流れることによって生ずる電界の影響を受けや
すくなり、ノイズを受けやすいという欠点があった。第
9図イ、口はこのような関係を示すもので、口の状態で
はクロストークが発生する。なお、7は電界を示してい
る。(Problem to be Solved by the Invention) However, reducing the lead pitch also reduces the lead spacing, which is difficult when considering crosstalk 2. In other words, if the lead spacing is small, adjacent leads It has the disadvantage that it is easily influenced by the electric field generated by the flow of current, and is susceptible to noise. Figure 9 A shows this relationship, and in the mouth state, crosstalk occurs. Note that 7 indicates an electric field.
この発明は上記のような問題点を解消するためになされ
たもので、信号ビンの増II′0に伴なうり一1’1f
Jj隔m少に対してもクロストークの心配がない半導体
装置を得ようとするものである。This invention was made to solve the above-mentioned problems.
The present invention aims to provide a semiconductor device free from crosstalk even when the Jj spacing is small.
この発明に係る半導体装置のリードの形状は、信号を伝
えるための導体の周辺を絶縁膜で覆い、更にその外(!
!Iにシールド用導体を設けたことを特徴としている。The shape of the lead of the semiconductor device according to the present invention is such that the periphery of the conductor for transmitting signals is covered with an insulating film, and the outside (!
! It is characterized in that a shielding conductor is provided at I.
この発明における半導体装置では、リード間隔が縮少し
てもリードに設けられたシールド用導体のためにクロス
トークの心配がなくなる。In the semiconductor device according to the present invention, even if the lead spacing is reduced, there is no fear of crosstalk because of the shielding conductor provided on the leads.
以下、この発明の一実施例を図2用いて説明する。第1
図イはリードの外観を示す斜視図、口は正面図、ハは断
面側面図である0本発明に係る半導体装置のり一部3は
、信号を伝えるための導体6の周囲に絶縁膜4を設け、
更にその周囲にシールドするための導体5を設けたもの
である。An embodiment of the present invention will be described below with reference to FIG. 1st
Figure A is a perspective view showing the external appearance of the lead, the opening is a front view, and Figure C is a cross-sectional side view. In the semiconductor device glue part 3 according to the present invention, an insulating film 4 is formed around a conductor 6 for transmitting signals. established,
Furthermore, a conductor 5 for shielding is provided around it.
第2図に本発明ご用いた隣接しタリードの電界を示す慨
念断面図を示す。このように、シールド用導体5が周囲
にあるため、信号伝達用導体には電界7が入りこまず、
従って、クロストークの心配はなくなる0
第8図に本発明を適用したリード3とノ寸ンブ2とをボ
ンディングしrJljl断面図を示す。図示のように、
信号伝達用導体6とバンプ2を接合することにより、半
導体チップ1の持つ能動機能?リード3に取り川下こと
が可能となる。FIG. 2 shows a conceptual cross-sectional view showing the electric field of adjacent tally leads used in the present invention. In this way, since the shield conductor 5 is around, the electric field 7 does not enter the signal transmission conductor.
Therefore, there is no need to worry about crosstalk. FIG. 8 shows a cross-sectional view of the bonding between the lead 3 and the sleeve 2 to which the present invention is applied. As shown,
By joining the signal transmission conductor 6 and the bump 2, the active function of the semiconductor chip 1 can be achieved. It becomes possible to take lead 3 and move downstream.
なお、上記実施例で&et最外周がシールド用導体5で
あったか、取り扱い号便利にするために、第4図に示す
ように、シールド用導体5の更に最外周に絶縁膜4を設
けてもよい。また、第8図に不すようにバンプ2とリー
ド3の接合部はシールドされていなかったか、第6図に
示すように、ノくンプ2とリード3の接合部近傍にまで
シールド部分5を伸ばしてもよい。In the above embodiment, the outermost periphery of the shielding conductor 5 was the shielding conductor 5, but for convenience, an insulating film 4 may be provided on the outermost periphery of the shielding conductor 5, as shown in FIG. . Also, as shown in FIG. 8, the junction between bump 2 and lead 3 was not shielded, or as shown in FIG. You can stretch it out.
以上のように、本発明を用いれば、たとえ隣接リード間
隔が狭くてもクロストークの心配のない半導体装置を得
るごとができる0As described above, by using the present invention, it is possible to obtain a semiconductor device free from crosstalk even if the spacing between adjacent leads is narrow.
第1図はこの発明の一実施例の要部であるリードを示す
もので、イは斜視図、口は正面図、ハは断面側面図、第
2図はこの発明の一実施例の動作説明用の概念図、第8
図はこの発明の一実施例のリードをバンプにボンディン
グした状態の断面側面図、第4図はこの発明の他の実施
例におけるリードを示す斜視図、第5図はこの発明の他
の実施例の要部を示す断面側面図、第6図は従来の半導
体装置を示す斜視図、第7図はその動作?説明すち二め
の正面断面図、第8図は同じく動作説明用の斜視図、第
9因は同じく動作説明用の概念図である。
図中、lは半導体チップ、2はバンプ、3はリード、4
は絶縁膜、5はシールド用導体、6は信号伝達用導体で
ある。
代理人 大 岩 増 雄
ク
ド
第1図
第4図
第5図
、3
第2図
′\7
戸
l、゛ す涌イネ+ツフ。
第6図
第7図
(ロ)
÷−七一乞汀
第8図
第91Fig. 1 shows a lead which is a main part of an embodiment of this invention, A is a perspective view, the opening is a front view, C is a cross-sectional side view, and Fig. 2 is an explanation of the operation of an embodiment of this invention. Conceptual diagram for
The figure is a cross-sectional side view of a lead in one embodiment of this invention bonded to a bump, FIG. 4 is a perspective view showing a lead in another embodiment of this invention, and FIG. 5 is another embodiment of this invention. FIG. 6 is a perspective view showing a conventional semiconductor device, and FIG. 7 shows its operation. The second front sectional view for explanation, FIG. 8 is a perspective view for explaining the operation, and the ninth factor is a conceptual diagram for explaining the operation. In the figure, l is a semiconductor chip, 2 is a bump, 3 is a lead, and 4 is a semiconductor chip.
5 is an insulating film, 5 is a shield conductor, and 6 is a signal transmission conductor. Agent Masu Oiwa Okudo Figure 1 Figure 4 Figure 5, 3 Figure 2'\7 Door l, ゛ Suwa rice + Tsufu. Figure 6 Figure 7 (b) ÷ - Seventy one figure Figure 8 Figure 91
Claims (1)
信号として出力するための突起電極と、該半導体チップ
を駆動するための電力を取り入れるための突起電極と、
上記突起電極とプリント基板等の半導体チップ被装着物
の端子とを電気的、機械的に接続する導体から成るリー
ドを有する半導体装置において、上記リードが、信号伝
達用導体と、その外周の絶縁体と、更に外側のシールド
用導体から成ることを特徴とする半導体装置。A semiconductor chip having an active function, a protruding electrode for outputting the active function as an electrical signal, and a protruding electrode for taking in electric power for driving the semiconductor chip;
In a semiconductor device having a lead made of a conductor that electrically and mechanically connects the protruding electrode and a terminal of a semiconductor chip mounted object such as a printed circuit board, the lead includes a signal transmission conductor and an insulator on its outer periphery. and an outer shielding conductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1085017A JPH02262356A (en) | 1989-04-03 | 1989-04-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1085017A JPH02262356A (en) | 1989-04-03 | 1989-04-03 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02262356A true JPH02262356A (en) | 1990-10-25 |
Family
ID=13846970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1085017A Pending JPH02262356A (en) | 1989-04-03 | 1989-04-03 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02262356A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563135A (en) * | 1991-08-29 | 1993-03-12 | Kawasaki Steel Corp | Lead frame with protective element |
JP2010153579A (en) * | 2008-12-25 | 2010-07-08 | Denso Corp | Lead frame |
-
1989
- 1989-04-03 JP JP1085017A patent/JPH02262356A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563135A (en) * | 1991-08-29 | 1993-03-12 | Kawasaki Steel Corp | Lead frame with protective element |
JP2010153579A (en) * | 2008-12-25 | 2010-07-08 | Denso Corp | Lead frame |
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