JPH08139229A - Semiconductor element mounting wiring board and semiconductor device using it - Google Patents

Semiconductor element mounting wiring board and semiconductor device using it

Info

Publication number
JPH08139229A
JPH08139229A JP27356294A JP27356294A JPH08139229A JP H08139229 A JPH08139229 A JP H08139229A JP 27356294 A JP27356294 A JP 27356294A JP 27356294 A JP27356294 A JP 27356294A JP H08139229 A JPH08139229 A JP H08139229A
Authority
JP
Japan
Prior art keywords
hole
substrate
wiring
metal conductor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27356294A
Other languages
Japanese (ja)
Inventor
Takehiro Sugiyama
剛博 杉山
Mamoru Onda
護 御田
Toyohiko Kumakura
豊彦 熊倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP27356294A priority Critical patent/JPH08139229A/en
Publication of JPH08139229A publication Critical patent/JPH08139229A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/44Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE: To ensure a larger wiring pattern space on the surface of a substrate by allowing high-frequency operation by reducing signal noise and cross talk and reducing through holes. CONSTITUTION: A through hole 2 is provided on an aluminum substrate 1, and the aluminum conductor is exposed on the inner plane of the through hole. On the front and rear planes of the substrate 1, including the inner plane of the through hole 2, an oxide film 4 is provided by oxidizing the aluminum. On the oxide film 4 in the through hole 2, through hole wiring 6 is provided, and on the oxide film 4 on the front plane of the substrate 1, a wiring pattern 7 to be connected with the through hole wiring 6 is provided. Thus, the through hole wiring 6 is permitted to have a coaxial structure surrounded by the aluminum conductor through the oxide film 4, and when the aluminum substrate 1 is grounded, shield effects are generated. Since the front and rear planes of the substrate can be grounded using the substrate 1, an exclusive through hole for grounding is not necessitated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高周波信号または高速
なデジタル信号を扱う半導体素子搭載用配線基板とそれ
を用いた半導体装置に係り、特に、半導体素子を搭載す
る基板の層間接続における配線構造を改良して、信号の
ノイズやクロストークを低減したものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting wiring board that handles high-frequency signals or high-speed digital signals and a semiconductor device using the same, and more particularly to a wiring structure in interlayer connection of a board mounting semiconductor elements. To improve signal noise and crosstalk.

【0002】[0002]

【従来の技術】従来、BGA(Ball Grid A
llay)パッケージ型半導体装置に用いられる基板
は、図6に示すように、絶縁基板21にスルーホール2
2を設け、スルーホール内面に金属めっきを施してスル
ーホール配線26を形成し、このスルーホール配線26
を基板上の配線パターン27と接続することによって、
基板の層間接続を行っている。
2. Description of the Related Art Conventionally, BGA (Ball Grid A) is used.
As shown in FIG. 6, the substrate used for the package type semiconductor device includes a through hole 2 in an insulating substrate 21.
2, the inner surface of the through hole is plated with metal to form a through hole wiring 26.
Is connected to the wiring pattern 27 on the substrate,
Inter-layer connection of substrates is performed.

【0003】そして、この層間接続した基板表面に半導
体素子を搭載してその端子を金ワイヤ29で配線パター
ン27に接続した上、基板裏面のスルーホール22の開
口端に外部接続用のボール端子8を形成してボール端子
8と半導体素子の端子間を導通させるようにし、これに
よってBGAパッケージ型半導体装置を構成している。
Then, a semiconductor element is mounted on the surface of the inter-layered substrates, the terminals thereof are connected to the wiring pattern 27 by the gold wires 29, and the ball terminals 8 for external connection are provided at the open ends of the through holes 22 on the back surface of the substrate. Is formed so that the ball terminal 8 and the terminal of the semiconductor element are electrically connected to each other, thereby forming a BGA package type semiconductor device.

【0004】ところで、半導体素子の端子には信号端
子、接地端子、電源端子があるが、これらはいずれも基
板表面に形成された配線パターンにそれぞれ接続され、
信号端子用スルーホール、接地電位用スルーホール、電
源電位用スルーホールによって基板裏面のボール端子に
導かれる。したがって、基板表面には、複数の信号配線
パターン、接地配線パターン、電源配線パターンが走っ
ており、それら配線パターンの数に応じた数のスルーホ
ールが必要となる。
By the way, the terminals of the semiconductor element include a signal terminal, a ground terminal, and a power terminal, all of which are connected to a wiring pattern formed on the surface of the substrate.
The signal terminal through hole, ground potential through hole, and power potential through hole lead to the ball terminals on the back surface of the substrate. Therefore, a plurality of signal wiring patterns, ground wiring patterns, and power supply wiring patterns run on the surface of the substrate, and through holes of the number corresponding to the number of these wiring patterns are required.

【0005】これまでのように、クロック周波数が50
MHz以下の比較的低速の半導体装置では、スルーホー
ル内に単に金属めっきを施してスルーホール配線を形成
するだけで特に問題はなかった。また、接地配線パター
ンや電源配線パターンを、信号配線パターンと離して1
ヶ所に集中させても特に問題はなかった。このため、そ
れらのパターン本数は信号パターンに比して比較的少な
くて済んでいた。また、それに応じて接地電位用スルー
ホールや電源電位用スルーホールの数も少なくて済み、
それらのスルーホールによって基板表面の配線スペース
に制約が生じることも少なかった。
As before, the clock frequency is 50
In a semiconductor device of a relatively low speed of MHz or less, there is no particular problem in that the through holes are simply formed by metal plating to form the through hole wiring. In addition, separate the ground wiring pattern and power wiring pattern from the signal wiring pattern.
There was no particular problem even if they were concentrated in one place. Therefore, the number of these patterns has been relatively small as compared with the signal pattern. In addition, the number of through holes for ground potential and through holes for power supply potential can be reduced accordingly.
The through holes did not often restrict the wiring space on the substrate surface.

【0006】[0006]

【発明が解決しようとする課題】しかし、最近、半導体
装置の高速化によってクロック周波数を50MHz以上
で動作させることが必要となってきたが、従来のような
スルーホールに単に金属めっきを施して形成したスルー
ホール配線では、半導体装置を高い周波数で動作させる
上で、次のような問題点があった。
However, recently, it has become necessary to operate at a clock frequency of 50 MHz or higher due to the speeding up of semiconductor devices. However, conventional through holes are simply formed by metal plating. The through hole wiring has the following problems in operating the semiconductor device at a high frequency.

【0007】(1)スルーホール配線のインピーダンス
不整合のため、信号波形が歪む。
(1) The signal waveform is distorted due to the impedance mismatch of the through-hole wiring.

【0008】(2)信号スルーホール配線が接地配線と
離れるため、信号スルーホール配線に流れる信号が電
界、磁界の影響を受けやすく、クロストークノイズの原
因となる。
(2) Since the signal through-hole wiring is separated from the ground wiring, the signal flowing through the signal through-hole wiring is easily affected by the electric field and magnetic field, which causes crosstalk noise.

【0009】(3)高速なデジタル信号によるスイッチ
ングにより、数の少ない接地端子及び電源端子に電流が
集中し、誤動作の原因となる。
(3) Due to high-speed digital signal switching, current concentrates on a small number of ground terminals and power supply terminals, which causes malfunction.

【0010】(4)ノイズ対策には、接地端子及び電源
端子を数多く必要とするが、数多くすると、これらの端
子を基板裏面に導くためのスルーホールの数が増え、基
板上の信号パターン配線のスペースが十分取れなくな
る。スペースを十分取ろうとすると半導体装置のサイズ
が大きくなる。
(4) A large number of grounding terminals and power supply terminals are required for noise suppression, but if many are provided, the number of through holes for guiding these terminals to the back surface of the board increases, and the signal pattern wiring on the board becomes large. Not enough space. If a sufficient space is taken, the size of the semiconductor device becomes large.

【0011】本発明の目的は、半導体素子を搭載する基
板の層間接続に同軸構造を導入することによって、前述
した従来技術の問題点を解消し、信号のノイズやクロス
トークを低減して高い周波数で動作させることが可能な
半導体素子用配線基板とそれを用いた半導体装置を提供
することにある。
An object of the present invention is to eliminate the above-mentioned problems of the prior art by introducing a coaxial structure in the interlayer connection of the substrate on which the semiconductor element is mounted, reduce signal noise and crosstalk, and increase the high frequency. It is an object of the present invention to provide a wiring board for a semiconductor element that can be operated in the above-mentioned manner and a semiconductor device using the same.

【0012】また、本発明の目的は、スルーホールを減
らすことによって、基板表面に配線パターンスペースを
より多く確保できる半導体素子用配線基板とそれを用い
た半導体装置を提供することにある。
It is another object of the present invention to provide a wiring board for a semiconductor element and a semiconductor device using the same, which can secure a larger wiring pattern space on the surface of the board by reducing through holes.

【0013】[0013]

【課題を解決するための手段】第1の発明の半導体素子
搭載用配線基板は、金属導体の基板にスルーホールを設
けてスルーホール内面に金属導体を露出させ、該スルー
ホールの内面を含めた上記基板の表裏面に絶縁層を設
け、上記スルーホール内の上記絶縁層の上にスルーホー
ル配線を設けるとともに、上記基板の表面の絶縁層の上
に上記スルーホール配線と接続される配線パターンを設
けることにより、上記スルーホール配線を上記絶縁層を
介して上記金属導体で囲む同軸構造としたものである。
In the wiring board for mounting a semiconductor element of the first invention, a through hole is provided in a substrate of a metal conductor to expose the metal conductor on the inner surface of the through hole, and the inner surface of the through hole is included. An insulating layer is provided on the front and back surfaces of the substrate, a through hole wiring is provided on the insulating layer in the through hole, and a wiring pattern connected to the through hole wiring is provided on the insulating layer on the surface of the substrate. By providing the through hole wiring, the through hole wiring is surrounded by the metal conductor to form a coaxial structure.

【0014】第2の発明の半導体素子搭載用配線基板
は、上記金属導体の基板としてアルミニウムを主成分と
する基板を用い、該基板の表面の酸化皮膜で上記絶縁層
を形成したものである。
The wiring board for mounting a semiconductor element of the second invention uses a substrate containing aluminum as a main component as a substrate of the metal conductor, and forms the insulating layer with an oxide film on the surface of the substrate.

【0015】第3の発明のの半導体素子搭載用配線基板
は、絶縁体の基板にスルーホールを設け、該スルーホー
ルの内面を含めた上記基板の表裏面に金属導体層を設
け、該金属導体層の上に絶縁層を設け、上記スルーホー
ル内の上記絶縁層の上にスルーホール配線を設けるとと
もに、上記基板の表面の絶縁層の上に上記スルーホール
配線と接続される配線パターンを設けることにより、上
記スルーホール配線を上記絶縁層を介して上記金属導体
層で囲まれた同軸状の配線構造とするものである。
In the wiring board for mounting a semiconductor element of the third invention, a through hole is provided in an insulating board, and metal conductor layers are provided on the front and back surfaces of the board including the inner surface of the through hole. An insulating layer is provided on the layer, a through hole wiring is provided on the insulating layer in the through hole, and a wiring pattern connected to the through hole wiring is provided on the insulating layer on the surface of the substrate. Thus, the through-hole wiring has a coaxial wiring structure surrounded by the metal conductor layer via the insulating layer.

【0016】第4の発明の半導体素子搭載用配線基板
は、第3の発明の金属導体層をアルミニウムで形成し、
該アルミニウム表面の酸化皮膜で上記絶縁層を形成した
ものである。
In the wiring board for mounting a semiconductor element of the fourth invention, the metal conductor layer of the third invention is formed of aluminum,
The above-mentioned insulating layer is formed by an oxide film on the surface of the aluminum.

【0017】第5の発明の半導体素子搭載用配線基板
は、第1の発明ないし第4の発明において、上記金属導
体または上記金属導体層を接地電位または電源電位に接
続するために、上記基板の表裏面上の絶縁層の一部を除
去して上記金属導体または上記金属導体層を露出させた
ものである。
A wiring board for mounting a semiconductor device according to a fifth aspect of the present invention is the wiring board according to any one of the first to fourth aspects of the invention, for connecting the metal conductor or the metal conductor layer to a ground potential or a power supply potential. A part of the insulating layer on the front and back surfaces is removed to expose the metal conductor or the metal conductor layer.

【0018】第6の発明の半導体素子搭載用配線基板
は、第5の発明の半導体素子搭載用配線基板の表面に半
導体素子を搭載し、該半導体素子の信号端子と上記配線
パターンとを電気的に接続するとともに、上記半導体素
子の接地端子または電源端子を上記半導体素子搭載用配
線基板の表面に露出させた上記金属導体または上記金属
導体層とを電気的に接続し、上記半導体素子搭載用配線
基板の裏面のスルーホールの開口に上記スルーホール配
線を介して上記信号端子と導通するボール端子を設ける
とともに、同じ裏面に露出させた上記金属導体または上
記金属導体層に上記半導体素子の接地端子または電源端
子と導通するボール端子を設けたものである。
The semiconductor element mounting wiring board of the sixth invention has a semiconductor element mounted on the surface of the semiconductor element mounting wiring board of the fifth invention, and the signal terminals of the semiconductor element and the wiring pattern are electrically connected. And electrically connecting the ground terminal or the power supply terminal of the semiconductor element to the metal conductor or the metal conductor layer exposed on the surface of the semiconductor element mounting wiring board, and the semiconductor element mounting wiring. A ball terminal that is electrically connected to the signal terminal through the through-hole wiring is provided in the opening of the through-hole on the back surface of the substrate, and the metal conductor or the metal conductor layer exposed on the same back surface is connected to the ground terminal of the semiconductor element or A ball terminal is provided which is electrically connected to the power supply terminal.

【0019】[0019]

【作用】第1の発明のように、スルーホール配線を金属
導体で囲む同軸構造にすると、特性インピーダンスの整
合がとれて信号が歪まなくなる。特に、金属導体を接地
すると、電界、磁界の影響を抑えることができ、クロス
トークノイズの発生を有効に防止することができる。
When the through-hole wiring is surrounded by the metal conductor so as to have the coaxial structure as in the first invention, the characteristic impedance is matched and the signal is not distorted. In particular, if the metal conductor is grounded, the influence of electric field and magnetic field can be suppressed, and the generation of crosstalk noise can be effectively prevented.

【0020】第2の発明のように、金属導体をアルミニ
ウムとし、そのアルミニウムの酸化皮膜を絶縁層として
用いると、均一な同軸構造を形成することができるの
で、特性が良好となる。
When the metal conductor is aluminum and the aluminum oxide film is used as the insulating layer as in the second aspect of the invention, a uniform coaxial structure can be formed, so that the characteristics are improved.

【0021】第3の発明のように、スルーホール配線を
金属導体層で囲む同軸構造にしても、特性インピーダン
スの整合がとれて信号が歪まなくなる。また、金属導体
層を接地すると、電界、磁界の影響を抑えることがで
き、クロストークノイズの発生を有効に防止することが
できる。
Even when the through hole wiring is surrounded by the metal conductor layer as in the third aspect of the invention, the characteristic impedance is matched and the signal is not distorted. Further, if the metal conductor layer is grounded, the influence of the electric field and the magnetic field can be suppressed, and the generation of crosstalk noise can be effectively prevented.

【0022】第4の発明のように、絶縁層にアルミニウ
ムの酸化皮膜を用いると、均一な同軸構造を形成するこ
とができるので、特性が良好となる。
When an aluminum oxide film is used for the insulating layer as in the fourth aspect of the invention, a uniform coaxial structure can be formed, so that the characteristics are improved.

【0023】第5の発明のように、金属導体または金属
導体層を接地電位または電源電位に接続すると、スルー
ホールの同軸構造を構成する金属導体または金属導体層
を介して表裏面の接地電位または電源電位を導通させる
ことができるので、接地電位または電源電位を基板表面
から基板裏面に導くためのスルーホールを個別に用意す
る必要がなくなる。
When the metal conductor or the metal conductor layer is connected to the ground potential or the power source potential as in the fifth invention, the ground potential of the front and back surfaces is connected via the metal conductor or the metal conductor layer forming the coaxial structure of the through hole or Since the power supply potential can be conducted, it is not necessary to separately prepare a through hole for guiding the ground potential or the power supply potential from the substrate front surface to the substrate back surface.

【0024】第6の発明のように、第5の発明の半導体
素子搭載用配線基板の表面に半導体素子を搭載して、半
導体素子の接地端子または電源端子を金属導体または金
属導体層に接続すると、スルーホールの同軸構造を構成
する金属導体または金属導体層を介して基板の裏面に接
地電位または電源電位を導くことができるから、接地電
位または電源電位用のスルーホールが不要となり、その
ためのスペースも不要となるから、基板表面に形成する
配線パターン密度を上げることができる。
As in the sixth invention, when the semiconductor element is mounted on the surface of the wiring board for mounting the semiconductor element of the fifth invention and the ground terminal or the power supply terminal of the semiconductor element is connected to the metal conductor or the metal conductor layer. Since the ground potential or the power supply potential can be guided to the back surface of the substrate through the metal conductor or the metal conductor layer forming the coaxial structure of the through hole, the through hole for the ground potential or the power supply potential is not necessary, and the space therefor is not necessary. Since it is not necessary, the density of the wiring pattern formed on the substrate surface can be increased.

【0025】[0025]

【実施例】以下、本発明の半導体素子搭載用配線基板と
それを用いた半導体装置の実施例を説明する。
EXAMPLES Examples of a semiconductor element mounting wiring board of the present invention and a semiconductor device using the same will be described below.

【0026】(第1実施例)図1に、基板に金属導体を
使用した第1実施例を示す。半導体素子搭載用配線基板
として、厚さ1.5mm、32mm角のアルミ基板1を用い
る。最初に、スルーホール配線を設けるアルミ基板位置
に、φ1.0mmのスルーホール2を設けて、スルーホー
ル内面にアルミ導体を露出させる(図1(a))。次に
エポキシ系のマスキング塗料3を基板1の全面に20μ
m塗布し、露光、現像により外部の接地電位とする裏面
の接地箇所と、半導体素子の接地端子に接続する表面の
接地箇所とにマスキング塗料3をそれぞれ残す(図1
(b))。
(First Embodiment) FIG. 1 shows a first embodiment in which a metal conductor is used for the substrate. An aluminum substrate 1 having a thickness of 1.5 mm and a size of 32 mm is used as a wiring board for mounting semiconductor elements. First, a through hole 2 having a diameter of 1.0 mm is provided at the position of the aluminum substrate where the through hole wiring is provided, and the aluminum conductor is exposed on the inner surface of the through hole (FIG. 1 (a)). Next, an epoxy masking paint 3 is applied to the entire surface of the substrate 1 by 20 μm.
The masking paint 3 is left on the grounding portion on the back surface which is applied to the external ground potential by coating, exposing and developing, and the grounding portion on the surface which is connected to the ground terminal of the semiconductor element (see FIG. 1).
(B)).

【0027】次に、硫酸によるアルマイト処理を施し、
マスキングを施した部分以外に絶縁層であるアルミナ
(Al2 3 )の酸化皮膜4を形成する(図1
(c))。このとき、電界浴は10〜20%のH2 SO
4 、電流密度はD.C.60〜200(A/m2 )、電
圧は10〜25V、温度15〜25℃、時間30〜60
分で膜厚20μmの酸化皮膜4が形成できる。酸化皮膜
4を形成後、残しておいたマスキング塗料3を除去し
て、外部の接地電位とする裏面接地箇所と、半導体素子
の接地端子に接続する表面接地箇所とを露出させる(図
1(d))。
Next, an alumite treatment with sulfuric acid is applied,
An oxide film 4 of alumina (Al 2 O 3 ) which is an insulating layer is formed on a portion other than the masked portion (FIG. 1).
(C)). At this time, the electric field bath is 10 to 20% H 2 SO.
4 , the current density is D. C. 60 to 200 (A / m 2 ), voltage is 10 to 25 V, temperature is 15 to 25 ° C., time is 30 to 60
The oxide film 4 having a film thickness of 20 μm can be formed in a minute. After the oxide film 4 is formed, the remaining masking paint 3 is removed to expose the back-side grounding point to be the external ground potential and the front-side grounding point connected to the ground terminal of the semiconductor element (FIG. 1 (d )).

【0028】次に、スルーホール2を含めた基板全体に
銅を蒸着して2〜3μmのCu皮膜5を形成する(図1
(e))。そして、再び、マスキング塗料を20μm塗
布し、露光、現像を行い、スルーホール配線6及び配線
パターン7として残す部分以外のCu皮膜5をエッチン
グにより除去して、スルーホール配線6、及びこれと接
続される配線パターン7を形成する(図1(f))。こ
のうちスルーホール2内に形成されたスルーホール配線
6は、酸化皮膜4を介して基板1のアルミ導体で囲まれ
る同軸構造となる。なお、6aはスルーホール電極であ
り、スルーホール配線形成時にスルーホール開口縁に形
成するリング状の配線電極である。
Next, copper is vapor-deposited on the entire substrate including the through holes 2 to form a Cu coating 5 having a thickness of 2 to 3 μm (see FIG. 1).
(E)). Then, masking paint is applied again to 20 μm, exposed and developed, and the Cu film 5 other than the portions to be left as the through hole wiring 6 and the wiring pattern 7 is removed by etching to connect the through hole wiring 6 and this. The wiring pattern 7 is formed (FIG. 1F). The through hole wiring 6 formed in the through hole 2 has a coaxial structure surrounded by the aluminum conductor of the substrate 1 with the oxide film 4 interposed therebetween. Reference numeral 6a is a through-hole electrode, which is a ring-shaped wiring electrode formed at the opening edge of the through-hole when forming the through-hole wiring.

【0029】その後、マスクを除去することによって、
本実施例の半導体素子搭載用配線基板が完成する。
Then, by removing the mask,
The semiconductor element mounting wiring board of this embodiment is completed.

【0030】引続き、この半導体素子搭載用配線基板を
用いてBGAパッケージ型半導体素子を製造するため
に、図2に示すように、半導体素子搭載用配線基板上に
半導体素子10をダイボンディングし、半導体素子10
の端子とアルミ基板1の表面に形成した配線パターン7
とを、Auワイヤ9を用いてワイヤボンディングする。
Subsequently, in order to manufacture a BGA package type semiconductor element using this semiconductor element mounting wiring board, the semiconductor element 10 is die-bonded onto the semiconductor element mounting wiring board as shown in FIG. Element 10
Wiring pattern 7 formed on the terminals and the surface of the aluminum substrate 1
And are wire-bonded using the Au wire 9.

【0031】また、半導体素子10の接地は、図1
(g)に示すように、アルマイト処理されなかった基板
表面接地箇所にワイヤ9をボンディングして行う。ま
た、基板1の裏面のスルーホール2の開口端と、アルマ
イト処理されなかった裏面接地箇所とに半田を印刷し、
これを加熱して信号端子用のボール端子8a、及び接地
端子用のボール端子8bをそれぞれ形成する(図1
(g))。
The semiconductor element 10 is grounded as shown in FIG.
As shown in (g), the wire 9 is bonded to the grounded portion on the surface of the substrate that has not been anodized. Also, solder is printed on the open end of the through hole 2 on the back surface of the substrate 1 and the back surface grounding portion that has not been anodized,
This is heated to form ball terminals 8a for signal terminals and ball terminals 8b for ground terminals (FIG. 1).
(G)).

【0032】このようにして図2に示すような半導体装
置が完成する。
Thus, the semiconductor device as shown in FIG. 2 is completed.

【0033】本実施例のようにスルーホール2に形成し
たスルーホール配線6を基板アルミ導体からなる金属導
体で囲まれた同軸構造とし、基板1を接地電位として基
板アルミ導体を接地するようにすると、スルーホール配
線6のインピーダンス整合が取れるようになるため、半
導体装置を50MHz以上の高い周波数で動作させて
も、信号波が歪むことがない。また、スルーホール配線
が接地電位にシールドされるため、スルーホール配線に
流れる信号が電界、磁界の影響を受けにくくなり、クロ
ストークノイズの発生が有効に防止される。
When the through-hole wiring 6 formed in the through-hole 2 has a coaxial structure surrounded by a metal conductor made of a substrate aluminum conductor as in this embodiment, the substrate 1 is grounded and the substrate aluminum conductor is grounded. Since the impedance of the through-hole wiring 6 can be obtained, the signal wave is not distorted even when the semiconductor device is operated at a high frequency of 50 MHz or higher. Further, since the through-hole wiring is shielded to the ground potential, the signal flowing through the through-hole wiring is less likely to be affected by the electric field and the magnetic field, and the crosstalk noise is effectively prevented.

【0034】また、基板にアルミ基板を使用して、その
基板の表面接地箇所に半導体素子の接地端子を接続し、
裏面接地箇所に形成したボール端子を外部の接地電位と
するようにして、基板を介して基板の表裏面の接地端子
を導通させるようにしたので、接地電位専用のスルーホ
ールを設けなくてもよい。このため、ノイズ対策のため
に接地端子数を多く形成した場合でも、スルーホールの
数を増加しなくてもよい。また、多数の接地用ボール端
子を基板裏面に設けて電流を拡散することができるか
ら、高速なデジタル信号によるスイッチングによって
も、特定の接地用ボール端子に電流が集中して誤動作が
生じるようなことがない。
Further, an aluminum substrate is used as the substrate, and the ground terminal of the semiconductor element is connected to the surface grounded portion of the substrate,
Since the ball terminals formed at the grounded portion on the back surface are set to the external ground potential and the ground terminals on the front and back surfaces of the substrate are conducted through the substrate, it is not necessary to provide a through hole dedicated to the ground potential. . Therefore, even if a large number of ground terminals are formed to prevent noise, the number of through holes does not have to be increased. Also, since a large number of ground ball terminals can be provided on the back side of the board to spread the current, it is possible that the current may concentrate on a specific ground ball terminal and cause malfunction even when switching with a high-speed digital signal. There is no.

【0035】また、図3(a)に示すように、基板1の
裏面に信号端子用のボール端子8aを碁盤目状に配置し
て、相隣る各4つのボール端子8aに囲まれた中央位置
に接地端子用のボール端子8bを配置するようにすれ
ば、図3(b)に示すように、接地端子用ボール端子8
bの基板表面の対応位置に、配線パターン用スペースが
確保できるから、半導体装置のサイズを大きくすること
なく、配線パターン7をより高密度に形成することがで
きる。
Further, as shown in FIG. 3 (a), ball terminals 8a for signal terminals are arranged in a grid pattern on the back surface of the substrate 1, and a center surrounded by four adjacent ball terminals 8a. If the ball terminal 8b for the ground terminal is arranged at the position, as shown in FIG. 3 (b), the ball terminal 8 for the ground terminal 8 is formed.
Since the wiring pattern space can be secured at the corresponding position on the substrate surface of b, the wiring pattern 7 can be formed at a higher density without increasing the size of the semiconductor device.

【0036】(第2実施例)図4に、基板に絶縁体を使
用した第2実施例を示す。半導体素子搭載用配線基板と
して、厚さ1.5mm、48mm角のガラス・エポキシ基板
11を用いる。最初に、スルーホール配線を設ける基板
位置にφ1.0mmのスルーホール2を設ける(図4
(a))。スルーホール2を含めた基板全面にアルミニ
ウムを蒸着し、5μmのアルミ皮膜12を形成する(図
4(b))。
(Second Embodiment) FIG. 4 shows a second embodiment in which an insulator is used for the substrate. A glass / epoxy substrate 11 having a thickness of 1.5 mm and a size of 48 mm is used as a wiring substrate for mounting semiconductor elements. First, the through hole 2 with a diameter of 1.0 mm is provided at the substrate position where the through hole wiring is provided (see FIG. 4).
(A)). Aluminum is vapor-deposited on the entire surface of the substrate including the through holes 2 to form an aluminum film 12 having a thickness of 5 μm (FIG. 4B).

【0037】次にエポキシ系のマスキング塗料3を基板
1の全面に20μm塗布し、露光、現像により外部の接
地電位と接続する裏面接地箇所と、半導体素子の接地端
子と接続する表面接地箇所とにマスキング塗料3をそれ
ぞれ残す(図4(c))。
Next, an epoxy-based masking paint 3 is applied to the entire surface of the substrate 1 to a thickness of 20 μm, and exposed to light and developed at a backside grounding point connected to an external ground potential and a frontside grounding point connected to a semiconductor element ground terminal. The masking paint 3 is left (FIG. 4 (c)).

【0038】次に、硫酸によるアルマイト処理を施し、
マスキングを施した部分以外にアルミナ(Al2 3
の酸化皮膜4を形成し、その後、残しておいたマスキン
グ塗料3を除去する(図4(d))。このとき、電界浴
は10〜20%のH2 SO、電流密度はD.C.60
〜200(A/m)、電圧は10〜25V、温度1
5〜25℃で、時間30分で膜厚10μmの酸化皮膜4
が形成できる。
Next, an alumite treatment with sulfuric acid is applied,
Alumina (Al 2 O 3 ) other than the masked part
Oxide film 4 is formed, and then the remaining masking paint 3 is removed (FIG. 4 (d)). At this time, the electric field bath was 10 to 20% H 2 SO 4 , and the current density was D.I. C. 60
~ 200 (A / m 2 ), voltage is 10-25V, temperature 1
Oxide film 4 with a thickness of 10 μm at 5 to 25 ° C in 30 minutes
Can be formed.

【0039】次に、Alスルーホール配線16を形成し
ない箇所、及び接地接続部分として残す箇所以外を金属
板のマスク13で覆う(図4(e))。その後、アルミ
ニウムを蒸着して膜厚3〜5μmのアルミニウム皮膜を
形成し、その上に、再びマスキング塗料を20μm塗布
し、露光、現像を行い、Alスルーホール配線16及び
Al配線パターン7として残す部分以外のアルミニウム
皮膜をエッチングにより除去して、Alスルーホール配
線16、及びこれと接続されるAl配線パターン17を
形成する(図4(f))。このうちスルーホール2内に
形成されたAlスルーホール配線16は、酸化皮膜4を
介してアルミ皮膜12で囲まれる同軸構造となる。
Next, the mask 13 made of a metal plate covers the portions other than the portions where the Al through-hole wiring 16 is not formed and the portions to be left as the ground connection portions (FIG. 4E). After that, aluminum is vapor-deposited to form an aluminum film having a film thickness of 3 to 5 μm, a masking paint of 20 μm is again applied on the aluminum film, and exposure and development are performed to leave the Al through-hole wiring 16 and the Al wiring pattern 7. The aluminum film other than the above is removed by etching to form the Al through-hole wiring 16 and the Al wiring pattern 17 connected thereto (FIG. 4 (f)). Of these, the Al through-hole wiring 16 formed in the through-hole 2 has a coaxial structure surrounded by the aluminum film 12 via the oxide film 4.

【0040】金属板マスク13を取り外した後、図5に
示すように、半導体素子14、14を複数搭載した多層
配線基板15をTAB18によってガラス・エポキシ基
板1の表面に形成したアルミニウム配線パターン7とA
u−Sn接合により接続する。その後、基板裏面のスル
ーホール2の開口端とアルマイト処理されいなかった裏
面接地位置とに半田を印刷して加熱し、ボール端子8
a、8bを形成する(図4(g))。
After removing the metal plate mask 13, as shown in FIG. 5, a multilayer wiring board 15 having a plurality of semiconductor elements 14, 14 mounted thereon is formed with an aluminum wiring pattern 7 formed on the surface of the glass / epoxy board 1 by TAB 18. A
Connected by u-Sn junction. After that, solder is printed on the open end of the through hole 2 on the back surface of the substrate and the back surface grounding position not subjected to the alumite treatment, and the ball terminal 8 is heated.
a and 8b are formed (FIG. 4 (g)).

【0041】このように第2実施例は、スルーホールを
設けた絶縁基板にアルミ皮膜を設け、スルーホール配線
をこのアルミ皮膜で囲まれた同軸構造とし、アルミ皮膜
とスルーホール配線間に形成した絶縁層は、アルミニウ
ム表面を酸化処理することによって形成し、さらにスル
ーホール配線を囲むアルミ皮膜を接地電位、または電源
電位に接続するようにしたものである。したがって、基
板を金属導体ではなく、絶縁基板とした点を除き、第1
実施例と構成が同じであるから、第1実施例と同様な効
果を奏する。なお、第2実施例のものは基板を絶縁基板
としたので、アルミ皮膜工程が増える点、また放熱性が
低下するという点で第1実施例より若干劣るが、実装す
るプリント基板と熱膨張率がほぼ一致するため、半田ボ
ールに極端なストレスがかからないという点が第1実施
例よりも優れている。
As described above, in the second embodiment, the aluminum film is provided on the insulating substrate having the through holes, and the through hole wiring has a coaxial structure surrounded by the aluminum film, and is formed between the aluminum film and the through hole wiring. The insulating layer is formed by oxidizing the surface of aluminum, and the aluminum film surrounding the through-hole wiring is connected to the ground potential or the power supply potential. Therefore, except that the substrate is not a metal conductor but an insulating substrate, the first
Since the configuration is the same as that of the embodiment, the same effect as that of the first embodiment is obtained. In addition, since the substrate of the second embodiment is an insulating substrate, it is slightly inferior to the first embodiment in that the number of aluminum film processes is increased and the heat dissipation is lowered, but the printed board to be mounted and the coefficient of thermal expansion are reduced. Are substantially the same as each other, which is superior to the first embodiment in that extreme stress is not applied to the solder balls.

【0042】(その他の実施例)上記実施例では、いず
れもスルーホール配線を囲むアルミ導体またはアルミ皮
膜を接地電位に接続するようにしたが、電源電位に接続
するようにしてもよい。そうすると、電源電位用のスル
ーホールを省略することができる。
(Other Embodiments) In each of the above embodiments, the aluminum conductor or aluminum film surrounding the through-hole wiring is connected to the ground potential, but it may be connected to the power supply potential. Then, the through hole for the power supply potential can be omitted.

【0043】[0043]

【発明の効果】請求項1に記載の発明によれば、基板を
金属導体で構成し、スルーホール配線を金属導体で囲ま
れた同軸構造にしてインピーダンス整合がとれるように
したので、高周波で動作させても歪みの少ない信号波形
を伝送できる。
According to the first aspect of the present invention, since the substrate is made of a metal conductor and the through-hole wiring has a coaxial structure surrounded by the metal conductor so that impedance matching can be achieved, it operates at a high frequency. Even if it is done, a signal waveform with little distortion can be transmitted.

【0044】請求項2に記載の発明によれば、絶縁層に
アルミニウムの酸化皮膜を用いることにより、均一な同
軸構造とすることができるから、特性が一層良好にな
る。
According to the second aspect of the invention, by using an aluminum oxide film for the insulating layer, a uniform coaxial structure can be obtained, so that the characteristics are further improved.

【0045】請求項3に記載の発明によれば、絶縁基板
に金属導体層を形成し、スルーホール配線を金属導体層
で囲まれた同軸構造にしてインピーダンス整合がとれる
ようにしたので、高周波で動作させても歪みの少ない信
号波形を伝送できる。
According to the third aspect of the present invention, since the metal conductor layer is formed on the insulating substrate and the through-hole wiring is formed in the coaxial structure surrounded by the metal conductor layer to achieve impedance matching, it is possible to achieve high frequency. A signal waveform with little distortion can be transmitted even when operated.

【0046】請求項4に記載の発明によれば、絶縁層に
アルミニウムの酸化皮膜を用いることにより、均一な同
軸構造とすることができるから、特性が一層良好にな
る。
According to the invention described in claim 4, since the uniform coaxial structure can be obtained by using the aluminum oxide film for the insulating layer, the characteristics are further improved.

【0047】請求項5に記載の発明によれば、基板の表
裏面上の絶縁層の一部を除去して金属導体または金属導
体層を露出させるようにしたので、専用のスルーホール
を設けなくても、金属導体層を接地電位または電源電位
に接続することができる。
According to the invention of claim 5, a part of the insulating layer on the front and back surfaces of the substrate is removed to expose the metal conductor or the metal conductor layer, so that a dedicated through hole is not provided. However, the metal conductor layer can be connected to the ground potential or the power supply potential.

【0048】請求項6に記載の発明によれば、同軸構造
を構成する金属導体または金属導体層を利用して表裏面
の接地端子または電源端子を導通させるので、接地電位
用または電源電位用のスルーホールを減らすことがで
き、基板表面の配線スペースをより多く確保できる。
According to the sixth aspect of the invention, since the ground terminals or the power source terminals on the front and back surfaces are made conductive by using the metal conductor or the metal conductor layer forming the coaxial structure, the ground potential or the power source potential is used. Through holes can be reduced, and more wiring space on the substrate surface can be secured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子搭載用配線基板とそれを用
いた半導体装置の第1実施例を説明するための基板及び
半導体装置の要部製造工程図。
FIG. 1 is a manufacturing process diagram of a substrate and a semiconductor device for explaining a first embodiment of a semiconductor element mounting wiring substrate of the present invention and a semiconductor device using the same.

【図2】第1実施例による半導体装置の全体斜視図。FIG. 2 is an overall perspective view of the semiconductor device according to the first embodiment.

【図3】第1実施例による半導体装置の要部説明図であ
って、(a)はボール端子を設けた基板の裏面図、
(b)は配線パターンを形成した基板の表面図。
FIG. 3 is an explanatory view of a main part of the semiconductor device according to the first embodiment, in which (a) is a rear view of a substrate provided with ball terminals;
(B) is a surface view of a substrate on which a wiring pattern is formed.

【図4】第2実施例を説明するための基板及び半導体装
置の要部製造工程図。
FIG. 4 is a manufacturing process diagram of a main part of a substrate and a semiconductor device for explaining a second embodiment.

【図5】第2実施例による半導体装置の全体斜視図。FIG. 5 is an overall perspective view of a semiconductor device according to a second embodiment.

【図6】従来例の半導体装置の要部断面図。FIG. 6 is a cross-sectional view of a main part of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 アルミ基板 2 スルーホール 3 マスキング塗料 4 酸化皮膜 5 Cu皮膜 6 スルーホール配線 7 配線パターン 8a 信号端子用ボール端子 8b 接地端子用ボール端子 9 Auワイヤ 1 Aluminum substrate 2 Through hole 3 Masking paint 4 Oxide film 5 Cu film 6 Through hole wiring 7 Wiring pattern 8a Signal terminal ball terminal 8b Ground terminal ball terminal 9 Au wire

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】金属導体の基板にスルーホールを設けてス
ルーホール内面に金属導体を露出させ、該スルーホール
の内面を含めた上記基板の表裏面に絶縁層を設け、上記
スルーホール内の上記絶縁層の上にスルーホール配線を
設けるとともに、上記基板の表面の絶縁層の上に上記ス
ルーホール配線と接続される配線パターンを設けること
により、上記スルーホール配線を上記絶縁層を介して上
記金属導体で囲む同軸構造とした半導体素子搭載用配線
基板。
1. A through hole is provided in a substrate of a metal conductor to expose the metal conductor on the inner surface of the through hole, and insulating layers are provided on the front and back surfaces of the substrate including the inner surface of the through hole. By providing through-hole wiring on the insulating layer and by providing a wiring pattern connected to the through-hole wiring on the insulating layer on the surface of the substrate, the through-hole wiring is connected to the metal through the insulating layer. A wiring board for mounting semiconductor elements that has a coaxial structure surrounded by conductors.
【請求項2】上記金属導体の基板としてアルミニウムを
主成分とする基板を用い、該基板表面の酸化皮膜で上記
絶縁層を形成した請求項1に記載の半導体素子搭載用配
線基板。
2. The wiring board for mounting a semiconductor element according to claim 1, wherein a substrate containing aluminum as a main component is used as the substrate of the metal conductor, and the insulating layer is formed by an oxide film on the surface of the substrate.
【請求項3】絶縁体の基板にスルーホールを設け、該ス
ルーホールの内面を含めた上記基板の表裏面に金属導体
層を設け、該金属導体層の上に絶縁層を設け、上記スル
ーホール内の上記絶縁層の上にスルーホール配線を設け
るとともに、上記基板の表面の絶縁層の上に上記スルー
ホール配線と接続される配線パターンを設けることによ
り、上記スルーホール配線を上記絶縁層を介して上記金
属導体層で囲まれた同軸状の配線構造とすることを特徴
とした半導体素子搭載用配線基板。
3. A through hole is provided in an insulating substrate, a metal conductor layer is provided on the front and back surfaces of the substrate including the inner surface of the through hole, an insulating layer is provided on the metal conductor layer, and the through hole is provided. By providing a through-hole wiring on the insulating layer inside, and by providing a wiring pattern connected to the through-hole wiring on the insulating layer on the surface of the substrate, the through-hole wiring through the insulating layer A wiring board for mounting a semiconductor element, which has a coaxial wiring structure surrounded by the metal conductor layer.
【請求項4】上記金属導体層をアルミニウムで形成し、
該アルミニウム表面の酸化皮膜で上記絶縁層を形成した
請求項3に記載の半導体素子搭載用配線基板。
4. The metal conductor layer is formed of aluminum,
The wiring board for mounting a semiconductor element according to claim 3, wherein the insulating layer is formed of an oxide film on the surface of the aluminum.
【請求項5】上記金属導体または上記金属導体層を接地
電位または電源電位に接続するために、上記基板の表裏
面上の絶縁層の一部を除去して上記金属導体または上記
金属導体層を露出させた請求項1ないし4のいずれかに
記載の半導体素子搭載用配線基板。
5. In order to connect the metal conductor or the metal conductor layer to a ground potential or a power supply potential, a part of the insulating layer on the front and back surfaces of the substrate is removed to form the metal conductor or the metal conductor layer. The wiring board for mounting a semiconductor element according to claim 1, which is exposed.
【請求項6】請求項5に記載の半導体素子搭載用配線基
板の表面に半導体素子を搭載し、該半導体素子の信号端
子と上記配線パターンとを電気的に接続するとともに、
上記半導体素子の接地端子または電源端子を上記半導体
素子搭載用配線基板の表面に露出させた上記金属導体ま
たは上記金属導体層に電気的に接続し、上記半導体素子
搭載用配線基板の裏面のスルーホールの開口に上記配線
パターンを介して上記信号端子と導通するボール端子を
設けるとともに、同じ裏面に露出させた上記金属導体ま
たは上記金属導体層に上記半導体素子の接地端子または
電源端子と導通するボール端子を設けた半導体装置。
6. A semiconductor element is mounted on the surface of the wiring board for mounting a semiconductor element according to claim 5, and a signal terminal of the semiconductor element and the wiring pattern are electrically connected to each other, and
A ground hole or a power supply terminal of the semiconductor element is electrically connected to the metal conductor or the metal conductor layer exposed on the surface of the semiconductor element mounting wiring board, and a through hole on the back surface of the semiconductor element mounting wiring board. A ball terminal that is electrically connected to the signal terminal through the wiring pattern is provided in the opening, and a ball terminal that is electrically connected to the ground terminal or the power supply terminal of the semiconductor element on the metal conductor or the metal conductor layer exposed on the same back surface. Semiconductor device provided with.
JP27356294A 1994-11-08 1994-11-08 Semiconductor element mounting wiring board and semiconductor device using it Pending JPH08139229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27356294A JPH08139229A (en) 1994-11-08 1994-11-08 Semiconductor element mounting wiring board and semiconductor device using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27356294A JPH08139229A (en) 1994-11-08 1994-11-08 Semiconductor element mounting wiring board and semiconductor device using it

Publications (1)

Publication Number Publication Date
JPH08139229A true JPH08139229A (en) 1996-05-31

Family

ID=17529540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27356294A Pending JPH08139229A (en) 1994-11-08 1994-11-08 Semiconductor element mounting wiring board and semiconductor device using it

Country Status (1)

Country Link
JP (1) JPH08139229A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081100A (en) * 2005-09-14 2007-03-29 Tdk Corp Wiring substrate, and manufacturing method thereof
JP2008053847A (en) * 2006-08-22 2008-03-06 Tdk Corp Non-reciprocal circuit element and communication device
JP2013033988A (en) * 2008-03-07 2013-02-14 Sk Hynix Inc Circuit board and semiconductor package using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081100A (en) * 2005-09-14 2007-03-29 Tdk Corp Wiring substrate, and manufacturing method thereof
JP2008053847A (en) * 2006-08-22 2008-03-06 Tdk Corp Non-reciprocal circuit element and communication device
JP2013033988A (en) * 2008-03-07 2013-02-14 Sk Hynix Inc Circuit board and semiconductor package using the same

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