KR20080086042A - Semiconductor chip package having reduced coupling noise - Google Patents

Semiconductor chip package having reduced coupling noise Download PDF

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KR20080086042A
KR20080086042A KR1020070027631A KR20070027631A KR20080086042A KR 20080086042 A KR20080086042 A KR 20080086042A KR 1020070027631 A KR1020070027631 A KR 1020070027631A KR 20070027631 A KR20070027631 A KR 20070027631A KR 20080086042 A KR20080086042 A KR 20080086042A
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signal
ground
wiring
terminal
pad
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KR1020070027631A
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Korean (ko)
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서장미
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삼성전자주식회사
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Publication of KR20080086042A publication Critical patent/KR20080086042A/en

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Abstract

A semiconductor chip package having reduced coupling noise is provided to electrically block a signal wiring which connects a signal pad of the semiconductor chip with a signal terminal of the lead frame by an extended ground wiring. A semiconductor chip package having reduced coupling noise includes a lead frame, a semiconductor chip(305), a signal wiring(323), and a ground wiring(325). The lead frame includes a die pad(301), a grounding terminal(302) extended on the side of the die pad, and a signal terminal(315) which is separated from the die pad. The semiconductor chip is mounted on the die pad and has a signal pad(307) and a ground pad(309). The signal wiring connects the signal pad and the signal terminal. The ground wiring connects the ground pad and the ground terminal. The ground wiring is located near the signal wiring, but not connected to the signal wiring. The length of the ground wiring is the same or greater than that of the signal wiring. The overlapping length between the ground wiring and the signal wiring is the same as the signal wiring.

Description

커플링 노이즈가 감소된 반도체 칩 패키지{Semiconductor chip package having reduced coupling noise}Semiconductor chip package having reduced coupling noise

도 1은 종래기술의 한 실시예에 따른 반도체장치를 설명하기 위한 사시도이다.1 is a perspective view illustrating a semiconductor device according to an embodiment of the prior art.

도 2는 종래기술의 다른 실시예에 따른 반도체장치를 설명하기 위한 사시도이다.2 is a perspective view illustrating a semiconductor device according to another embodiment of the prior art.

도 3은 본 발명의 제 1 실시예에 따른 반도체장치를 설명하기 위한 사시도이다.3 is a perspective view illustrating a semiconductor device according to a first embodiment of the present invention.

도 4는 본 발명의 제 2 실시예에 따른 반도체장치를 설명하기 위한 평면도이다.4 is a plan view illustrating a semiconductor device according to a second exemplary embodiment of the present invention.

도 5는 본 발명의 제 3 실시예에 따른 반도체장치를 설명하기 위한 평면도이다.5 is a plan view illustrating a semiconductor device according to a third embodiment of the present invention.

도 6은 본 발명의 제 4 실시예에 따른 반도체장치를 설명하기 위한 평면도이다.6 is a plan view illustrating a semiconductor device according to a fourth embodiment of the present invention.

본 발명은 반도체장치에 관한 것으로, 특히 다이 패드 측면에 신장된 접지단자를 구비한 리드 프레임(lead frame)을 사용하여 전기적 혼신(crosstalk)을 감소시킨 반도체장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having reduced electrical crosstalk by using a lead frame having a ground terminal extended on a side of a die pad.

최근 멀티미디어 고속 인터넷, 영상회의 등이 현실화됨에 따라 고속의 데이터 전송에 사용되는 반도체장치에 대한 수요가 급증하고 있다. 상기 새로운 서비스에 사용되는 반도체장치는 고속의 데이터 전송 기능 뿐 아니라, 그 응용 서비스와 관련한 특수기능을 다양하게 갖추어야 한다. 이에 따라, 하나의 칩이 구비하는 포트들(ports)의 수가 갈수록 증가일로에 있다.Recently, as multimedia high-speed Internet and video conferencing become a reality, demand for semiconductor devices used for high-speed data transmission is increasing rapidly. The semiconductor device used for the new service should have not only a high speed data transfer function but also various special functions related to the application service. Accordingly, the number of ports included in one chip is increasing.

상기 멀티플 포트(multiple ports)를 구비한 반도체장치 또한 현대 사회가 요구하는 전자부품 소형화의 요구로부터 자유로울 수 없다. 이와 관련한 기술발전에 따라 더 좁은 공간에 더 많은 수의 포트들이 배치됨으로써, 상기 반도체장치 내의 포트들 간의 이격거리는 갈수록 좁혀지고 있다. 그 결과, 상기 포트들로 연결되는 신호선들 사이의 간격이 좁아짐으로써 인접 신호선간의 전기적 간섭이 큰 폭으로 증가한다. 인접 신호선 간의 상기 전기적 간섭을 커플링 노이즈(coupling noise)라 한다. 특히 데이터전송 신호선을 통해 고속의 전류신호 펄스가 흐를 경우, 인접 신호선에 미치는 커플링 노이즈(coupling noise)는 심각한 전기적 혼신(crosstalk)을 야기할 수 있다. 따라서 고속 신호가 전송되는 반도체장치의 경우 상기 커플링 노이즈를 최소화하기 위한 패키지 구조의 설계가 필수적으로 요구된다.The semiconductor device having the multiple ports also cannot be free from the demand for miniaturization of electronic components required by the modern society. As the number of ports is arranged in a narrower space according to the related technology development, the separation distance between the ports in the semiconductor device is getting narrower. As a result, the gap between the signal lines connected to the ports is narrowed, thereby greatly increasing the electrical interference between adjacent signal lines. The electrical interference between adjacent signal lines is called coupling noise. In particular, when a high-speed current signal pulse flows through the data transmission signal line, coupling noise on the adjacent signal line may cause severe electrical crosstalk. Therefore, in the case of a semiconductor device to which a high speed signal is transmitted, it is necessary to design a package structure to minimize the coupling noise.

도 1은 종래기술의 한 실시예에 따른 반도체장치의 사시도이다.1 is a perspective view of a semiconductor device according to an embodiment of the prior art.

도 1을 참조하면, 종래의 반도체장치는 다이 패드(101)를 구비한다. 상기 다이 패드(101) 상에 반도체 칩(105)이 접착층(103)에 의해 부착되어 있다. 상기 반도체 칩(105)은 써데스(SERDES; serializer/deserializer) 칩과 같은 고속 데이터 전송에 사용되는 반도체 소자일 수 있다. 상기 반도체 칩(105) 상의 신호패드(107)는 신호배선(123)에 의해 신호단자(115)에 전기적으로 연결된다. 그러나, 상기 종래의 반도체장치의 경우, 신호단자들의 수가 늘어갈수록 상기 신호배선들 사이의 이격거리는 짧아지게 됨으로써 커플링 노이즈가 증가하게 되나, 이를 효과적으로 방지하는 기능을 갖추지 못하고 있음을 알 수 있다.Referring to FIG. 1, a conventional semiconductor device includes a die pad 101. The semiconductor chip 105 is attached to the die pad 101 by the adhesive layer 103. The semiconductor chip 105 may be a semiconductor device used for high-speed data transmission, such as a serializer / deserializer (SERDES) chip. The signal pad 107 on the semiconductor chip 105 is electrically connected to the signal terminal 115 by the signal wiring 123. However, in the case of the conventional semiconductor device, as the number of signal terminals increases, the separation distance between the signal wires is shortened, thereby increasing coupling noise, but it can be seen that it does not have a function for effectively preventing this.

도 2는 종래기술의 다른 실시예에 따른 반도체장치의 사시도이다.2 is a perspective view of a semiconductor device according to another embodiment of the prior art.

도 2를 참조하면, 종래의 다른 반도체장치는 접지에 연결된 다이 패드(201)을 구비하고 있다. 상기 다이 패드(201) 상에 접착층(203)에 의해 반도체 칩(205)이 부착되어 있다. 상기 반도체 칩(205) 상의 본드패드들(207, 209)은 신호전송에 쓰이는 신호패드들(207)과 접지에 연결되는 데 쓰이는 접지패드(209)로 나눌 수 있다. 신호패드(207)는 신호배선(223)에 의해 신호단자(215)에 연결된다. 접지패드(209)는 접지배선(225)에 의해 상기 다이 패드(201)에 연결된다. 상기 접지배선(225)은 상기 신호배선들(223)에 인접하여 배치된다. 그 결과, 상기 신호배선들(223)이 상기 접지배선(225)에 의해 전기적으로 차폐되어 커플링 노이즈가 감소하게 된다.Referring to FIG. 2, another conventional semiconductor device includes a die pad 201 connected to a ground. The semiconductor chip 205 is attached to the die pad 201 by an adhesive layer 203. Bond pads 207 and 209 on the semiconductor chip 205 may be divided into signal pads 207 used for signal transmission and a ground pad 209 used to be connected to ground. The signal pad 207 is connected to the signal terminal 215 by the signal wiring 223. The ground pad 209 is connected to the die pad 201 by a ground wiring 225. The ground line 225 is disposed adjacent to the signal lines 223. As a result, the signal wires 223 are electrically shielded by the ground wires 225 to reduce coupling noise.

그러나 상기 접지배선(225)이 상기 신호배선(223)에 비해 현저하게 짧은 길이로 형성될 수밖에 없는 구조상 문제점을 안고 있다. 이에 따라 공중에 뜬 상태로 노출된 상기 신호배선(223)의 일부 구간이 상기 접지배선(225)에 의해 차폐되지 못하게 됨으로써 커플링 노이즈를 방지하는 기능이 저하된다.However, the ground wiring 225 has a structural problem that can not be formed to a significantly shorter length than the signal wiring 223. As a result, some sections of the signal wiring 223 exposed in the air are not shielded by the ground wiring 225, thereby degrading the function of preventing coupling noise.

본 발명이 이루고자 하는 기술적 과제는 상술한 종래기술의 문제점을 개선하기 위한 것으로서, 고속의 신호전송에 사용되는 신호배선들 사이의 커플링 노이즈를 감소시킨 반도체장치를 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a semiconductor device in which coupling noise between signal wires used for high-speed signal transmission is reduced.

상기 기술적 과제를 달성하기 위하여 본 발명은, 커플링 노이즈가 감소된 반도체장치를 제공한다. 상기 반도체장치는 리드 프레임(lead frame)을 구비한다. 상기 리드 프레임은 다이패드(die pad), 상기 다이 패드의 측면에 신장된 접지단자, 및 상기 다이 패드와 분리된 신호단자로 구성된다. 상기 다이 패드 상에 반도체 칩이 장착된다. 상기 반도체 칩은 신호패드 및 접지패드를 구비한다. 상기 신호패드 및 상기 신호단자는 신호배선에 의해 상호 연결되어 있다. 상기 접지패드 및 상기 접지단자는 접지배선에 의해 상호 연결된다. 상기 접지배선은 상기 신호배선에 인접하나 상기 신호배선과 분리되도록 배치한다.In order to achieve the above technical problem, the present invention provides a semiconductor device with reduced coupling noise. The semiconductor device has a lead frame. The lead frame includes a die pad, a ground terminal extending on the side of the die pad, and a signal terminal separated from the die pad. A semiconductor chip is mounted on the die pad. The semiconductor chip has a signal pad and a ground pad. The signal pad and the signal terminal are interconnected by signal wiring. The ground pad and the ground terminal are interconnected by a ground wiring. The ground line is adjacent to the signal line but arranged to be separated from the signal line.

본 발명의 몇몇 실시예들에서, 상기 접지배선의 길이는 상기 신호배선보다 길거나 같되, 상기 접지배선 및 상기 신호배선 간의 중첩된 길이는 상기 신호배선과 같을 수 있다.In some embodiments of the present invention, the length of the ground line may be longer than or equal to the signal line, and the overlapped length between the ground line and the signal line may be the same as the signal line.

다른 실시예들에서, 상기 신호배선에 인접하고 상기 신호배선과 분리되도록 배치된 다른 접지배선을 더 구비하되, 상기 접지배선들 사이에 상기 신호배선이 배 치될 수 있다.In other embodiments, the circuit board may further include another ground line adjacent to the signal line and separated from the signal line, and the signal line may be disposed between the ground lines.

또 다른 실시예들에서, 상기 접지단자는 상기 신호단자의 일단과 좌우로 중첩하여 나란히 배치될 수 있다.In other embodiments, the ground terminals may be arranged side by side to overlap one end of the signal terminal to the left and right.

또 다른 실시예들에서, 상기 접지배선의 길이는 상기 신호배선의 80% 내지 300%일 수 있다.In still other embodiments, the length of the ground line may be 80% to 300% of the signal line.

또 다른 실시예들에서, 상기 신호단자의 일단은 평면도 상에서 보여질때 요철형상을 가질 수 있다. 이 경우 상기 접지단자는 상기 신호단자의 상기 요철 형상에 평행하게 대응하는 형상을 가질 수 있다.In still other embodiments, one end of the signal terminal may have an uneven shape when viewed in a plan view. In this case, the ground terminal may have a shape parallel to the concave-convex shape of the signal terminal.

또 다른 실시예들에서, 상기 접지단자는 상기 신호배선에 중첩되어 배치될 수 있다.In other embodiments, the ground terminal may be disposed to overlap the signal wiring.

또 다른 실시예들에서, 상기 반도체 칩은 써데스 칩(SERDES chip)일 수 있다.In still other embodiments, the semiconductor chip may be a SERDES chip.

이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시 예들을 상세히 설명하기로 한다. 그러나 본 발명은 여기서 설명되어지는 실시 예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시 예들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이다. 또한, 층이 다른 층 또는 기판 "상"에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나 또는 그들 사이에 제3의 층이 개재될 수도 있다. 명세서 전체에 걸쳐서 동일한 참조번호로 표시된 부분들은 동일한 구성요소들을 의미한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

도 3은 본 발명의 제 1 실시예들에 의한 반도체장치를 설명하기 위한 사시도이다.3 is a perspective view illustrating a semiconductor device in accordance with first embodiments of the present invention.

도 3을 참조하면, 본 발명의 제 1 실시예에 따른 반도체장치는 다이 패드(301)를 구비한다. 상기 다이 패드(301)는 도전성 물질막으로 형성될 수 있다. 상기 다이 패드(301)의 측면에는 긴 직사각형의 형태로 상기 다이 패드(301)로부터 신장되어 형성된 접지단자들(302)이 위치할 수 있다. Referring to FIG. 3, the semiconductor device according to the first embodiment of the present invention includes a die pad 301. The die pad 301 may be formed of a conductive material film. The ground terminal 302 which is formed to extend from the die pad 301 in the form of an elongate rectangle may be located at the side of the die pad 301.

상기 다이 패드(301) 상에 반도체 칩(305)이 배치된다. 상기 반도체 칩(305)과 상기 다이 패드(301) 사이에는 상기 반도체 칩(305)을 상기 다이 패드(301)에 부착하기 위한 접착제 층(303)이 있을 수 있다. 상기 반도체 칩(305)은 신호전송에 쓰이는 신호패드들(307)과 접지에 쓰이는 접지패드들(309)을 구비할 수 있다.The semiconductor chip 305 is disposed on the die pad 301. An adhesive layer 303 may be disposed between the semiconductor chip 305 and the die pad 301 to attach the semiconductor chip 305 to the die pad 301. The semiconductor chip 305 may include signal pads 307 used for signal transmission and ground pads 309 used for grounding.

상기 다이 패드(301)의 측면 바깥에 일정 간격을 두고 신호단자들(315)이 가로 방향으로 나란히 배치할 수 있다. 상기 신호단자들(315) 사이에 상기 접지단자들(302)이 위치할 수 있다.The signal terminals 315 may be arranged side by side in the horizontal direction at a predetermined interval outside the side of the die pad 301. The ground terminal 302 may be located between the signal terminals 315.

신호배선들(323)은 상기 신호패드들(307)과 상기 신호단자들(315)을 연결시켜 줄 수 있다. 접지배선들(325)은 상기 접지패드들(309)을 상기 접지단자(302)에 연결시켜 줄 수 있다.Signal wires 323 may connect the signal pads 307 and the signal terminals 315. The ground wires 325 may connect the ground pads 309 to the ground terminal 302.

상기 접지배선들(325)은 상기 신호배선들(323) 사이에 발생할 수 있는 커플링 노이즈(coupling noise)를 감소시키기 위해 배치될 수 있다. 만일 상기 접지배선들(325)이 존재하지 않는다면, 상기 신호배선들(323)은 그 각각에 인접한 다른 신호배선에 의해 유도되는 전기장에 노출되게 된다. 그 결과 인접 신호선 간에 간섭이 생기는 바, 이를 커플링 노이즈(coupling noise)라고 한다. 특히 고속 데이터 전송을 위한 전송선(이하 '고속 신호선'이라 한다)의 경우 상기 커플링 노이즈에 더욱 취약하다. 본 발명의 상기 접지배선들(325)은 그에 인접한 상기 신호배선들(323)의 전기적 차폐에 제공되는바, 특히 상기 신호배선들(323)이 고속 신호선으로 사용될 경우 상기 전기적 차폐에 의한 전기적 혼신의 감소가 두드러지게 나타날 수 있다.The ground lines 325 may be disposed to reduce coupling noise that may occur between the signal lines 323. If the ground wires 325 are not present, the signal wires 323 are exposed to an electric field induced by another signal wire adjacent to each other. As a result, interference occurs between adjacent signal lines, which is called coupling noise. In particular, a transmission line (hereinafter, referred to as a 'high speed signal line') for high speed data transmission is more vulnerable to the coupling noise. The ground wires 325 of the present invention are provided for the electrical shielding of the signal wires 323 adjacent thereto, in particular, when the signal wires 323 are used as high-speed signal lines, The decrease may be noticeable.

상기 신호배선(323)에 대한 상기 접지배선(325)의 전기적 차폐효과는 상기 신호배선(323) 및 상기 접지배선(325) 간의 이격거리에 의해서도 크게 좌우될 수 있다. 즉, 인접한 배선들 사이의 이격거리를 더 좁힐수록 더욱 효과적인 차폐가 가능할 수 있다. 다만, 상기 이격거리를 줄이는 데는 현재의 반도체 제조공정 기술의 디자인 룰에 의해 제한을 받을 수밖에 없다. 이에 해당하는 세부기술로는 와이어 본딩(wire bonding) 기술 및 리드 프레임 에칭(lead frame etching) 기술을 들 수 있다.The electrical shielding effect of the ground line 325 with respect to the signal line 323 may be greatly influenced by the separation distance between the signal line 323 and the ground line 325. That is, the narrower the separation distance between adjacent wires, the more effective shielding may be possible. However, in order to reduce the separation distance, it is inevitably limited by the design rules of the current semiconductor manufacturing process technology. Detailed technologies corresponding thereto include wire bonding technology and lead frame etching technology.

도 2와 도 3을 참조하여, 종래기술에 따른 반도체장치와 본 발명에 따른 반도체장치의 구성을 상호 비교할 경우, 본 발명의 장점을 전기적 차폐효과의 면에서 확연히 파악할 수 있다. 종래의 상기 반도체장치의 경우, 상기 신호배선(도 2의 223)의 전기적 차폐를 위해 제공되는 상기 접지배선(도 2의 225)의 길이는 상기 신호배선(도 2의 223)에 비해 현저히 짧은바 공간에 떠 있는 상기 신호배선(도 2의 223)의 상당 부분이 커플링 노이즈에 대해 오픈(open)된 상태로 제공된다. 이와 대 비하면, 본 발명의 경우, 상기 접지배선(도 3의 325)의 길이가 상기 접지단자(도 3의 302)의 형상을 조정함에 따라 상기 반도체 칩(도 3의 305)과 상기 다이 패드(도 3의 301) 간의 거리에 구애받지 아니하고 임의적으로 연장될 수 있음을 알 수 있다. 따라서, 상기 접지배선(325)의 길이를 상기 신호배선(323)과 동일한 길이 또는 그 이상의 길이로 충분히 연장할 수 있다. 보다 바람직하게는, 상기 접지배선(325)의 길이는 상기 신호배선(323)의 80% 내지 300%로 조정할 수 있다. 길이가 연장된 상기 접지배선(325)를 상기 신호배선(323)과 인접하여 나란히 배치할 경우 상기 신호배선(323)에 대한 전기적 차폐효과를 획기적으로 향상시킬 수 있게 된다.2 and 3, when comparing the configuration of the semiconductor device according to the prior art and the semiconductor device according to the present invention, the advantages of the present invention can be clearly seen in terms of electrical shielding effect. In the conventional semiconductor device, the length of the ground line 225 of FIG. 2 provided for electrical shielding of the signal line 223 of FIG. 2 is significantly shorter than that of the signal line 223 of FIG. 2. A substantial portion of the signal wiring (223 in FIG. 2) floating in space is provided open to coupling noise. In contrast, in the present invention, the length of the ground wire 325 of FIG. 3 adjusts the shape of the ground terminal 302 of FIG. 3, and thus the semiconductor chip 305 of FIG. It can be seen that it can be arbitrarily extended regardless of the distance between 301 of FIG. 3. Therefore, the length of the ground wiring 325 can be sufficiently extended to the same length or longer than the signal wiring 323. More preferably, the length of the ground wiring 325 may be adjusted to 80% to 300% of the signal wiring 323. When the ground wire 325 having an extended length is disposed in parallel with the signal wire 323, the electrical shielding effect on the signal wire 323 can be significantly improved.

도 4는, 본 발명의 제 2 실시예들에 따른 반도체장치의 일부 구조를 설명하는 평면도이다.4 is a plan view illustrating some structures of semiconductor devices according to example embodiments of the present inventive concept.

도 4를 참조하면, 제 2 실시예들에 따른 반도체장치의 경우 접지단자(402)를 구비한 다이 패드(401) 상에 반도체 칩(405)이 위치한다. 상기 반도체 칩(405)의 신호패드(407)는 신호배선(423)에 의하여 신호단자(415)와 연결된다. 상기 반도체 칩(405)의 접지패드(409)는 접지배선(425)에 의하여 상기 접지단자(402)와 연결된다.Referring to FIG. 4, in the semiconductor device according to the second exemplary embodiment, the semiconductor chip 405 is positioned on the die pad 401 having the ground terminal 402. The signal pad 407 of the semiconductor chip 405 is connected to the signal terminal 415 by a signal wiring 423. The ground pad 409 of the semiconductor chip 405 is connected to the ground terminal 402 by a ground wiring 425.

제 2 실시예들에 따른 상기 반도체장치는 상기 신호배선(423)에 대한 상기 접지배선(425)의 전기적 차폐효과를 극대화하기 위하여 제 1 실시예들에 따른 상기 반도체장치(도 3에 도시)의 일부 구조를 변형한 것이다. 이를 위해, 상기 신호단자(415) 일단의 평면 형상을 "L" 자 형의 요철 형태로 변형하였다. 상기 신호단자(415)와 마주보는 상기 접지단자(402) 또한 상기 신호단자(415)와 대응되는 형상 으로 변형되어 평면상에서 좁은 이격거리를 두고 서로 맞물리도록 배치된다. 그 결과, 상기 신호배선(423)과 상기 접지배선(425) 사이가 더욱 좁혀짐으로써 전기적 차폐효과가 증가할 수 있게 된다. 이에 더하여, 상기 신호배선(423)의 상당 부분이 상기 접지단자(402)와 평면도 상에서 중첩하게 되어 전기적 차폐효과는 배증될 수 있다.The semiconductor device according to the second exemplary embodiment of the semiconductor device (shown in FIG. 3) according to the first exemplary embodiment of the present invention may maximize the electrical shielding effect of the ground line 425 with respect to the signal line 423. Some structural variations. To this end, the planar shape of one end of the signal terminal 415 is deformed into an “L” shaped unevenness. The ground terminal 402 facing the signal terminal 415 is also deformed into a shape corresponding to the signal terminal 415 so as to be engaged with each other with a narrow separation distance on a plane. As a result, the electrical shielding effect can be increased by narrowing between the signal wiring 423 and the ground wiring 425. In addition, since a substantial portion of the signal wiring 423 overlaps the ground terminal 402 on the top view, the electrical shielding effect can be doubled.

도 5는, 본 발명의 제 3 실시예들에 따른 반도체장치의 일부 구조를 설명하는 평면도이다.5 is a plan view illustrating some structures of semiconductor devices according to third exemplary embodiments of the present invention.

도 5를 참조하면, 제 3 실시예들에 따른 반도체장치의 경우 신호단자(515)의 일단의 평면 형상이 "T"자 형의 요철 형태를 가진다. 상기 신호단자(515)에 대응하는 접지단자(502) 또한 상기 신호단자(515)에 맞물리도록 변형되어 있다. 그 결과, 신호배선(523)의 좌우에 매우 근접하여 한 쌍의 접지배선(525a, 525b)이 배치할 수 있게 된다. 상기 한쌍의 접지배선(525a, 525b)에 의한 강력한 전기적 차폐는 상기 신호배선(523)이 커플링 노이즈에 대해 취약한 고속 신호선일 경우 특히 효과가 있을 수 있다.Referring to FIG. 5, in the semiconductor device according to the third exemplary embodiment, a planar shape of one end of the signal terminal 515 has a “T” shaped unevenness. The ground terminal 502 corresponding to the signal terminal 515 is also modified to engage the signal terminal 515. As a result, the pair of ground wirings 525a and 525b can be arranged very close to the left and right of the signal wiring 523. Strong electrical shielding by the pair of ground lines 525a and 525b may be particularly effective when the signal line 523 is a high speed signal line that is vulnerable to coupling noise.

도 6은, 본 발명의 제 4 실시예들에 따른 반도체장치의 일부 구조를 설명하는 평면도이다.6 is a plan view illustrating some structures of semiconductor devices according to fourth embodiments of the present invention.

도 6를 참조하면, 제 4 실시예들에 따른 반도체장치의 경우 한 쌍의 신호단자들(615a, 615b)이 그 일단의 평면 형상이 "L"자 형의 요철 형태를 가진 채, 서로 등을 맞댄 상태로 근접하여 나란히 배치되어 있다. 상기 한 쌍의 신호단자들(615a, 615b)에 대응하는 접지단자(602) 또한 상기 한 쌍의 신호단자들(615a, 615b)에 좁 은 이격거리를 두고 맞물리도록 변형되어 있다. 제 4 실시예들에 따른 상기 반도체장치는 한 쌍의 신호배선들(623a, 623b)로 이루어진 신호배선 군(signal wire group) 전체에 대한 전기적 차폐효과를 극대화시키기 위해 제 1 실시예들에 따른 상기 반도체장치(도 3에 도시)의 구조를 일부 변형한 것이다. 상기 한 쌍의 신호배선들(623a, 623b)은, 써데스(SERDES; serializer/deserializer) 칩의 전기신호의 입출력에 통상적으로 쓰이는 디퍼렌셜 시그널 페어(differential signal pair)를 구성하는 포지티브 시그널(positive signal)과 네거티브 시그널(negative signal)을 위한 것일 수 있다. 상기 반도체장치의 경우, 상기 한 쌍의 신호단자들(615a, 615b)과 상기 접지단자(602)의 변형에 의해 상기 한 쌍의 신호배선들(623a, 623b)의 좌우 양측에 한 쌍의 접지배선들(625a, 625b)이 매우 좁은 이격거리를 두고 배치된다. 그 결과, 상기 한 쌍의 신호배선들(623a, 623b)에 대한 전기적 차폐를 더욱 효과적으로 할 수 있게 된다.Referring to FIG. 6, in the semiconductor device according to the fourth exemplary embodiment, a pair of signal terminals 615a and 615b have one end of planar shape having an “L” shaped unevenness, and the like. They are arranged side by side in close proximity. The ground terminal 602 corresponding to the pair of signal terminals 615a and 615b is also modified to engage with the pair of signal terminals 615a and 615b at a narrow separation distance. The semiconductor device according to the fourth embodiments of the present invention may provide an electrical shielding effect for the entire signal wire group including a pair of signal wires 623a and 623b. The structure of the semiconductor device (shown in FIG. 3) is partially modified. The pair of signal wires 623a and 623b constitute a positive signal constituting a differential signal pair commonly used for input and output of an electrical signal of a SERDES (serializer / deserializer) chip. And negative signal. In the case of the semiconductor device, a pair of ground wires are formed on both left and right sides of the pair of signal wires 623a and 623b by the deformation of the pair of signal terminals 615a and 615b and the ground terminal 602. The fields 625a and 625b are arranged at very narrow distances. As a result, electrical shielding of the pair of signal wires 623a and 623b can be more effectively performed.

이상 본 발명의 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예들에 한정되지 않고 본 발명의 사상 내에서 여러 가지의 다른 형태로 변형될 수 있다. 예를 들면, 반도체장치를 구성하는 신호배선들 모두에 대해, 각각의 상기 신호배선들에 인접한 위치에서 전기적 차폐를 위한 접지배선을 제공할 필요는 없다. 즉, 고속의 반도체소자(high speed semiconductor device)에서 커플링 노이즈에 취약한 특정의 신호전송용 단자들을 고려하여 다이 패드의 형태, 접지단자들의 위치 및 형태, 그리고 신호단자들의 형태를 다양하게 설계하는 것이 바람직하다.Although a preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiments and may be modified in various other forms within the spirit of the present invention. For example, it is not necessary to provide a grounding wiring for electrical shielding at a position adjacent to each of the signal wirings for all the signal wirings constituting the semiconductor device. That is, in consideration of specific signal transmission terminals vulnerable to coupling noise in a high speed semiconductor device, it is necessary to design the die pad, the position and shape of the ground terminals, and the shape of the signal terminals in various ways. desirable.

상술한 바와 같이 본 발명에 따르면, 다이 패드의 측면에 신장된 접지단자가 배치된 리드 프레임을 구비한 반도체 장치를 제공한다. 상기 접지단자에 의해 반도체 칩의 접지패드를 상기 다이 패드와 연결시키는 접지배선의 길이를 임의적으로 연장시킬 수 있다. 길이가 연장된 상기 접지배선은 상기 반도체 칩의 신호패드와 상기 리드 프레임의 신호단자를 연결시키는 신호배선의 전기적 차폐에 제공될 수 있는바, 이 경우 상기 신호배선의 오픈(open) 영역을 크게 줄일 수 있다. 그 결과, 인접한 고속 신호선간에 발생할 수 있는 커플링 노이즈를 줄이는 데 있어서 종래기술에 비하여 월등한 효과를 얻을 수 있다.As described above, according to the present invention, there is provided a semiconductor device having a lead frame having a ground terminal extending on a side of a die pad. The ground terminal may arbitrarily extend the length of the ground wiring connecting the ground pad of the semiconductor chip to the die pad. The length of the ground line may be provided to the electrical shielding of the signal line connecting the signal pad of the semiconductor chip and the signal terminal of the lead frame. In this case, the open area of the signal line may be greatly reduced. Can be. As a result, a superior effect can be obtained as compared with the prior art in reducing coupling noise that may occur between adjacent high speed signal lines.

Claims (8)

다이 패드(die pad), 상기 다이 패드의 측면에 신장된 접지단자, 및 상기 다이 패드와 분리된 신호단자를 구비하는 리드 프레임(lead frame);A lead frame including a die pad, a ground terminal extending on a side of the die pad, and a signal terminal separated from the die pad; 상기 다이 패드 상에 장착되고 신호패드 및 접지패드를 구비하는 반도체 칩;A semiconductor chip mounted on the die pad and having a signal pad and a ground pad; 상기 신호패드 및 상기 신호단자 간을 연결하는 신호배선; 및A signal wire connecting the signal pad and the signal terminal; And 상기 접지패드 및 상기 접지단자 간을 연결하되, 상기 신호배선에 인접하나 상기 신호배선과 분리되도록 배치된 접지배선을 포함하는 반도체장치.And a ground line connected between the ground pad and the ground terminal and adjacent to the signal line but separated from the signal line. 제 1 항에 있어서,The method of claim 1, 상기 접지배선의 길이는 상기 신호배선보다 길거나 같되, 상기 접지배선 및 상기 신호배선 간의 중첩된 길이는 상기 신호배선과 같은 것을 특징으로 하는 반도체 장치.The length of the ground line is longer than or equal to the signal line, and the overlapping length between the ground line and the signal line is the same as the signal line. 제 1 항에 있어서,The method of claim 1, 상기 신호배선에 인접하고 상기 신호배선과 분리되도록 배치된 다른 접지배선을 더 포함하되, 상기 접지배선들 사이에 상기 신호배선이 배치된 반도체장치.And another ground line adjacent to the signal line and arranged to be separated from the signal line, wherein the signal line is disposed between the ground lines. 제 3 항에 있어서,The method of claim 3, wherein 상기 접지단자는 상기 신호단자의 일단과 좌우로 중첩하여 나란히 배치된 것 을 특징으로 하는 반도체장치.And wherein the ground terminals overlap one end of the signal terminal to the left and right to be arranged side by side. 제 1 항에 있어서,The method of claim 1, 상기 접지배선의 길이는 상기 신호배선의 80% 내지 300%인 것을 특징으로 하는 반도체장치.The length of the ground wiring is a semiconductor device, characterized in that 80% to 300% of the signal wiring. 제 1 항에 있어서,The method of claim 1, 상기 신호단자의 일단은 평면도 상에서 보여질 때 요철 형상을 가지되, 상기 접지단자는 상기 신호단자의 상기 요철 형상에 평행하게 대응하는 형상인 것을 특징으로 하는 반도체장치.Wherein one end of the signal terminal has a concave-convex shape when viewed in a plan view, and the ground terminal has a shape corresponding to the concave-convex shape of the signal terminal in parallel. 제 1 항에 있어서,The method of claim 1, 상기 접지단자는 상기 신호배선에 평면도 상에서 보여질 때 중첩된 것을 특징으로 하는 반도체장치.And the ground terminal is superimposed on the signal wiring when viewed in plan view. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩은 써데스 칩(SERDES chip)인 것을 특징으로 하는 반도체장치.The semiconductor chip is a semiconductor device, characterized in that the SERDES chip (SERDES chip).
KR1020070027631A 2007-03-21 2007-03-21 Semiconductor chip package having reduced coupling noise KR20080086042A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742263A (en) * 2014-12-30 2016-07-06 美国亚德诺半导体公司 High frequency integrated circuit and packaging for same
CN111630717A (en) * 2018-01-23 2020-09-04 东友精细化工有限公司 Thin film antenna circuit connection structure and display device including the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742263A (en) * 2014-12-30 2016-07-06 美国亚德诺半导体公司 High frequency integrated circuit and packaging for same
CN111630717A (en) * 2018-01-23 2020-09-04 东友精细化工有限公司 Thin film antenna circuit connection structure and display device including the same
US11557830B2 (en) 2018-01-23 2023-01-17 Dongwoo Fine-Chem Co., Ltd. Film antenna-circuit connection structure and display device including the same
CN111630717B (en) * 2018-01-23 2023-02-17 东友精细化工有限公司 Thin film antenna circuit connection structure and display device including the same

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