JPH0226059A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH0226059A
JPH0226059A JP63176618A JP17661888A JPH0226059A JP H0226059 A JPH0226059 A JP H0226059A JP 63176618 A JP63176618 A JP 63176618A JP 17661888 A JP17661888 A JP 17661888A JP H0226059 A JPH0226059 A JP H0226059A
Authority
JP
Japan
Prior art keywords
electrodes
inner lead
semiconductor element
lead
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63176618A
Other languages
Japanese (ja)
Inventor
Takayasu Handa
半田　隆保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63176618A priority Critical patent/JPH0226059A/en
Publication of JPH0226059A publication Critical patent/JPH0226059A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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Abstract

PURPOSE:To make the title device multipinned by making electrodes of a semiconductor element have a two-row electrode arrangement while forming a two-stage type inner lead form composed of two layers. CONSTITUTION:A first metal layer consisting of a first layer inner lead 5 as an inner lead, a tab 4, whereon a semiconductor element 2 is to be placed, and a tab-suspending lead 8, and a second metal layer consisting of a second layer inner lead 5a or the like form a two-stage type construction by a method wherein both layers are adhered with an electric insulating adhesive 7. Then, an electrode, wherein outer peripheral electrodes 3 and inner peripheral electrodes 3a are in two rows arranged, is formed around on one main surface of the semiconductor element 2. Further, the outer peripheral electrode 3 and the first layer inner lead 5 are connected with a gold bonding wire 6a, while similarly the inner peripheral electrode 3a and the second layer inner lead 5a are connected with a gold bonding wire 6b. In this way, multipinning can be realized through a two-row arrangement and two-layer constitution.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の樹脂封止型半導体装置は、第３Ａ、Ｂ図
に示す様に、半導体素子２２の一主面上の周囲にはほぼ
直線上に一列に配列された外周電極２３と、半導体素子
２２の周囲には前記外周電極２３に対応した複数の、内
部リード１５を有し、外周電極２３と内部リード１５を
有し、外周電極２３と内部リード１５間を金やアルミニ
ウムのボンディングワイヤ１６により結線し、その後、
これらの部分はエポキシ等の封止樹脂９で封止し、樹脂
封止型半導体装置を構成していた。Conventionally, this type of resin-sealed semiconductor device has, as shown in FIGS. 3A and 3B, peripheral electrodes 23 arranged in a substantially straight line around one main surface of a semiconductor element 22, and a semiconductor The element 22 has a plurality of inner leads 15 around the outer circumferential electrode 23 corresponding to the outer circumferential electrode 23, the outer circumferential electrode 23 and the inner lead 15, and a gold or aluminum bonding wire 16 between the outer circumferential electrode 23 and the inner lead 15. Connect the wires by, and then
These parts were sealed with a sealing resin 9 such as epoxy to form a resin-sealed semiconductor device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

近年、半導体素子の高集積化技術は急速に進み、多機能
化、システム化の進む中で、樹脂封止型半導体装置にお
いても、多ピン化の強い要求があるが、上述したこの種
の半導体装置では、以下に説明する理由により多ビン化
が制限される問題点がある。In recent years, high integration technology for semiconductor devices has progressed rapidly, and with the advancement of multifunctionality and systemization, there is a strong demand for increased pin count in resin-sealed semiconductor devices. The device has a problem in that the number of bins is limited for reasons explained below.

その第１として、内部リード側は、一般に０゜１５〜０
．２５ｍｍ厚の４２％Ｎ１−残Ｆｅ合金や銅系の素材を
用ることが多く、この場合、エツチングやスタンピング
によるパターン形成方法では、板厚の倍かその８０％の
ピッチにパターン形成し、しかも、そのリードにボンデ
ィング細線を接続することが現状の技術のほぼ限界とさ
れている。従って、１０×１０ＩＩＩＩ＋２の半導体素
子で、０．１５＋ｌＩ＋ａ厚材のリードを考えた場合、
従来構成のリードフレームでは、約１５０〜２００ビン
が限界となる。First, the internal lead side is generally 0°15 to 0
．． A 25 mm thick 42% N1-residue Fe alloy or copper-based material is often used, and in this case, pattern formation by etching or stamping involves forming a pattern at a pitch that is twice the thickness of the plate or 80% of it. , connecting a thin bonding wire to the lead is considered to be almost the limit of current technology. Therefore, when considering a lead of 0.15+lI+a thick material for a 10×10III+2 semiconductor element,
A conventional lead frame has a limit of about 150 to 200 bins.

一方、半導体素子側の電極のピッチはボンディング方法
により若干具るが、０．１５＋ｕ＋が現状技術の限界で
、１０Ｘ１０ｎｎ２の半導体素子を考えた場合は約２０
０ビン強となる。従って、１０×１ｏＩｌａ１１２程度
の半導体素子を考えた場合の両者の組合せにおける多ビ
ン化は、約２００ビン程度で制限される。On the other hand, the pitch of the electrodes on the semiconductor element side varies slightly depending on the bonding method, but 0.15+u+ is the limit of current technology, and when considering a 10x10nn2 semiconductor element, approximately 20
That's just over 0 bottles. Therefore, when considering a semiconductor element of about 10×1oIla112, the number of bins in the combination of both is limited to about 200 bins.

本発明の目的は多ビン化が可能な樹脂封止型半導体装置
を提供することにある。An object of the present invention is to provide a resin-sealed semiconductor device that can be made into multiple bottles.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の樹脂封止型半導体装置は、半導体素子の一主面
上の周囲には少なくとも２列の電極配列を有し、該電極
のそれぞれに対応する内部リードも少なくとも２層で構
成する多段型の先端形状を有し、前記電極とそれぞれに
対応する前記内部リード先端間が金属ボンディングワイ
ヤで結合されている。The resin-sealed semiconductor device of the present invention is a multi-stage type semiconductor device having at least two rows of electrode arrays around one main surface of a semiconductor element, and internal leads corresponding to each of the electrodes also consisting of at least two layers. The electrodes and the corresponding internal lead tips are connected by metal bonding wires.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１Ａ、Ｂ図は本発明の第１の実施例の部分拡大平面図
及びＡ−Ａ’線断面図である。Figures 1A and 1B are a partially enlarged plan view and a sectional view taken along the line AA' of the first embodiment of the present invention.

第１の実施例は、第１Ａ、Ｂ図に示すように、まず、内
部リードとして第２層内部リード５ａよリワイヤボディ
ング可能な分だけ突出して形成した第１層内部リード５
と、半導体素子２を搭載するタブ４及びタブ吊りリード
８等から成る第１の金属層と、第２層内部リード５ａ等
からなる第２の金属層をエポキシ樹脂の如き電気的絶縁
接着剤７で両金属層間を接着して２段型構造を形成した
。In the first embodiment, as shown in FIGS. 1A and 1B, a first layer internal lead 5 is formed as an internal lead so as to protrude from the second layer internal lead 5a by an amount that can be rewired.
Then, a first metal layer consisting of a tab 4 on which the semiconductor element 2 is mounted, a tab suspension lead 8, etc., and a second metal layer consisting of a second layer internal lead 5a, etc. are bonded with an electrically insulating adhesive 7 such as an epoxy resin. The two metal layers were bonded together to form a two-stage structure.

一方、半導体素子２の一主面上の周囲には外周電極３と
内周電極３ａの２列配列した電極を形成した。On the other hand, two rows of electrodes, an outer electrode 3 and an inner electrode 3a, were formed around one principal surface of the semiconductor element 2.

次に、外周電極３と第１層内部リード５間を金ボンディ
ングワイヤ６ａにて結線し、同様に、内周電極３ａと第
２層内部リード５ａ間を金ボンディングワイヤ６ｂにて
結線し、その後、封止樹脂９にて樹脂封止を行い、樹脂
封止型半導体装置１を完成させた。Next, a gold bonding wire 6a is used to connect the outer electrode 3 and the first layer internal lead 5, and similarly, a gold bonding wire 6b is used to connect the inner electrode 3a and the second layer internal lead 5a. Then, resin sealing was performed using sealing resin 9 to complete a resin-sealed semiconductor device 1.

第２図は本発明の第２の実施例の部分拡大平面図である
。FIG. 2 is a partially enlarged plan view of a second embodiment of the invention.

第１の実施例は、第１Ａ図に示すように、半導体素子２
の内周電極３ａの配置は対応する外周電極３に対し真内
側に形成した例であるが、第２の実施例では、外周電極
１３間の中間に内周電極１３ａを形成した干瓢形状の２
列配列電極を形成した例である。In the first embodiment, as shown in FIG. 1A, a semiconductor element 2
The arrangement of the inner electrodes 3a is an example in which the inner electrodes 3a are formed directly inside the corresponding outer electrodes 3, but in the second embodiment, the inner electrodes 3a are formed in the middle between the outer electrodes 13 in a gourd shape.
This is an example in which column array electrodes are formed.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、半導体素子の電極を２列の
電極配列にすることにより、従来例と同等の素子サイズ
を想定しても約２倍の電極数を形成することが可能とな
り、又、リード側においても、２層で構成する２段型内
部リード形状にすることにより、約２倍のリードを作る
ことが可能になる。すなわち、前述した様に、１０×１
０ＩＩＩｆｆｉ２の素子サイズで、０．１５厚リード材
を用いた現状技術の限界が約２００ビンで制限されるの
に対し、２列配置化と２層化により約２倍の４００ビン
の多ビン化が実現可能となる。多列配置化と多層化の組
合せにより、より多ビン化を可能にするという効果があ
る。As explained above, in the present invention, by arranging the electrodes of a semiconductor element in two rows, it is possible to form approximately twice the number of electrodes even assuming the same element size as in the conventional example. Also, on the lead side, by adopting a two-stage internal lead shape composed of two layers, it is possible to make approximately twice as many leads. That is, as mentioned above, 10×1
With the element size of 0IIIffi2, the current technology using 0.15 thick lead material is limited to about 200 bins, but by using two rows and two layers, the number of bins can be doubled to about 400 bins. becomes possible. The combination of multi-row arrangement and multi-layer arrangement has the effect of enabling a larger number of bins.

【図面の簡単な説明】[Brief explanation of the drawing]

第１Ａ、Ｂ図は本発明の第１の実施例の部分拡大平面図
及びＡ−Ａ’線断面図、第２図は本発明の第２の実施例
の部分拡大平面図、第３Ａ、Ｂ図は従来の樹脂封止型半
導体装置の一例の平面図及びＢ−Ｂ’線断面図である。 １．１１・・・樹脂封止型半導体装置、２，１２゜２２
・・・半導体素子、３．１３．２３・・・外周電極、３
ａ、１３ａ・・・内周電極、４・・・タブ、５・・・第
１層内部リード、５ａ・・・第２層内部リード、６ａ、
６ｂ・・・ボンディングワイヤ、７・・・接着材、８・
・・タブ吊りリード、９・・・封止樹脂、１５・・・内
部リード。Figures 1A and B are a partially enlarged plan view and a sectional view taken along line A-A' of the first embodiment of the present invention; Figures 2 are a partially enlarged plan view of the second embodiment of the present invention; and Figures 3A and B are The figures are a plan view and a sectional view taken along the line BB' of an example of a conventional resin-sealed semiconductor device. 1.11...resin-sealed semiconductor device, 2,12°22
... Semiconductor element, 3.13.23 ... Outer electrode, 3
a, 13a... Inner circumferential electrode, 4... Tab, 5... First layer internal lead, 5a... Second layer internal lead, 6a,
6b...Bonding wire, 7...Adhesive material, 8.
...Tab hanging lead, 9...Sealing resin, 15...Internal lead.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の一主面上の周囲には少なくとも２列の電極
配列を有し、該電極のそれぞれに対応する内部リードも
少なくとも２層で構成する多段型の先端形状を有し、前
記電極とそれぞれに対応する前記内部リード先端間を金
属ボンディングワイヤで結合することを特徴とする樹脂
封止型半導体装置。The semiconductor element has at least two rows of electrode arrays around its periphery on one main surface, and the internal leads corresponding to each of the electrodes also have a multi-stage tip shape composed of at least two layers, and each of the electrodes and A resin-sealed semiconductor device characterized in that the tips of the internal leads corresponding to the above are connected by a metal bonding wire.
JP63176618A 1988-07-14 1988-07-14 Resin-sealed semiconductor device Pending JPH0226059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63176618A JPH0226059A (en) 1988-07-14 1988-07-14 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63176618A JPH0226059A (en) 1988-07-14 1988-07-14 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH0226059A true JPH0226059A (en) 1990-01-29

Family

ID=16016723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63176618A Pending JPH0226059A (en) 1988-07-14 1988-07-14 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH0226059A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
JP2003078100A (en) * 2001-09-06 2003-03-14 Sony Corp Semiconductor device and manufacturing method therefor
JP2008186889A (en) * 2007-01-29 2008-08-14 Denso Corp Semiconductor device
CN105950900A (en) * 2016-05-06 2016-09-21 河南理工大学 Manufacturing method of high-strength micro-fine silver alloy bonding wire for small wafer LED packaging

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
JP2003078100A (en) * 2001-09-06 2003-03-14 Sony Corp Semiconductor device and manufacturing method therefor
JP4674427B2 (en) * 2001-09-06 2011-04-20 ソニー株式会社 Manufacturing method of semiconductor device
JP2008186889A (en) * 2007-01-29 2008-08-14 Denso Corp Semiconductor device
CN105950900A (en) * 2016-05-06 2016-09-21 河南理工大学 Manufacturing method of high-strength micro-fine silver alloy bonding wire for small wafer LED packaging

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