JPH02260539A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a MOSFET to be manufactured easily by forming an ion- implantation mask selectively on the side surface on the drain side of a gate electrode by utilizing an application film which is formed selectively and by forming a drain and a source region using this mask. CONSTITUTION:A gate electrode 3 is formed on a semiconductor substrate 1 and a shallow junction region is formed on the semiconductor substrate 1. Then, after covering the source side part of the gate electrode 3 selectively with an application film 6, an insulting film 5 is formed on the entire surface and then it is subjected to anisotropic etching, thus leaving an insulation film 5 only on the side surface on the drain side of the gate electrode 3 as an ion- implantation mask 7. After that, deep junction regions 8 and 9 as source and drain regions are formed by utilizing the gate electrode 3 and the ion- implantation mask 7. Thus, it is possible to form the ion-implantation mask 7 selectively on the side surface on the drain side of the gate electrode 3 and to offset the drain region for the gate electrode 3 by utilizing this ion- implantation mask 7 and to produce the LDD structure only on the drain side by utilizing this offset. Therefore, it is possible to produce a MOSFET easily.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate field effect transistor (MOSF).
Regarding semiconductor devices equipped with L D D (
Lightly Doped Drain) structure M
The present invention relates to a method of manufacturing an OSFET.

[Conventional technology]

In recent years, MOSFETs with an LDD structure have been proposed, in which shallow, low-concentration junctions are formed between the gate electrode and each of the source and drain regions. However, it cannot be denied that this structure increases the source resistance, lowers gm, and has the problem of deteriorating the noise figure as an amplifier.

For this reason, conventionally, a structure in which the above-mentioned shallow junction is formed only on the drain side has been proposed, and the cutoff characteristics of the MOSFET due to the short channel effect are improved without increasing the source resistance.

[Problem to be solved by the invention]

However, forming a shallow coupling only on the drain side in this way makes it impossible to directly utilize the conventional manufacturing method that takes advantage of the symmetry of MOSFETs. In particular, since shallow junctions are required to be formed minutely, manufacturing of this type of MOSFET becomes extremely complicated and difficult.

An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to easily manufacture such a MOSFET.

[Means to solve the problem]

A first method of manufacturing a semiconductor device of the present invention includes forming a gate electrode on a semiconductor substrate and forming a shallow junction region on the semiconductor substrate, and then selectively covering a source side portion of the gate electrode with a coating film. An insulating film is formed on the entire surface and anisotropically etched to leave the insulating film as an ion implantation mask only on the drain side of the gate electrode, and then the gate electrode and the ion implantation mask are used. The method includes a step of forming deep junction regions as drain and source regions.

Further, in the second manufacturing method of the present invention, similarly to the first manufacturing method, after forming a gate electrode and a shallow junction region on a semiconductor substrate, an insulating film is formed on the entire surface and this is anisotropically etched. The insulating film is left as an ion implantation mask on both sides of the gate electrode, and the ion implantation mask on the drain side is selectively covered with a coating film, and the ion implantation mask on the source side is etched away. The process includes forming deep junction regions as drain and source regions in the substrate.

Furthermore, in the third manufacturing method of the present invention, after forming a gate electrode on a semi-insulating semiconductor substrate, an insulating film is formed on the entire surface and anisotropically etched to form the insulating film on both sides of the gate electrode. The ion implantation mask on the drain side is left as an ion implantation mask, the ion implantation mask on the drain side is selectively covered with a coating film, the ion implantation mask on the source side is etched away, and then a deep junction is formed on the semiconductor substrate as a drain region and a source region. forming a shallow junction region after removing the ion implant mask.

[Effect]

In any of the above manufacturing methods, an ion implantation mask can be selectively formed only on the side surface of the gate electrode on the drain side.
This ion implantation mask is used to offset the drain region with respect to the gate electrode, and this offset can be used to manufacture an LDD structure only on the drain side.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(First Example) FIG. 1 is a sectional view of an LDD structure MOSFET manufactured by the manufacturing method of the present invention. In the figure, I is a p-type silicon substrate, and a gate electrode 3 is placed on a gate oxide film 2.
is formed and covered with an insulating film 1o. Further, n-type diffusion regions 8 and 9 are formed in the p-type silicon substrate 1 to constitute source/drain regions, and the n-type diffusion regions 8 and 9 are formed on the drain side.
A type diffusion region 4 is formed to constitute an LDD. In addition,
7 is an ion implantation mask used when constructing this LDD, and 13 and 14 are a drain electrode and a source electrode, respectively.

Next, the method for manufacturing the MOSFET shown in FIG.
This will be explained using step-by-step cross-sectional views of FIGS. (a) to (g).

First, as shown in FIG. 2(a), a gate oxide film 2 is formed on a p-type silicon substrate 1, and a gate electrode 3 is formed thereon. In this case, polycrystalline silicon, W, Mo, and compounds thereof are used as materials for the gate electrode 3. After forming a shallow n-type diffusion region 4 using the gate electrode 3 as a mask by ion implantation, a polyimide film 5 is coated on the entire surface and cured at 450° C. to planarize it.

The conditions for ion implantation were to use 31p- (phosphorus), an acceleration voltage of 50 KeV, and a dose of 16 x 10 "cm-".
If the depth is reduced to approximately 0.1 μm, the depth will be approximately 0.1 μm.

Next, as shown in FIG. 2(b), a resin film 6 made of, for example, a negative resist is formed to cover the source side portion of the gate electrode 3 and its vicinity. At this time, the polyimide film 5
By using an etching back method, the end portion can be formed into a tapered shape.

Next, as shown in FIG. 2(c), the polyimide film 5 is removed by etching with a hydrazine aqueous solution using the resin film 6 as a mask. As a result, the polyimide film 5 is left in a state covering the source side portion of the gate electrode 3 and its vicinity, and the opposite end portion is tapered to follow the resin 1116. Furthermore, after the resin film 6 is removed entirely, a plasma nitride film 7 is formed on the entire surface.

Next, as shown in FIG. 2(d), the plasma nitride film 7 is etched using a reactive ion etching method, leaving the plasma nitride film 7 only on the side surface of the gate electrode 3 on the drain side, and using an ion implantation mask. Form as 7. At this time, since the polyimide M5 has a tapered shape on the source side of the gate electrode 3, the plasma nitride film 7 is not left behind.

At this time, the underlying gate oxide film 2 and plasma nitride film 7
Because it is necessary to increase the selection ratio with NF3, C
Hz F, CH, F, etc. may be used as the etching gas, and the etching selectivity of the two can be set to 10 to 50.

Next, as shown in FIG. 2(e), the polyimide film 6 is completely removed with a hydrazine aqueous solution. Thereafter, deep n+ type diffusion regions 8 and 9 as a drain and a source, whose drain sides are offset, are formed by ion implantation on the entire surface. For example, if 31P'' is used, the acceleration voltage is 150 KeV, and the dose is about 1X10''cm -'', the junction depth is 0.3 μm and the two-layer resistance is about 1500 Ω/hole.

Next, as shown in FIG. 2(f), an insulating film 10 made of, for example, a PSG film is formed. Thereafter, the drain opening 11 and the source opening 11 are opened using a resist (not shown) as a mask.

Next, as shown in FIG. 2(g), the drain region 8. is passed through the drain hole 11 and the source hole 12. A drain electrode 13 and a source electrode 14 respectively connected to the source region 9 are formed to obtain an LDD structure MOSFET.

Note that in this example, the gate oxide WA2 on the drain and source regions is not removed, but if this is to be removed,
The gate oxide film 2 may be removed in the step shown in FIG. 2(a).

Here, a plasma oxide film or PSGlil may be used as the material for the ion implantation mask 7. However, in this case, since a selectivity with respect to the gate oxide film 2 cannot be obtained in reactive ion etching, as shown in FIG. 3(a), the gate electrode 3. Polyimide film 6. Ion implantation mask 7
It is unavoidable that the gate oxide film 2 becomes thinner in the region not covered by this.

Therefore, as shown in FIG. 3(b), immediately before the subsequent step, that is, the step shown in FIG. 2(e), reactive ion etching using gas such as CHF is performed to oxidize the gate W4.
It is necessary to increase the selectivity between the gate oxide film 2 and the silicon substrate 1, and to etch the gate oxide film 2 to expose the silicon substrate.

(Second Embodiment) FIGS. 4(a) to 4(f) are cross-sectional views showing the second embodiment of the present invention in the order of steps, and show another method of forming the LDD structure of FIG. 1.

First, as shown in FIG. 4(a), a gate oxide film 2 is formed on a p-type silicon substrate 1, and a gate electrode 3 is provided thereon. In this case, the same material as in the first embodiment can be used for the gate electrode.

Next, as shown in FIG. 4(b), a shallow n-type diffusion region 4 is formed by ion implantation. The conditions for ion implantation are 3.
'P', acceleration voltage 50KeV, dose 6
If the depth is about 10 "cra-", the depth will be 0.1
It becomes about μm. Furthermore, a film serving as a mask for ion implantation, for example, a silicon oxide film 7A, is formed on the entire surface.

Next, as shown in FIG. 4C, etching is performed using a reactive ion etching method using, for example, CH3F gas to form a silicon oxide film 7 on the side wall of the gate electrode 3.
A remains and is formed as an ion implantation mask.

Next, as shown in FIG. 4(d), after covering the ion implantation mask 7A on the drain side with a selectively formed coating film, in this case a resin film 6A, the ions on the source side are etched with an HF-based etching solution, for example. The implantation mask 7A is removed by etching.

Next, as shown in FIG. 4(e), after removing the resin film 6A, deep n-type diffusion regions 8 and 9 with the drain side offset are formed on the entire surface by ion implantation.
When ff1p+ is used as the ion species, the acceleration voltage is 150 KeV, and the dose is about I x 10 "ctrr-", the junction depth becomes 0.3 μm and the layer resistance becomes 1500 Ω/hole.

Thereafter, an insulating film 10 such as PSG is formed over the entire surface.

Thereafter, as shown in FIG. 4(f), a drain hole 11 and a source hole 12 are opened using a resist (not shown) as a mask, and after removing the resist, a drain electrode 13 and a source electrode 14 are formed. do.

This method also makes it possible to form the LDD structure shown in FIG. However, in this case, the gate oxide film 2 is likely to be over-etched below the gate electrode 3, particularly on the source side, so it is necessary to perform the process shown in FIG. 4(c) with high precision. When this overetching of the gate oxide film 2 occurs, a constriction is likely to occur on the source side of the insulating film 10, which causes deterioration of the reliability.

(Third Embodiment) FIG. 5 shows an example in which the present invention is applied to a GaAs MESFET, and is a sectional view of the manufactured MESFET.

In the figure, 21 is a GaAs semi-insulating semiconductor substrate, 22
is an n layer, and a Schottky gate electrode 23 is formed on this GaAs substrate 21. Further, n'' regions 26 and 27 are formed on both sides of the Schottky gate electrode 23, and an n-95 region 28 is formed between the Schottky gate electrode 23 and the n4N region 26 on the drain side. 30
are drain and source ohmic electrodes, respectively.

Figures 6(a) to 6(d) show the MES of the LDD structure in Figure 5.
A method of manufacturing an FET is shown.

First, as shown in FIG. 6(a), an insulating GaAs substrate 21 is
Then, selective ion implantation is performed to form the n-layer 22. Then, a metal having a WSi, -W structure, for example, is formed on the entire surface by sputtering or the like to a thickness of 0.5 μm, and this is patterned to form a Schottky gate electrode 23. Thereafter, a silicon oxide film 24, for example, is deposited on the entire surface.

Next, as shown in FIG. 6(b), reactive ion etching is performed using CF 2 gas to leave the silicon oxide film 24 on both sides of the Schottky gate electrode 23, which is then formed as an ion implantation mask 24. Thereafter, the ion implantation mask 24 on the drain side is covered with a coating film, that is, a resin film 25.

Next, as shown in FIG. 6C, the ion implantation mask on the source side is removed by etching using the resin film 25 as a mask. For this etching, for example, an HF-based etching solution is used.

Next, as shown in FIG. 6(d), ions are implanted into the CyaAs substrate 21 to form n1 regions 26 and 27 as drains and sources whose drain sides are offset.At this time, resist is applied around the periphery. Cover with and n”?
After forming the il regions 26 and 27, the ion implantation mask 24 is removed by etching with an HF-based etching solution while leaving this resist.

Thereafter, as shown in FIG. 6(d), by implanting ions into the GaAs substrate 21, an n region 28 is formed at the location where the ion implantation mask 24 was present. Thereafter, the entire surface is covered with an annealing protective film, annealing is performed in H2, and the protective film is removed. Furthermore, n”?iI area 26
．． By selectively forming an ohmic metal such as AuGeNi on the drain ohmic electrode 27 shown in FIG. 5 and performing alloy heat treatment. A source ohmic electrode 30 is formed.

〔Effect of the invention〕

As explained above, the present invention utilizes a selectively formed coating film to selectively form an ion implantation mask only on the side surface of the gate electrode on the drain side, and uses this ion implantation mask to form the drain and source regions. Therefore, only the drain region can be offset from the gate electrode, and by using this offset, only the drain region can be
There is an effect that a D-structured MOSFET or MESFET FET can be manufactured.

[Brief explanation of drawings]

Figure 1 shows an LDD structure MOSFET that is the subject of the present invention.
2(a) to (g) are sectional views showing the first embodiment of the present invention in the order of steps for manufacturing the structure of FIG. 1, and FIGS. 3(a) and (b) are sectional views of 4(a) to <r) are sectional views showing the second embodiment of the present invention in the order of steps; FIG.
Cross-sectional view of LDD structure when applied to ESFET, No. 6
Figures (a) to (d) are cross-sectional views showing a third embodiment of the present invention in order of steps for manufacturing the LDD structure of Figure 5. 1...p-type silicon substrate, 2...gate oxide film, 3
...gate electrode, 4...n-type diffusion region, 5...
Polyimide film, 6.6A... Resin film, 7... Plasma nitride film (ion implantation mask), 7A... Silicon oxide film (ion implantation mask), 8... N type diffusion region (
(drain region), 9... n-type diffusion region (source region) 10... insulating film, 11... drain opening, 12
... Source opening, 13... Drain electrode, 14.
...Source electric bridge, 21...GaAs substrate, 22...
n layer, 23...Schottky gate electrode, 24...silicon oxide film (ion implantation mask), 25...resin film, 26...n'' region (drain region), 27...n''
area source area), 28... n-fil area, 29...
- Drain ohmic electrode, 30...source ohmic electrode. Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate, a step of forming a shallow junction region on the semiconductor substrate using the gate electrode as a mask, and coating selectively forming a source side portion of the gate electrode. a step of forming an insulating film on the entire surface and anisotropically etching it to leave the insulating film as an ion implantation mask only on the side surface on the drain side of the gate electrode; and a step of covering the gate electrode and the ion implantation. A method of manufacturing a semiconductor device, comprising the step of forming deep junction regions as a drain region and a source region in the semiconductor substrate using a mask. 2. A step of forming a gate electrode on the semiconductor substrate, a step of forming a shallow junction region on the semiconductor substrate using the gate electrode as a mask, and forming an insulating film on the entire surface and anisotropically etching it to form the gate electrode. A step of leaving the insulating film as an ion implantation mask on both sides of the electrode, a step of covering the ion implantation mask on the drain side with a selectively formed coating film, and etching away the ion implantation mask on the source side using this coating film as a mask. and a step of forming deep junction regions as a drain region and a source region in the semiconductor substrate using the gate electrode and the ion implantation mask as a mask after removing the coating film. Production method. 3. forming a gate electrode on a semi-insulating semiconductor substrate; forming an insulating film over the entire surface and anisotropically etching it to leave the insulating film as an ion implantation mask on both sides of the gate electrode; A step of covering the ion implantation mask on the drain side with a selectively formed coating film, a step of etching away the ion implantation mask on the source side using this coating film as a mask, and a step of removing the ion implantation mask on the source side after removing the coating film. forming a deep junction region as a drain region and a source region in the semiconductor substrate using an implantation mask as a mask; and forming a shallow junction region using the gate electrode as a mask after removing the ion implantation mask. A method for manufacturing a semiconductor device, characterized by: