JPH10247684A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a MISFET in characteristics by a method wherein a gate oxide film and a conductor film are formed on a semiconductor substrate, a silicon nitride film is formed on a part of the semiconductor substrate other than a groove forming part, and a part of the substrate other than the part masked with the silicon nitride film is anisotropically etched for the formation of a groove, and the surface of the substrate is polished. SOLUTION: A first conductive polycrystalline silicon film 3 is formed on a first insulating silicon dioxide film 2, the first conductive film 3 and the silicon dioxide film 2 are removed by anisotropic etching using a silicon nitride film 4 left on the conductor film as a mask, and a groove is cut in the silicon substrate for isolating elements from each other. Oxide such as silicon dioxide is filled in the groove, and the surface of the substrate is flattend by polishing, and ions are implanted into the substrate through the polysilicon film and the silicon dioxide film. Then, conductive material is deposited as a second conductive film to serve as a wiring layer. It is no region where a MISFET is hard to form.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit device in which elements formed on a semiconductor substrate are separated by using a groove, that is, a so-called shallow groove.
Further, the present invention relates to a semiconductor integrated circuit device manufactured by using the manufacturing method.

[0002]

2. Description of the Related Art PMISFETs (P-channel MISFETs (metal-insulator-semiconductor field-effect transistors)) and NMISFETs (N-channel type MISFETs)
In a conventional CMISFET (complementary MISFET) type semiconductor integrated circuit device configured of a plurality of PMISFETs and a plurality of NMISs formed on the same substrate,
It is necessary to separate the MISFETs as necessary. The reason is to prevent a parasitic element such as a capacitor or a transistor from being formed between the elements due to the interaction between the elements.

At present, the most commonly known element isolation method described above is LOCOS (Loca).
l Oxidation of Silicon) method. This method is shown based on the numbers shown in FIG. A thin silicon dioxide film 1 on a semiconductor substrate 101
03. After forming the silicon nitride film 104 thereon, the silicon nitride film other than the portion where an element such as a MISFET is formed is removed by etching. afterwards,
By oxidizing the surface of the semiconductor substrate, an oxide film (field oxide film) other than the portion where the silicon nitride film remains
102 is formed. After the field oxide film is formed, the silicon nitride film, the silicon dioxide film formed first is removed, and then oxidation for forming a gate oxide film is performed. Thereafter, a drain, a source diffusion layer is formed, and a gate electrode is formed. The element formation process such as formation is advanced.

In the above-mentioned LOCOS method, there is a problem that the bird's beak becomes unusable as a MISFET at the edge of the silicon nitride film serving as a mask when forming a field oxide film. A region indicated by an arrow portion 105 in FIG. 16 is a bird's beak portion. Even if the silicon nitride film 104 and the silicon dioxide film 103 formed on the semiconductor substrate are removed, it is difficult to form the MISFET because the bird's beak portion has the shape shown in the drawing. It is very difficult to suppress the bird's beak with the technology at the present stage, and this is a problem in promoting high integration of the semiconductor integrated circuit device.

[0005] As a method of avoiding the above-mentioned problem of high integration, a new method replacing the LOCOS method is being studied. One example of those methods discussed by the inventor is shown. A silicon dioxide film and a silicon nitride film are formed on a semiconductor substrate, and the silicon nitride film in the element isolation region is removed by photoetching while leaving the silicon nitride film in the element formation region. Using the silicon nitride on the element formation region as a mask,
Anisotropically etching the unmasked portion forms a trench-shaped groove, a so-called shallow groove. 2 inside the shallow groove
Element separation is performed by filling with an insulator such as silicon oxide, and the surface of the substrate is planarized by polishing the mask portion and the element separation portion by a CMP (chemical mechanical polishing) method or the like. Then 2
This is a method in which an element such as a MISFET is formed in a region other than the shallow groove element isolation region filled with silicon oxide. By using this method, a region such as a bird's beak where it is difficult to form a MISFET is not formed between the element isolation region and the element formation region, so that the degree of integration of the semiconductor integrated circuit device can be increased. .

[0006]

The present inventor has found that the following facts occur by using the above-mentioned element isolation method using a so-called shallow groove.

The method using the shallow groove has the following problems. After the surface is flattened by CMP,
Etching for removing the silicon dioxide film on the element forming region used as a mask, or oxidizing several tens of micrometers on the element forming region and removing them to expose a high quality silicon surface It is necessary to perform etching or the like for removing the sacrificial oxide film. Due to this oxide film etching, silicon dioxide on the surface of the shallow trench isolation portion is also etched away, and the surface of the shallow trench isolation portion may be slightly lower than the surface of the silicon substrate in the element formation region. In this state, the MIS is formed on the element formation region.
When the gate oxide film and the gate electrode of the FET are formed, the following problems occur. FIG. 17 shows a state in which a gate oxide film made of silicon dioxide is formed by thermal oxidation of a semiconductor substrate, and a gate electrode is formed above the gate oxide film by CVD or the like. In the figures shown here, the gate electrode is viewed from the source diffusion layer or the drain diffusion layer region. As shown in FIG. 17, a surface of a silicon substrate serving as a gate of the silicon substrate 201,
Silicon dioxide layer 2 filled in shallow grooves for element isolation
Step difference from the 02 surface occurs. At this time, if the silicon substrate is oxidized to form a gate oxide film, the silicon dioxide film will be formed to extend to the side surface of the silicon substrate. After that, when a gate electrode 204 is formed, as shown in the figure, a gate oxide film and a gate electrode having a shape covering a step formed between a gate forming region and a device isolation region in a device forming region. Is formed.
Therefore, when a voltage is applied to the gate electrode to make the MISFET conductive, concentration of an electric field occurs at the end of the gate region of the silicon substrate. As a result, even when the voltage applied to the gate is low, a channel region is formed at the end of the gate, and a transistor called Tr2 is formed in the region 205 in FIG. This transistor is turned on at a lower threshold value than the transistor Tr1 formed in an area other than the end which is the area 206 because of the electric field concentration at the end. That is, one MI
Two transistors, Tr1 and Tr2, are substantially formed in the SFET. FIG. 18 shows the characteristics of the gate voltage Vg and the drain current Ids at this time. As shown in the figure, Tr2 formed at the end portion is
Since the channel region is narrow in area, Tr2
A larger current cannot flow than the transistor Tr1 formed except for the transistor Tr1. However, the MISFET as one circuit element is one MISFET exhibiting the Ids characteristics of the combination of the Ids of Tr1 and the Ids of Tr2, and possibly includes the possibility of forming a MISFET having characteristics different from those originally expected. It will be.

Further, in addition to the above-mentioned problems, since the electric field is concentrated at the end of the silicon substrate where the gate is formed as described above, dielectric breakdown is apt to occur at the end, and the performance of the element is degraded. The problem of a high probability of being let go is no longer negligible.

An object of the present invention is to solve the above-mentioned problem.

A further object of the present invention is to provide a method of manufacturing a semiconductor device in which the thickness of a gate oxide film is reduced and the electric field concentration is reduced at the edge of a silicon substrate when shallow trench isolation is used, and a semiconductor using the method. Another object is to provide an integrated circuit device.

A further object of the present invention is to provide a method of manufacturing a semiconductor device in which the formation of a parasitic transistor at the edge of a silicon substrate, which has the possibility of deviating expected characteristics, and a semiconductor integrated circuit device using the method. Yes.

It is a further object of the present invention to provide a semiconductor device using shallow trench isolation and a semiconductor integrated circuit device using the method, which achieves improved transistor characteristics and reduced wiring steps without increasing the number of processes. In

[0013] Further objects of the present invention will become clear from the description and drawings of the present invention.

[0014]

A method of manufacturing a semiconductor integrated circuit device according to a typical embodiment of the present invention to achieve the above-described object will be described below. A first insulator film to be a gate oxide film later and a first conductor film to be a gate electrode later are formed on a semiconductor substrate, and a silicon nitride or the like as a first mask is formed in a portion other than a groove forming portion. Then, a groove is formed by performing anisotropic etching on portions other than the mask portion. The depth of the groove extends to the semiconductor substrate. Further, after the trench portion is filled with silicon oxide or the like as a first insulator, the surface of the silicon oxide is polished by CMP, and the upper surface thereof is substantially flush with the first conductive film serving as a gate electrode. A first insulator, which is an element isolation insulator, is formed.

According to such a manufacturing method, after the gate oxide film and the gate insulating film are formed, the trench is filled with the first insulator which is an element isolation insulator, so that the trench is filled at a position higher than the surface of the semiconductor substrate. An element isolation insulator having an upper surface can be obtained. Further, an element isolation insulator having an upper surface formed at a position higher than the surface of the semiconductor substrate can be easily obtained by CMP.

According to a typical embodiment of the present invention, a second conductive film serving as a wiring is formed on a gate electrode and an element isolation insulator on substantially the same plane, the upper surfaces of which are formed. . Since the second conductor film is formed on the gate electrode and the element isolation insulator which are substantially flush with each other, the second conductor film can be formed without considering a step.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described below with reference to the drawings.

The figure shown in FIG. 1 is a single semiconductor substrate 1, a so-called wafer, obtained by thinly slicing a highly purified silicon single crystal. A plurality of semiconductor devices can be manufactured on this semiconductor substrate. Note that the drawing shown here is a part of a cross-sectional view of the semiconductor substrate.

First, before forming a shallow trench isolation region which is a trench to be an element isolation region, a silicon dioxide film 2 as a first insulator film is formed on the surface of the semiconductor substrate 1. Since the first insulator film later becomes a gate oxide film of the MISFET,
It is desirable to form the film by thermal oxidation which can easily control the film thickness.

Thereafter, a polycrystalline silicon film 3 which is a first conductor film to be a gate electrode of a MISFET later is formed on the silicon dioxide film 2 which is a first insulator film by CVD (C).
chemical Vapar Deposition
And the like.

Next, a silicon nitride film 4 as a first mask is formed on the polycrystalline silicon film 3 as a first conductor film. This state is shown in FIG. Although not shown in the drawing, at the stage of forming the silicon dioxide film as the first insulator film, a P-type or N-type conductivity type well may already be formed in the semiconductor substrate. .

Next, a resist is applied to a uniform thickness on the silicon nitride film 4 as a first mask. As a coating method, a spin coating method is generally used. After the resist is uniformly applied on the silicon nitride film 4,
Set it on the photosensitive device with a photomask or reticle,
Perform accurate alignment. By exposing the resist through the mask or reticle for a required time, the pattern of the photomask or reticle is printed on the resist.
Thereafter, development is performed to remove the resist at a predetermined position on the semiconductor substrate, that is, a portion where a shallow groove for element isolation described later is formed, and a portion where a shallow groove for element isolation is not formed, for example, an element such as a MISFET is formed. The resist 5 is left in the portion to be formed. This state is shown in FIG.

Next, the silicon nitride film 4
Using the resist 5 remaining in the mask as a mask, the etching gas converted into high-frequency plasma reacts with the silicon nitride film 4 exposed in the portion where no resist remains. This method is called dry etching, and can process an anisotropic shape with little undercut on the lower portion of the resist. After leaving the silicon nitride film 4 in a predetermined region by etching, the resist 5 used as a mask is removed. This stage is shown in FIG.

Next, dry etching is performed again using the silicon nitride film 4 remaining on the first conductor film as a mask as a result of the above, so that the polysilicon film which is the first conductor film serving as the gate electrode is formed. Then, the silicon dioxide film as the first insulator film to be the gate oxide film is removed by anisotropic etching. Further, the silicon substrate is dug by anisotropic etching. Through the above steps, a groove for element isolation is formed. The depth of the groove depends on the depth of a source and a drain to be formed later, but it is desired that the depth be such that a parasitic element such as a transistor is not formed in the element isolation region. FIG. 5 shows this state. The groove formed here is generally called a shallow groove. Also, the grooves formed by the anisotropic etching have a slight angle with respect to the surface mask or the semiconductor substrate surface, or the first conductive film or the upper surface of the first insulator film, though there are some errors. Formed.

After the shallow groove is formed by the above steps,
The silicon nitride film 4 used as a dry etching mask is removed by hot phosphoric acid. Then, by depositing an oxide such as silicon dioxide 6 as the first insulator in the shallow groove, the inside of the shallow groove is filled with an insulator. In addition,
In this specification, when depositing an insulator in a groove, filling at least the inside of the groove with the insulator is referred to as filling.
This situation is shown in FIG. The embedding of silicon dioxide performed here is preferably performed by CVD or the like. FIG.
Although the surface of the buried silicon dioxide is flat, the silicon dioxide is deposited on the polysilicon which is the first conductive film, while the silicon dioxide is actually buried in the shallow groove. Therefore, when silicon dioxide is buried in the shallow groove, the effect of step coverage appears. Therefore, the shape is different from the shape shown in the figure, but it does not greatly affect the essence of the present invention. Is shown.

Next, the surface of the silicon dioxide 6 deposited in the shallow groove is subjected to CMP (Chemical Mech).
flattening by an analog polish. C
Polishing by MP uses the polysilicon film 3 serving as a gate electrode remaining in portions other than the shallow groove portion as a stopper film,
Proceed to that depth. Therefore, the gate electrode and the upper surface of the insulator filling the shallow groove are substantially flush with each other.

FIG. 7 shows a state in which the CMP is completed. When flattening by CMP, a slight level difference may occur depending on the material to be polished, altitude, etc.
Since this is an event that additionally occurs as a result of flattening, flattening including the occurrence of these steps will be referred to as flattening. And, they are expressed as substantially the same plane including the steps.

The buried silicon dioxide is removed by CMP.
According to FIG. 7 showing a state after polishing by
FIG. 8 shows a view of the semiconductor substrate in that state as viewed from above. Around the polysilicon 3 appearing on the surface of the element forming region, a silicon dioxide 6 filled in a shallow groove for element isolation is formed. The figure shown here is a part of a semiconductor substrate. The arrangement of the polysilicon 3 serving as the gate electrode that appears on the surface, that is, the arrangement of the element formation region is not limited to that shown in the present embodiment. FIGS. 1 to 7 are cross-sectional views when the semiconductor substrate is cut along the axis 11 shown in FIG. 9 is a cross-sectional view when the semiconductor substrate is cut along the twelve axes shown in FIG. 8 at the stage of FIG. 7 and FIG. As shown here, after removing the silicon nitride film as the first mask, the trench is not filled with the first insulator, and in order to reduce the number of steps, the trench is filled first and then the trench is filled later. It is also possible to remove silicon nitride.

Next, ion implantation is performed through a polysilicon film as a first conductor film and a silicon dioxide film as a first insulator film on the surface of the semiconductor substrate planarized by CMP. I do. The ion implantation is performed to form each of the following regions by controlling the acceleration voltage of the ions. First, a well region is formed by implanting the most accelerated P-type impurity 21 deeper than the surface. The arrow shown in FIG. 7 schematically shows the depth direction of the region into which the ions are implanted. The well is shown as a region 31 shown in FIGS. 7 and 9. Further, the ion 22 is implanted with a voltage weaker than the ion accelerating voltage at the time of forming the well, and the channel region is implanted. The ions 23 accelerated with a weaker voltage are implanted into the polysilicon film as the first conductor film. It is also possible to dope ions. Here, the wells are formed by ion implantation, but the wells may be formed at the initial stage as described above.

After ion implantation for forming wells, channels, and the like, a conductive material serving as a wiring layer is deposited on the semiconductor substrate shown in FIGS.
Is formed. In this embodiment, WSi2 is deposited, but the present invention is not limited to this. As described above, since the conductive layer serving as the wiring layer is formed on substantially the same plane, the wiring layer can be easily formed irrespective of step coverage or the like. In addition, the first gate electrode
And the second conductive film serving as a wiring layer are formed by directly laminating, so that it is not necessary to form an extra contact hole or the like.

Next, a resist is applied on the wiring material,
The resist is removed so as to leave a portion of the resist where the conductive film is left as a conductive film or wiring on the gate electrode. As a method, as described earlier in the present embodiment,
Exposure of the pattern using a photomask or reticle,
It can be realized by a method of removing extra resist. After forming the pattern of the resist 5 on the second conductor, the shaft 11
A cross-sectional view in the direction of FIG. 10 is shown in FIG.

Thereafter, using the remaining resist 5 as a mask, the unmasked portion of the second conductor film such as WSi2 which is to be a wiring, for example, WSi2, is removed by the above-described anisotropic etching. If the unmasked second conductive film is removed, the remaining portions other than the remaining portion of the resist except the shallow trench portion filled with silicon dioxide for element isolation are removed. The polysilicon film as the first conductor film is removed by anisotropic etching until it reaches the silicon dioxide film 2 as the first insulator film. This situation is shown in FIG. This figure shows axis 1
It is sectional drawing of two directions. When removing the first conductor film,
Since the resist and the second conductor film perform anisotropic etching using as a mask, the shape is generally shown in FIG.

Next, after the above-described situation in which the second conductor film and the first conductor film are left in predetermined regions, the resist used in the previous step is removed. Thereafter, N accelerated weaker than the P-type ions implanted when the well 31 was formed.
By implanting the type ions 24 at a position shallower than the P-type ions, the drain and source diffusion layers 32 can be formed. The figure at that time is shown below. 13 is a cross-sectional view when the semiconductor substrate is cut along the axis 12, FIG. 14 is a view seen from above, and FIG. 15 is a cross-sectional view when the semiconductor substrate is cut along the axis 11. In each of the figures, reference numeral 2 denotes a first insulator film in an element formation region, and reference numeral 6 denotes a first insulating film filled in a shallow groove.
Is a second conductive film which is a wiring connecting between gates. However, since 7 is formed on the gate electrode, it also serves as the gate electrode. In this embodiment, one active region, that is, one region surrounded by a shallow groove with an element isolation region
One MISFET transistor is formed. Of the two diffusion layers of each MISFET, one diffusion layer is shared by the two MISFETs.

Further, the first conductor film formed of polysilicon serves as a gate electrode of each MISFET. The second conductor film formed of WSi2 or the like formed on the conductor film serves as a wiring layer for connecting a part of the gate electrode or between the gates. Further, a region for forming a contact hole necessary for connection with another wiring is provided in the wiring layer serving as the second conductor film. This eliminates the need to form a contact hole on the gate electrode for connection to another wiring, and allows a contact hole to be formed above the silicon dioxide filled in the shallow groove for element isolation. , When forming a contact hole, without damaging the gate electrode.
There is no need to worry about upsetting the characteristics of the SFET. However, when the contact hole does not need to be formed on the first insulator and can be formed on the gate electrode, the element isolation region can be further narrowed, and the integration degree of the semiconductor device can be improved. It becomes possible. That is, the configuration shown above can be variously changed as needed, and is not limited to the configuration shown in the present embodiment.

According to the above-described embodiment, the area of the element isolation region can be reduced and the element formation region can be widened, so that the degree of integration of the semiconductor integrated circuit can be improved. Furthermore, since the surface of the first insulator in the element isolation region using the shallow groove is higher than the surface of the first insulator film serving as the gate insulating film, there is a problem in the element isolation by the conventional shallow groove isolation. The thinning of the oxide film and the concentration of the electric field at the end of the gate electrode do not occur. Therefore, the occurrence of a parasitic MISFET at the end of the gate electrode and the dielectric breakdown can be suppressed.
The characteristics of the ISFET can be improved. Further, in the present embodiment, as described above, the semiconductor surface can be made flatter than before.

In this embodiment, the groove is formed after the first conductor film is formed. However, the shallow groove is formed after the first insulator film is formed, and the groove is formed by the first insulator. After filling with
By forming WSi or polysilicon of the second conductor film over the first insulator film and the first insulator, a method in which steps and materials are reduced can be employed. In addition, since the gate end reinforcing oxidation can be performed before forming the metal part forming the wiring part, there is no problem such as abnormal oxidation or sublimation of the metal. Further, since the above-described steps can be performed without significantly increasing the steps of manufacturing a conventional semiconductor integrated circuit, it is possible to supply a semiconductor integrated circuit having higher added value than the conventional one.

In this embodiment, a single drain structure is used as the drain structure, but the present invention is not limited to this. In order to prevent the electric field from being concentrated between the diffusion layer and the gate due to miniaturization, a double drain structure or an LDD (Lightly
It is also possible to use a Doped Drain structure. Although a method for forming the LDD structure is not particularly limited, the low concentration diffusion layer 33 is formed by implanting ions 24 in the steps shown in FIGS. A film is formed on the surface of the semiconductor substrate. Thereafter, anisotropic etching is performed so that spacer portions 8 remain at both ends of the gate electrode in FIG. The LDD structure can be formed by forming the diffusion layer 32 by ion-implanting the spacer portion as a mask at a higher concentration than when 33 is formed. FIG. 13 showing the case where the LDD structure shown above is formed.
19 is shown in FIG. By using the LDD structure, the concentration of the electric field between the diffusion layer and the gate can be reduced.

Further, although not specifically described in the above embodiment, after the shallow groove is formed and before silicon dioxide is filled, ions are implanted into the shallow groove using the silicon nitride film as a mask, thereby forming a channel. It is also possible to form a stopper. By forming the channel stopper, it is possible to further suppress the formation of the parasitic MISFET.

[0039]

By using the shallow trench isolation method of the present invention, it is possible to reduce the isolation area and to provide a semiconductor integrated circuit device capable of improving the degree of integration more than before. . Further, by implementing the present invention, it becomes possible to stabilize the characteristics of the MISFET transistor formed in the semiconductor integrated circuit device. Further, by implementing the present invention, the semiconductor integrated circuit device described above can be provided without increasing the number of processes.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing an embodiment of the present invention.

FIG. 3 is a sectional view showing an embodiment of the present invention.

FIG. 4 is a sectional view showing one embodiment of the present invention.

FIG. 5 is a sectional view showing one embodiment of the present invention.

FIG. 6 is a sectional view showing one embodiment of the present invention.

FIG. 7 is a sectional view showing an embodiment of the present invention.

FIG. 8 is a plan view showing an embodiment of the present invention.

FIG. 9 is a sectional view in a second direction showing an embodiment of the present invention.

FIG. 10 is a sectional view showing one embodiment of the present invention.

FIG. 11 is a sectional view in a second direction showing an embodiment of the present invention.

FIG. 12 is a sectional view in a second direction showing one embodiment of the present invention.

FIG. 13 is a sectional view in a second direction showing an embodiment of the present invention.

FIG. 14 is a plan view showing an embodiment of the present invention.

FIG. 15 is a sectional view showing one embodiment of the present invention.

FIG. 16 is a cross-sectional view when a conventional element isolation method is used.

FIG. 17 is a cross-sectional view when a conventional element isolation method is used.

FIG. 18 shows a MISFE when a conventional element isolation method is used.
The figure which shows the Vg-Ids characteristic of TFET.

FIG. 19 is a sectional view in a second direction showing an embodiment of the present invention.

[Description of References] 1: a semiconductor substrate, 2: a silicon dioxide film as a first insulator film, 3: a polysilicon film as a first conductor film,
4: Silicon nitride film as first mask, 5:
Resist: 6: silicon dioxide as a first insulator filling a shallow groove, 7: WSi as a second conductor film, 8: silicon dioxide as a spacer, 11: first sectional axis , 1
2: second sectional axis, 21, 22, 23, 24: ions implanted into the substrate, 31: well region, 32: diffusion layer, 3
3: low concentration diffusion layer, 101: semiconductor substrate, 102: field oxide film, 103: 2 silicon oxide film, 104:
Silicon nitride film, 105: bird's beak portion,
201: semiconductor substrate, 202: silicon dioxide filled in a shallow groove, 203: silicon oxide film, 204: polysilicon film, 205: region where Tr2 is formed, 206:
Region where Tr1 is formed.

Claims (29)

[Claims] A step of preparing a first substrate on which a first conductor film is formed over a semiconductor substrate and a first insulator film over the semiconductor substrate; Forming a groove having a depth greater than the sum of the thickness of the first insulator film and the thickness of the first conductor film in the portion; and filling the groove with an insulator. Forming a MISFET on the semiconductor substrate other than the trench filled with the insulator. 2. The method according to claim 1, wherein the first insulator film is a gate insulating film of the MISFET, and the first conductor film is a MISFET.
2. The method according to claim 1, wherein the method serves as a gate electrode of an FET. 3. The method according to claim 1, wherein the step of forming the groove includes a step of forming a mask on the first conductive film and a step of dry-etching a region where the mask is not formed. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The semiconductor device according to claim 1, wherein said step of filling said insulator is a step of filling said insulator to at least a plane substantially flush with a surface of said semiconductor substrate. 2. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 5. The semiconductor integrated circuit according to claim 4, wherein said step of filling said insulator is a step of filling said insulator to a plane substantially flush with a surface of said first conductor film. Circuit manufacturing method. 6. The step of filling the insulator with the step of forming an insulator by depositing an insulator in the groove and on the first conductor film and polishing the insulator. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein: 7. The method for manufacturing a semiconductor integrated circuit device further comprises a step of processing the first conductive film to form a gate electrode, and a step of forming a gate electrode and covering the groove with an insulator and the gate electrode. Impurities into the semiconductor substrate region of the MISFET
7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: forming a diffusion layer. 8. A first insulator film is formed on a semiconductor substrate, a first conductor film is formed on the first insulator film, and a first conductor film is formed on a predetermined position of the first conductor film. Forming a first mask, forming a groove in the semiconductor substrate through the first insulator film and the first conductor film using the first mask as a mask, forming a first groove in the groove; After filling the insulator, a second conductor film is formed on the upper surface of the first conductor film and the upper surface of the first insulator, and a second mask is formed on the surface of the second conductor film. Forming a semiconductor integrated circuit device using the second mask as a mask, and removing predetermined portions of the second conductive film and the first conductive film. 9. When forming the groove, the thickness of the first conductor film is larger than the sum of the respective thicknesses of the first insulator film and the first conductor film with respect to the surface of the first conductor film. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the semiconductor device is digged deep. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
10. The semiconductor integrated circuit according to claim 8, further comprising a step of forming a well by implanting ions into the semiconductor substrate via the first insulator film. Device manufacturing method. 11. The method according to claim 1, wherein the step of removing a part of the first conductor film and the part of the second conductor film is a step of forming a gate electrode of a MISFET and a wiring between the gate electrodes. A method for manufacturing a semiconductor integrated circuit device according to claim 8. 12. The method for manufacturing a semiconductor integrated circuit device according to claim
Further, ions are implanted through the first insulator film to form a spacer on a side surface of the unremoved first conductor film, and a larger amount of ions than the ions is formed through the first insulator film. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said ions are implanted with strong energy. 13. The semiconductor device according to claim 8, wherein in the method of manufacturing a semiconductor integrated circuit, a channel stopper region is further formed by implanting ions into the groove. A method for manufacturing an integrated circuit device. 14. A step of forming a first film composed of one or more kinds of films on a semiconductor substrate; a step of forming a first mask at a predetermined position on the first film; A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a groove using the first mask as a mask; and a step of filling a first insulator in the groove. 15. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein said first film is a laminated film of an insulator film and a conductor film. 16. The semiconductor integrated circuit device according to claim 14, wherein said groove is formed by anisotropic etching and has a depth greater than a thickness of said first film. Production method. 17. The semiconductor according to claim 14, wherein an upper surface of said first insulator is substantially flush with an upper surface of said first film. A method for manufacturing an integrated circuit device. 18. The semiconductor device according to claim 14, wherein a second conductor film is formed on the upper surface of the first film and the upper surface of the first insulator. Of manufacturing a semiconductor integrated circuit device. 19. A method of manufacturing a semiconductor device having an insulator for isolating an element formed on a semiconductor substrate, wherein the element isolation insulator is formed on the semiconductor substrate and has a thickness not exceeding the upper surface of the element isolation insulator. Forming a first film and a second conductor film on the first film and the insulator; forming the first film and the second conductor film on the first film and the insulator; Removing a predetermined portion of the semiconductor integrated circuit device, wherein a side surface of the insulator is formed substantially at right angles to a surface of the semiconductor substrate. 20. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein said first film comprises an insulator film serving as a gate insulating film and a conductor film forming a gate electrode. 21. The semiconductor integrated circuit according to claim 19, wherein said insulator is formed in a groove formed in said semiconductor substrate by anisotropic etching. Device manufacturing method. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the lower surface of said second conductor film is formed as substantially the same plane. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein said first film is formed before said insulator. 24. A semiconductor device comprising: a plurality of MISFETs having a gate insulating film and a gate electrode formed on a semiconductor substrate; and an insulator for performing element isolation for isolating the plurality of MISFETs. The upper surface of the object is formed at least higher than the upper surface of the gate insulating film, and
A semiconductor integrated circuit device, wherein a side surface of the element isolation insulator is substantially perpendicular to an upper surface of the semiconductor substrate. 25. The semiconductor integrated circuit device according to claim 24, wherein said insulator for element isolation is an insulator filled in a groove formed by anisotropic etching. 26. A plurality of MISFETs having a gate insulating film and a gate electrode formed on a semiconductor substrate, an insulator for element isolation separating the plurality of MISFETs, the gate electrode and the element isolation insulation. A conductor film formed so as to be electrically connected to the gate electrode, on the object, the upper surface of the gate electrode and the upper surface of the element isolation insulator are formed so as to be substantially flush with each other; The semiconductor integrated circuit device, wherein the conductor film is formed substantially in parallel with an upper surface of the gate electrode and an upper surface of the insulator for element isolation. 27. The semiconductor integrated circuit device according to claim 26, wherein said conductor film is formed directly on said gate electrode and said insulator for element isolation. 28. An upper surface of the insulator for element isolation,
28. The semiconductor device according to claim 26, wherein at least the gate insulating film is formed higher than an upper surface of the gate insulating film, and a side surface of the insulator is substantially perpendicular to an upper surface of the semiconductor substrate. The described semiconductor integrated circuit device. 29. The semiconductor integrated circuit according to claim 26, wherein said insulator is formed in a groove of said semiconductor substrate formed by anisotropic etching. Circuit device.