JP2002280446A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the number of the contacting times of a chemical and element separation in wet etching. SOLUTION: The element separation 5 is formed at a silicon substrate 1, a resist 7 is formed in an area on the side of one element separation end 5b of the separation 5, and a silicon oxide film 3 in an area on the side of the other element separation end 5a is removed by wet etching to produce a semiconductor device 1. Thus, the one end 5b is not contact with the chemical and only the other end 5a is contact with the chemical, so the whole separation 5 is not contact with the chemical. By wet etching and removing the film 3 on the area on the side of the end 5b in a similar order, the number of the contacting times of the separation 5 and the chemical is minimized until a process for forming a gate electrode. Consequently, a recess is not made by corrosion of the ends 5a and 5b and the occurrence of the formation of a parasitic MOS transistor and a reverse narrow channel effect is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an insulator is removed by wet etching.

[0002]

2. Description of the Related Art Recently, MOSFETs (Metal-Oxide-Semi
2. Description of the Related Art Semiconductor devices typified by conductor field-effect transistors (Transistor) have been improved in performance and integration, and a plurality of elements are usually formed on the same semiconductor substrate in order to improve the degree of integration. . In this case, it is necessary to electrically separate the formed elements so that they do not adversely affect each other.

As a method of electrically isolating elements on a semiconductor substrate, a predetermined area on the semiconductor substrate is locally oxidized to be an insulator, thereby forming a device isolation.
l Oxidation of Silicon (LOCOS) method, shallow trench isolation (Sh) that forms shallow grooves in a semiconductor substrate, embeds insulators in the grooves, and forms element isolation
allow Trench Isolation (STI) method has been proposed.

In the case of the LOCOS method, since the semiconductor substrate is oxidized, a step is likely to be formed on the surface of the semiconductor substrate, which may affect a subsequent film forming process. On the other hand, the STI method
After forming a trench between the elements of the semiconductor substrate and embedding an insulator such as silicon dioxide in the trench, the surface is polished and smoothed, so that a fine separation width can be realized and the resolution capability between the elements is improved. Since a high and flat surface can be obtained, it is widely used as an element isolation technology of a semiconductor device.

[0005]

However, the conventional transistor manufacturing method using the STI method has the following problems.

First, an example of a conventional method for manufacturing a semiconductor device using the STI method will be described. 4 to 6 are views showing a method for manufacturing a semiconductor device having two types of gate oxide films of an input / output transistor and a logic transistor on a semiconductor substrate.

FIGS. 4A and 4B are diagrams showing a process of forming a transistor forming region of a semiconductor device. FIG. 4A shows a device isolation forming process, FIG. 4B shows a silicon oxide film removing process, and FIG. 4D is a cross-sectional view of the semiconductor device in each step of the manufacturing process of the logic transistor formation region, in which FIG.

The semiconductor device 100 includes a silicon substrate 101
A silicon oxide film 102 formed by oxidizing the surface of a silicon substrate 101;
A silicon nitride film 103 deposited by a method, an element isolation 104 made of silicon dioxide embedded in a trench formed by etching the silicon nitride film 103, the silicon oxide film 102, and the silicon substrate 101;
01, a through oxide film 105 made of silicon dioxide grown by thermally oxidizing the surface, and an input / output transistor formation region 10 formed by implanting ions into the silicon substrate 101.
6, a resist 107 for masking a region other than the input / output transistor formation region 106, and a logic transistor formation region 1 formed by implanting ions into the silicon substrate 101.
08 and a resist 109 for masking other than the region of the logic transistor formation region 108.

FIG. 4A is a view showing a state in which element isolation is formed by the STI method. First, the silicon substrate 101
The entire surface of the silicon oxide film 102 is oxidized by a thermal oxidation method.
Is formed, a silicon nitride film 103 is deposited on the entire surface of the silicon substrate 101 by a CVD method.

The silicon nitride film 103 serves as a hard mask when forming a trench for element isolation in the silicon substrate 101. Therefore, first, the silicon nitride film 1
A resist is applied on the substrate 03 to develop and expose the etching pattern.
03 is masked with a resist. Next, the silicon nitride film 103 is dry-etched to form an etching mask for forming a trench. Finally, using the silicon nitride film 103 as a mask, the silicon oxide film 102 and the silicon substrate 101 are dry-etched to form a trench in the silicon substrate 101.

After forming the trench, silicon dioxide is deposited on the entire surface of the silicon substrate 101 by a CVD method to fill the trench. Next, the deposited silicon dioxide is subjected to chemical mechanical polishing (CM) to the surface of the silicon nitride film 103.
P) Polish with an apparatus. At this time, the silicon nitride film 1
03 functions as a polishing stopper.

By the above-mentioned STI method, the silicon substrate 10
The element isolation 104 is formed in FIG. FIG. 4B is a view showing a state in which a silicon oxide film formed by thermal oxidation of the silicon substrate is removed by wet etching.

First, the silicon nitride film 103 is wet-etched with a chemical solution containing phosphoric acid, and then the silicon oxide film 102 is wet-etched with a chemical solution containing hydrofluoric acid. As a result, only the element isolation 104 remains on the silicon substrate 101.

FIG. 4C is a view showing a state in which an input / output transistor forming region is formed on a silicon substrate. FIG.
After the step (b), the surface of the silicon substrate 101 is oxidized to form a through oxide film 105. Next, a resist 107 for masking a region other than the input / output transistor formation region 106 is formed and masked, and ions are implanted into the silicon substrate 101 to form the input / output transistor formation region 106. Here, the through oxide film 105 is formed on the silicon substrate 1.
When ions are implanted into the silicon substrate 01, the contamination metal is prevented from entering the silicon substrate by knock-on.

FIG. 4D is a diagram showing a state in which a logic transistor forming region is formed on a silicon substrate. After forming the input / output transistor formation region 106, the logic transistor formation region 10 is formed in the same procedure as shown in FIG.
8 is manufactured. That is, this time, a resist 109 for masking a region other than the region of the logic transistor formation region 108 is formed and masked, and ions are implanted into the silicon substrate 101 to form the logic transistor formation region 108. Also in this case, the through oxide film 105 prevents the contamination metal from knocking into the silicon substrate when ions are implanted into the silicon substrate 101.

After forming the input / output transistor formation region 106 and the logic transistor formation region 108 by the above-described method, the process proceeds to a gate oxide film formation process. 5A and 5B are diagrams showing a gate oxide film forming step, wherein FIG. 5A shows a through oxide film removing step, FIG. 5B shows an oxide film forming step, and FIG. 5C shows removal of an oxide film formed in a logic transistor forming region. Step, (d)
FIG. 4 is a cross-sectional view of the semiconductor device in each step of a gate oxide film forming step. However, in FIG. 5, the same components as those shown in FIG. 4 are denoted by the same reference numerals.

The semiconductor device 100 includes a silicon substrate 101
Element isolation 104 formed on the silicon substrate 101;
I / O transistor formation region 106 and logic transistor formation region 108 formed by implanting ions into silicon substrate 101, oxide film 110 formed by thermally oxidizing the surface of silicon substrate 101, and I / O transistor formation region 106 The formed resist 111 and the gate oxide film 112 formed on the input / output transistor formation region 106
And a gate oxide film 113 formed on the logic transistor formation region 108.

FIG. 5A is a view showing a state in which a through oxide film formed on a silicon substrate has been removed. After the formation of the input / output transistor formation region 106 and the logic transistor formation region 108 shown in FIG. 4, the through oxide film 105 formed on the surface of the silicon substrate 101 is removed by wet etching using a chemical solution containing hydrofluoric acid. I do. During this wet etching, the entire surface of the silicon substrate 101 comes into contact with hydrofluoric acid, so that the element isolation 104 as well as the through oxide film 105 also come into contact with hydrofluoric acid in the chemical solution, and the element isolation end 104a and the element isolation end 104b become hydrofluoric acid. Eroded by Further, the erosion may progress to the element isolation 104 formed inside the silicon substrate 101, and a dent may occur.

FIG. 5B shows a state in which an oxide film is formed on the surface of the silicon substrate. After removing the through oxide film 105, the silicon substrate 1 is first formed to form a gate oxide film 112 on the input / output transistor formation region 106.
Oxide film 110 is grown by thermally oxidizing the entire surface of surface 01.

FIG. 5C is a view showing a state in which the oxide film formed on the logic transistor formation region has been removed. When a semiconductor device having two types of gate oxide films is manufactured, an oxide film 110 formed over the entire surface of the silicon substrate 101 is formed.
Of these, the oxide film 110 on the logic transistor formation region 108 is removed while leaving the oxide film 110 on the input / output transistor formation region 106, and a new oxide film is formed again on the entire surface of the silicon substrate 101. Can be

Therefore, first, the input / output transistor formation region 106 is masked with a resist 111, and wet etching is performed with a chemical solution containing hydrofluoric acid to remove only the oxide film 110 on the logic transistor formation region 108.
Here, too, as shown in FIG.
And the hydrofluoric acid in the chemical solution come into contact with each other, and a dent is generated in the element isolation 104, particularly, the element isolation end 104b, or an already generated dent is increased.

FIG. 5D shows a state in which a gate oxide film has been formed. After removing the oxide film 110 on the logic transistor formation region 108, the resist 111 is removed. After that, the surface of the silicon substrate 101 is thermally oxidized again,
Gate oxide film 1 on input / output transistor formation region 106
12, and a gate oxide film 113 on the logic transistor formation region 108 is formed. At this time, the oxide film 1 previously formed is formed on the input / output transistor formation region 106.
Since an oxide film is further formed on the gate electrode 10, the gate oxide film 11 formed on the logic transistor formation region 108 is formed.
A gate oxide film 112 thicker than 3 is formed. Thus, two types of gate oxide films can be formed.

Next, the step of forming the gate electrode will be described. FIG. 6 is a view showing a step of forming a gate electrode.
3A is a cross-sectional view of the semiconductor device in each of a polycrystalline silicon forming step, a resist pattern forming step, and a gate electrode forming step. However, in FIG. 6, the same components as those shown in FIGS. 4 and 5 are denoted by the same reference numerals.

The semiconductor device 100 includes a silicon substrate 101
Element isolation 104 formed on the silicon substrate 101;
An input / output transistor formation region 106 and a logic transistor formation region 108 formed by implanting ions into the silicon substrate 101;
A gate oxide film 112 formed on the logic transistor formation region 108;
Polycrystalline silicon 114 deposited on the entire surface by the VD method;
The gate electrode pattern resist 115 and the gate electrode 1
16a and 116b.

FIG. 6A shows a state in which polycrystalline silicon serving as a gate electrode has been formed. A gate oxide film 112 formed on the input / output transistor formation region 106;
After forming the gate oxide film 113 formed on the logic transistor formation region 108, the polysilicon 11
4 is deposited by a CVD method.

FIG. 6B shows a state in which a resist for etching the gate electrode pattern is formed. A resist 115 is applied on the deposited polycrystalline silicon 114 to develop and expose an etching pattern.
The polycrystalline silicon 114 other than the regions where a and b are formed is masked with a resist 115.

FIG. 6C is a diagram showing a state where the gate electrode is formed. Using the resist 115 formed in FIG. 6B as a mask, the polysilicon 114, the gate oxide film 112 formed on the input / output transistor formation region, and the gate oxide film 113 formed on the logic transistor formation region are etched. Gate electrode 116 of input / output transistor
a, The gate electrode 116b of the logic transistor is formed. Here, the gate oxide film 112 of the gate electrode 116a is formed.
Is formed to be thicker than the gate oxide film 113 of the gate electrode 116b.

By the above method, elements formed on the silicon substrate are electrically separated from each other, and a semiconductor device having two types of gate oxide films can be manufactured. However, in the method of manufacturing the semiconductor device 100,
After the formation of the element isolation 104 shown in FIG.
5B, the removal of the silicon oxide film 102 formed by thermal oxidation of the silicon substrate 101, the removal of the through oxide film 105 shown in FIG. 5A, and the removal of the logic transistor formation region 108 shown in FIG. For removing the oxide film 110,
Wet etching must be performed using a chemical solution containing hydrofluoric acid. As described above, when the wet etching is performed a plurality of times, the element isolation 104 comes into contact with hydrofluoric acid in the chemical solution, so that the element isolation end 104a of the element isolation 104 is formed.
In addition, the element isolation 104b may be eroded by hydrofluoric acid to cause a depression. Further, the erosion may progress to the element isolation 104 formed inside the silicon substrate 101 in some cases.

A DRAM (Dynamic Random Access)
Memory (Larg)
e Scale Integration), I / O transistors, logic transistors, D
Since the RAM cell transistor is formed on a silicon substrate, the number of steps increases, and the number of times that the element isolation comes into contact with a chemical solution containing hydrofluoric acid by wet etching increases. It is possible that the height will be higher or the dent already formed in the element isolation will be even larger.

As described above, when the element isolation formed on the silicon substrate is eroded by hydrofluoric acid and a depression is generated, when the polycrystalline silicon of the gate electrode is deposited, the depression, ie, the source region or the drain region of the silicon substrate is deposited. When polycrystalline silicon enters the gate electrode, a gate electrode is formed in contact with the source region or the drain region, and as a result, a parasitic MOS transistor having a low threshold voltage is formed in the generated depression.

Further, since the gate electrode is formed in contact with the source region or the drain region and the channel width is reduced, the contribution of the low threshold voltage portion formed in the recess cannot be neglected. An inverse narrow channel effect that lowers the threshold value of the entire device occurs. As a result, there is a problem that the performance of the transistor is deteriorated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method of manufacturing a semiconductor device that minimizes the number of times of contact between a chemical solution and element isolation in a wet etching process.

[0033]

According to the present invention, in a method of manufacturing a semiconductor device for removing a silicon oxide film by wet etching, a step of forming an element isolation on a silicon substrate, and oxidizing a surface of the silicon substrate. Forming a silicon oxide film, forming a resist in a region on one element isolation end side of the element isolation, and implanting ions into a region on the other element isolation end side of the element isolation, Removing the silicon oxide film formed on the region on the other element isolation end side by wet etching.

According to the above structure, the region on one element isolation end side of the element isolation is masked with the resist, and the silicon oxide film on the other element isolation end side area is wet-etched. At this time, only the other element separation end comes into contact with the chemical, and one element separation end does not come into contact with the chemical. Thus, the entire element separation does not come into contact with the chemical solution. Further, the silicon oxide film on the one element isolation end side region is removed by wet etching in the same procedure, so that only one element isolation end comes into contact with the chemical solution,
The other element separation end does not contact the chemical. Thereby, the number of times of contact between the element separation and the chemical solution is minimized, and the occurrence of the depression due to the element separation and the contact with the chemical solution is suppressed.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing a manufacturing process of the semiconductor device according to the present embodiment.

Here, a method for manufacturing a semiconductor device having two types of gate oxide films of an input / output transistor and a logic transistor on a semiconductor substrate will be described. 1A and 1B are diagrams showing a process of forming an input / output transistor formation region, wherein FIG. 1A shows an element isolation formation process, FIG. 1B shows an ion implantation process, FIG. 1C shows a wet etching process, and FIG. 1D shows a gate oxide film formation. It is sectional drawing of the semiconductor device in each process of a process.

FIG. 1A is a view showing a state in which element isolation is formed by the STI method. The semiconductor device 1 was formed on a silicon substrate 2, a silicon oxide film 3 formed by oxidizing the surface of the silicon substrate 2, a silicon nitride film 4 deposited on the silicon oxide film 3 by a CVD method, and the silicon substrate 2. And an element isolation 5 made of silicon dioxide embedded in the trench.

First, the entire surface of the silicon substrate 2 is oxidized by a thermal oxidation method to form a silicon oxide film 3 with a thickness of about 5 to 20 nm. Next, a silicon nitride film 4 is deposited on the entire surface of the silicon substrate 2 to a thickness of about 50 to 200 nm by a CVD method.

The silicon nitride film 4 is formed on the silicon substrate 2
It becomes a hard mask when forming a trench for forming the element isolation 5. Therefore, first, a resist is applied on the silicon nitride film 4 to develop an etching pattern.
Exposure is performed, and the silicon nitride film 4 other than the trench formation region is masked with a resist. Next, the silicon nitride film 4
Is dry-etched to form an etching mask for trench formation. Finally, using the silicon nitride film 4 as a mask, the silicon oxide film 3 and the silicon substrate 2 are dry etched to form a trench in the silicon substrate 2.

After the formation of the trench, silicon dioxide is deposited on the entire surface of the silicon substrate 2 to a thickness of about 200 to 800 nm by CVD to fill the trench. Next, the deposited silicon dioxide is transferred to the surface of the silicon nitride film 4 by C
It is polished by an MP device. At this time, the silicon nitride film 4
Functions as a polishing stopper.

The element isolation 5 is formed on the silicon substrate 2 by the above-mentioned STI method. FIG. 1B is a diagram showing a state in which an input / output transistor formation region is formed on a silicon substrate by an ion implantation method.

The semiconductor device 1 includes a silicon substrate 2 and a through oxide film 31 formed by oxidizing the surface of the silicon substrate 2.
A device isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and an N-type MOS transistor (NMOS) formation region of the input / output transistor formation region 6. P type M
And a resist 7 for masking the area other than the OS transistor (PMOS) formation region.

A silicon nitride film 4 is formed on the silicon substrate 2 on which the element isolation 5 has been formed by using a chemical solution containing phosphoric acid.
Is removed by wet etching to expose the surface of the silicon oxide film 3 shown in FIG. Thereafter, the silicon oxide film 3 is removed with hydrofluoric acid, and the through oxide film 31 is formed again by thermal oxidation. Next, in order to selectively implant ions into the NMOS formation region of the input / output transistor formation region 6, a resist 7 is formed in a region other than the NMOS formation region of the input / output transistor formation region 6, and boron (B), boron difluoride ( Boron is ion-implanted using BF ₂ ) or the like. At this time, the through oxide film 31 formed by thermal oxidation of the surface of the silicon substrate 2 functions as a sacrificial oxide film. By implanting ions through the through oxide film 31, it is possible to prevent the contaminated metal from entering the silicon substrate 2 by knock-on.

Similarly, in the case of forming the PMOS in the input / output transistor formation region 6, since ions are selectively implanted into the PMOS formation region in the input / output transistor formation region 6, the PMOS is formed in a region other than the PMOS formation region in the input / output transistor formation region 6. A resist mask is formed, and arsenic (As) or phosphorus (P) is ion-implanted. Also in this case, the through oxide film 31 functions as a sacrificial oxide film, and the knock-on effect is suppressed.

The input / output transistor formation region 6 is formed in the silicon substrate 2 by the above method. FIG. 1 (c)
FIG. 4 is a view showing a state in which a through oxide film formed by thermal oxidation of a silicon substrate is removed by wet etching.

The semiconductor device 1 includes a silicon substrate 2 and a through oxide film 31 formed by oxidizing the surface of the silicon substrate 2.
An element isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and an NM of the input / output transistor formation region 6.
And a resist 7 for masking other than the OS formation region or the PMOS formation region.

After the ion implantation in the step of FIG. 1B, the through oxide film 31 on the input / output transistor formation region 6 is removed by wet etching using a chemical solution containing hydrofluoric acid. At this time, the element separation end 5a contacts the hydrofluoric acid in the chemical solution, but the element separation end 5b does not contact the hydrofluoric acid. Since the upper surface of the element isolation 5 is protected by the resist 7 and is not exposed, there is no erosion by hydrofluoric acid.

By the above method, the through oxide film 31 on the input / output transistor formation region 6 is removed. Figure 1
(D) is a diagram showing a state in which a gate oxide film is formed on the input / output transistor formation region.

The semiconductor device 1 includes a silicon substrate 2 and a through oxide film 31 formed by oxidizing the surface of the silicon substrate 2.
And an element isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and a gate oxide film 8 formed on the input / output transistor formation region 6. Have been.

After the step of FIG. 1C, the resist 7 is removed, the surface of the silicon substrate 2 is thermally oxidized again to grow a silicon oxide film, and a gate oxide film 8 is formed on the input / output transistor formation region 6. Form. The thickness of the gate oxide film 8 is about 5 to 15 nm.

The input / output transistor formation region is manufactured by the above-described method, and then the process proceeds to a logic transistor formation region manufacturing process. Next, a method for manufacturing a logic transistor formation region is described.

FIGS. 2A and 2B are views showing a process of forming a logic transistor forming region, wherein FIG. 2A shows an ion implantation process, FIG. 2B shows a wet etching process, and FIG. 2C shows a semiconductor device in each process of a gate oxide film forming process. FIG. However, in FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

FIG. 2A is a view showing a state in which a logic transistor formation region is formed by an ion implantation method. The semiconductor device 1 is formed by implanting ions into the silicon substrate 2, a through oxide film 31 formed by oxidizing the surface of the silicon substrate 2, the element isolation 5 formed on the silicon substrate 2, and the silicon substrate 2. An input / output transistor formation region 6,
A gate oxide film 8 formed on the input / output transistor formation region 6, a logic transistor formation region 9 formed by implanting ions into the silicon substrate 2, and a region other than the NMOS formation region or the PMOS formation region of the logic transistor formation region 9 And a resist 10 to be masked.

After the gate oxide film 8 shown in FIG. 1D is formed, ions are selectively implanted into the NMOS formation region of the logic transistor formation region 9. Form 10. After the formation of the resist 10, boron is ion-implanted using B, BF ₂ or the like. At this time, the through oxide film 31 on the logic transistor formation region 9 functions as a through oxide film, and the knock-on effect is suppressed.

Further, the P of the logic transistor formation region 9
Similarly, in the case of MOS formation, in order to selectively implant ions into the PMOS formation region of the logic transistor formation region 9, a resist 10 is formed in a region other than the PMOS formation region of the logic transistor formation region 9, and arsenic or phosphorus is ion-implanted. Also in this case, the through oxide film 31 functions as a sacrificial oxide film, and the knock-on effect is suppressed.

The logic transistor formation region 9 is formed in the silicon substrate 2 by the above method. FIG. 2B is a view showing a state in which a silicon oxide film formed by thermal oxidation of the silicon substrate is removed by wet etching.

The semiconductor device 1 includes a silicon substrate 2, an element isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and an input / output transistor formation region 6. A gate oxide film 8 formed thereon, a logic transistor formation region 9 formed by implanting ions into the silicon substrate 2, and a resist 10 for masking the logic transistor formation region 9 other than the NMOS formation region or the PMOS formation region. It is configured.

After the ion implantation in the step of FIG. 2A, the through oxide film 31 on the logic transistor forming region 9 is removed by wet etching using a chemical solution containing hydrofluoric acid. At this time, the element separation end 5b comes into contact with hydrofluoric acid in the chemical solution. Since the upper surface of the element isolation 5 is protected by the resist 10 and is not exposed, there is no erosion by hydrofluoric acid.

By the above method, the through oxide film 31 on the logic transistor formation region 9 is removed. FIG. 2 (c)
FIG. 4 is a diagram showing a state where a gate oxide film is formed in a logic transistor formation region.

The semiconductor device 1 includes a silicon substrate 2, an element isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and an input / output transistor formation region 6. It comprises a gate oxide film 8 formed thereon, a logic transistor formation region 9 formed by implanting ions into the silicon substrate 2, and a gate oxide film 11 formed on the logic transistor formation region 9.

The through oxide film 31 on the logic transistor formation region 9 is removed by wet etching using a chemical solution containing hydrofluoric acid, the resist 10 is removed, and then the surface of the silicon substrate 2 is thermally oxidized. A silicon oxide film is grown, and a gate oxide film 11 is formed in the logic transistor formation region 9. At this time, since a silicon oxide film is further formed on the gate oxide film 8 previously formed on the input / output transistor formation region 6, the gate oxide film 8 on the input / output transistor formation region 6 The film thickness is
The thickness becomes larger than the thickness of the gate oxide film 11 formed on the logic transistor formation region 9. As a result, two types of gate oxide films can be formed on the silicon substrate 2.

The logic transistor formation region 9 is manufactured by the above method. Subsequent to the fabrication of the input / output transistor formation region 6 and the logic transistor formation region 9, formation of a gate electrode is performed.

FIGS. 3A and 3B are views showing a gate electrode forming step, wherein FIG. 3A shows a polycrystalline silicon forming step, FIG. 3B shows a resist pattern forming step, and FIG. 3C shows a semiconductor device in each step of the gate electrode forming step. FIG. However, FIG.
In the figure, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

The semiconductor device 1 includes a silicon substrate 2, an element isolation 5 formed on the silicon substrate 2, an input / output transistor formation region 6 formed by implanting ions into the silicon substrate 2, and a gate oxide of the input / output transistor. A film 8, a logic transistor formation region 9 formed by implanting ions into the silicon substrate 2, a gate oxide film 11 formed on the logic transistor formation region 9, polycrystalline silicon 12 deposited by CVD, Electrode pattern resist 1
3 and gate electrodes 14a and 14b.

FIG. 3A shows a state in which polycrystalline silicon serving as a gate electrode is formed. After forming the gate oxide film 8 in the input / output transistor formation region 6 and the gate oxide film 11 in the logic transistor formation region 9, polycrystalline silicon is deposited on the entire surface by CVD.

FIG. 3B is a view showing a state in which a resist has been formed. A resist 13 is applied on the deposited polycrystalline silicon 12 to develop and expose an etching pattern, and the polycrystalline silicon 12 other than the gate electrode formation region is masked by the resist 13.

FIG. 3C is a diagram showing a state in which the gate electrode has been formed. Using resist 13 as a mask, polycrystalline silicon 12, gate oxide film 8 formed on input / output transistor formation region 6, and logic transistor formation region 9
The gate oxide film 11 formed thereon is etched to form the gate electrode 14a of the input / output transistor and the gate electrode 14b of the logic transistor. Here, the gate electrode 1
The thickness of the gate oxide film 8 of 4a is formed larger than the thickness of the gate oxide film 11 of the gate electrode 14b.

According to the manufacturing method shown in FIGS. 1 to 3, the input / output transistor and the logic transistor are formed on the silicon substrate 2 by being electrically separated by the element isolation 5. Further, the input / output transistor and the logic transistor are formed of gate oxide films having different thicknesses.

As described above, according to the present manufacturing method, when the through oxide film 31 formed on the silicon substrate 2 by the thermal oxidation method is removed by wet etching in the process of manufacturing the semiconductor device, the upper surface of the element isolation 5 is removed. Be sure to resist 7 or 1
0, and the portion that comes into contact with hydrofluoric acid contained in the chemical solution during wet etching is minimized.
Thus, the entire element isolation does not come into contact with hydrofluoric acid, and erosion due to hydrofluoric acid is suppressed.

Furthermore, what should be noted in this manufacturing method is that FIG.
In the manufacturing process shown in FIG. 3 to FIG. 3, the element isolation end 5a contacts the hydrofluoric acid in the chemical solution only until the gate electrode is formed in the process shown in FIG. The point that 5b comes into contact with hydrofluoric acid in the chemical solution is only the step shown in FIG. 2 (b). That is, the element isolation end 5a
In addition, each of the element isolation ends 5b contacts the hydrofluoric acid only once, so that the number of times of contact between the element isolation and the hydrofluoric acid can be minimized, and erosion by hydrofluoric acid can be suppressed.

In the above description, in the step shown in FIG. 1B, the silicon oxide film 3 shown in FIG. 1A is removed with hydrofluoric acid, and the surface of the silicon substrate 2 is again thermally oxidized. Although the through oxide film 31 is formed, it is also possible to proceed to the next step without removing the silicon oxide film 3 with hydrofluoric acid. In this case, the silicon oxide film 3 can be used as a through oxide film.

That is, in the step shown in FIG. 1B, the silicon nitride film 4 is removed by wet etching using a chemical solution containing phosphoric acid on the silicon substrate 2 on which the element isolation 5 has been formed. The surface of oxide film 3 is exposed. Next, the N of the input / output transistor formation region 6
A resist 7 is formed in regions other than the MOS formation region, and boron ions are implanted. At this time, the silicon oxide film 3 functions as a sacrificial oxide film. P of input / output transistor formation region 6
Similarly, arsenic or phosphorus is ion-implanted for MOS formation. Also in this case, the silicon oxide film 3 functions as a sacrificial oxide film.

As described above, without removing the silicon oxide film 3 with hydrofluoric acid, the silicon oxide film 3 can have the function of a through oxide film. Thereby, the step of removing silicon oxide film 3 and the step of forming through oxide film 31 can be omitted.

In the above description, a method for manufacturing a semiconductor device having two types of gate oxide film thicknesses has been described.
As in the case of forming a RAM cell transistor,
The present invention can be applied to the manufacture of a semiconductor device having three types of gate oxide films.

In this case, after forming the input / output transistor according to the procedure shown in FIG. 1 described above, a DRAM cell transistor is formed according to the same procedure as that shown in FIG.
A logic transistor is formed by the procedure shown in FIG. Accordingly, even when three types of gate electrodes having different gate oxide film thicknesses are formed, element isolation between the elements and contact with hydrofluoric acid can be minimized.

That is, according to the above-described manufacturing method, even when the gate oxide films are formed to have different thicknesses, the element isolation is performed by the chemical solution at the time of wet etching regardless of the number of times of forming the gate oxide films. Can be minimized the number of times of contact with hydrofluoric acid.

[0077]

As described above, according to the present invention, a resist is formed in a region on one element isolation end side among element isolation ends of element isolation formed on a silicon substrate, and a resist is formed on the other element isolation end side. The silicon oxide film formed on the region is removed by wet etching. Thus, during wet etching, the other element separation end comes into contact with the chemical solution, but one element separation end does not come into contact with the chemical solution, and the entire element separation does not come into contact with the chemical solution.

Further, the silicon oxide film on one element isolation end side region is removed by wet etching in the same procedure, so that the gate oxide film can be separately formed before the step of forming the gate electrode. Regardless of the number of times, it is possible to minimize the number of times each element separation end contacts the chemical solution.

Therefore, it is possible to suppress the occurrence of the dent of the element isolation due to the contact between the element isolation and the chemical solution, thereby preventing the formation of the parasitic MOS transistor in the dent portion and the occurrence of the reverse narrow channel effect.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a process of forming an input / output transistor formation region, wherein FIG. 1A shows an element isolation formation process, FIG. 1B shows an ion implantation process, FIG. 1C shows a wet etching process, and FIG. It is sectional drawing of the semiconductor device in each process of a formation process.

FIGS. 2A and 2B are diagrams illustrating a manufacturing process of a logic transistor formation region, in which FIG. 2A illustrates an ion implantation process, FIG. 2B illustrates a wet etching process, and FIG. FIG.

FIG. 3 is a view showing a step of forming a gate electrode, and FIG.
4A is a cross-sectional view of the semiconductor device in each of a polycrystalline silicon forming step, a resist pattern forming step, and a gate electrode forming step.

4A and 4B are diagrams illustrating a process of forming a transistor formation region of a semiconductor device, wherein FIG. 4A illustrates an element isolation formation process, FIG. 4B illustrates a silicon oxide film removal process, and FIG. (D) is a cross-sectional view of the semiconductor device in each step of the manufacturing process of the logic transistor formation region.

FIG. 5 is a view showing a step of forming a gate oxide film;
(A) is a through oxide film removing step, (b) is an oxide film forming step, (c) is an oxide film removing step formed in a logic transistor formation region, and (d) is a gate oxide film forming step. 3 is a cross-sectional view of the semiconductor device in FIG.

FIG. 6 is a view showing a step of forming a gate electrode;
3B is a cross-sectional view of the semiconductor device in each step of a polycrystalline silicon forming step, (b) a resist pattern forming step, and (c) a gate electrode forming step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Silicon substrate, 3 ... Silicon oxide film, 4 ... Silicon nitride film, 5 ... Element isolation, 5
a, 5b: element isolation end; 6, input / output transistor formation region; 7, resist; 8, gate oxide film.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA37 AA44 AA77 AA79 AA84 BA01 CA07 CA17 CA24 DA02 DA24 5F043 AA32 BB22 GG05 5F048 AA04 AA07 AA09 AB01 AC01 AC03 BB05 BB16 BD04 BG01 BG14

Claims (6)

[Claims] 1. A method for manufacturing a semiconductor device for removing a silicon oxide film by wet etching, comprising: forming an element isolation on a silicon substrate; and oxidizing a surface of the silicon substrate to form a silicon oxide film. A step of forming a resist in a region on one element isolation end side of the element isolation; a step of injecting ions into a region on the other element isolation end side of the element isolation; A step of removing the silicon oxide film formed by wet etching by wet etching. 2. The method according to claim 1, further comprising a step of oxidizing the surface of the silicon substrate to form the silicon oxide film before the step of forming the element isolation on the silicon substrate. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the chemical solution for the wet etching contains hydrofluoric acid. 4. A semiconductor device manufactured by the method according to claim 1. 5. The semiconductor device according to claim 4, comprising a gate oxide film having two different thicknesses. 6. The semiconductor device according to claim 4, wherein the semiconductor device has three types of gate oxide films.