JP2003243649A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can restrain proximity effect and loading effect in forming a gate electrode and reduce parasitic capacitance. <P>SOLUTION: After a trench type element isolation region 2 surrounding an active region is formed in a semiconductor substrate 1, a gate insulating film 3 and a polycrystalline silicon film 4 are formed sequentially on the substrate 1. Resist 5 composed of resist 5a for forming a gate electrode and resist 5b for forming a dummy pattern is formed on the polycrystalline silicon film 4. The resist 5 is used as a mask and the silicon film 4 is etched, thereby forming a gate electrode 4a and a dummy pattern 4b. After the resist 5 is eliminated, the dummy pattern 4b is exposed by using a photolithography method, and resist 6 covering the gate electrode 4a is formed. After that, the resist 6 is used as a mask, and the dummy pattern 4b is etched and eliminated. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a MIS transistor (hereinafter, referred to as MISFE
(Referred to as "T") gate electrode formation method.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices, the miniaturization of elements has been advanced, and MISs formed in semiconductor devices have been formed.
The spacing between the gate electrodes of the FET is also miniaturized, and a structure in which a plurality of gate electrodes are arranged at a fine spacing is required. On the other hand, a single MISFET is
A structure in which the gate electrode is arranged in an isolated state apart from T is also required. Conventionally, such a semiconductor device MISFE
When the gate electrode of T is manufactured by the photolithography method and the dry etching method, the size of the gate electrode is different between the MISFET in which a plurality of gate electrodes are densely arranged and the MISFET in which an isolated gate electrode is arranged. There was a problem that there was variation in.

The first cause of this variation is the proximity effect due to the diffraction of light that occurs between adjacent gate patterns when the photoresist film is exposed by the photolithography method. That is, the gate length is formed small in the gate electrode in the region where the plurality of gate electrodes are densely arranged due to the proximity effect, and is increased in the isolated gate electrode region because the proximity effect is not remarkable. .

The second cause of this variation is an etching deposition caused by the reattachment of the etched gate material to the etched side surface when the gate material is etched. The loading effect depends on the etching deposition amount. There is. That is, since the amount of deposition is small in the region where the gate electrode is dense, the gate length becomes
Since the amount of deposition is large in the region where the gate electrode is isolated, the gate length becomes large.

As described above, since there is a difference in the gate lengths of the MISFETs in the region where the gate electrodes are dense and the region where the gate electrodes are isolated, there is a problem that the characteristics of the MISFET vary.

Therefore, conventionally, a method of using a dummy pattern has been proposed in order to suppress the proximity effect and the loading effect.

A conventional method of manufacturing a semiconductor device will be described below with reference to FIGS. 6 (a) to 6
FIG. 7C, FIG. 7A, and FIG. 7B are cross-sectional views showing a manufacturing process of a conventional n-type MISFET having an isolated gate electrode. FIG. 8 shows the n-type MIS in FIG.
It is a top view of FET.

First, in a step shown in FIG. 6A, a groove type element isolation region 102 surrounding an active region is formed on a p type semiconductor substrate 101. After that, a gate insulating film 103 is formed on the active region, and then a polycrystalline silicon film 104 is formed on the entire surface of the semiconductor substrate 101.

Next, in the step shown in FIG. 6B, a resist 105 is formed on the polycrystalline silicon film 104 by photolithography. At this time, a gate electrode forming resist 105a is formed above the active region, and at the same time, a dummy pattern forming resist 105b is formed above the groove type element isolation region 102. Next, the resist 10
5 is used as a mask to anisotropically etch the polycrystalline silicon film 104 to form the gate electrode 1 on the gate insulating film 103.
Simultaneously with forming 04a, the groove type element isolation region 102 is formed.
A dummy pattern 104b is formed on top.

Next, in the step shown in FIG. 6C, the resist 105 is removed. Next, using the gate electrode 104a and the groove-type element isolation region 102 as a mask, ion implantation of n-type impurities is performed to form an n-type extension region 106. At this time, in this embodiment, the gate insulating film 103 on the source / drain regions is removed by etching, but it may be left.

Next, in the step shown in FIG. 7A, after depositing an insulating film on the entire surface of the semiconductor substrate 101, the insulating film is etched by anisotropic etching to form the gate electrode 104a.
Side walls 107 are formed on the side surfaces of the. At this time, the sidewall 107 is simultaneously formed on the side surface of the dummy pattern 104b. Next, the gate electrode 104
a, side wall 107 and groove type element isolation region 102
Using the as a mask, ion implantation of n-type impurities is performed on the semiconductor substrate 101 to form high-concentration source / drain regions 108.

Next, in a step shown in FIG. 7B, an interlayer insulating film 109 is formed on the entire surface of the semiconductor substrate 101. After that, the interlayer insulating film 109 on the source / drain region 108 is formed.
After forming a contact hole reaching the source / drain region 108, a metal plug 110 made of a metal film of tungsten or the like is selectively formed in the contact hole.

As a result, an n-type MISFET having an isolated gate electrode 104a as shown in FIG. 8 can be formed.

According to the above method, the gate electrode 1
Simultaneously with forming 04a, the groove type element isolation region 102 is formed.
Since the dummy pattern 104b is formed thereover, the proximity effect in the photolithography process and the loading effect in the dry etching process can be suppressed, and the variation in the gate length of the gate electrode can be reduced.

[0015]

However, in the conventional method for manufacturing a semiconductor device as described above, since the dummy pattern 104b is left to the end, it is not possible to cope with the recent high density of the gate electrode. The effect of suppressing the proximity effect and the loading effect is low, and variations in the gate length of the gate electrode are becoming a problem.

That is, as shown in FIG. 8, in the conventional method, the distance X between the gate electrode 104a and the dummy pattern 104b is determined by the width of the metal plug 110 serving as a contact and the distance between the metal plug 110 and the gate electrode 104a. And the distance between the metal plug 110 and the dummy pattern 104b. Therefore, compared with the distance between the gate electrodes in the region where the plurality of gate electrodes are densely formed,
Since the distance between the isolated gate electrode and the dummy pattern becomes wide, the effect of suppressing the proximity effect and the loading effect becomes low, and the gate length of the gate electrode varies.

Further, since the dummy pattern 104b remains till the end, a parasitic capacitance is generated through the dummy pattern 104b, so that there is a problem that the parasitic capacitance is increased and delay characteristics are affected.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can suppress the proximity effect and the loading effect in forming the gate electrode and can reduce the parasitic capacitance.

[0019]

According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming a gate insulating film on a semiconductor substrate and a film of a gate electrode on the gate insulating film are formed. Step (b), a step (c) of forming a first resist composed of a gate electrode forming resist and a dummy pattern forming resist on the gate electrode film, and the gate electrode using the first resist as a mask. A step (d) of forming a gate electrode and a dummy pattern by etching the film for use, a step (e) of removing the first resist after the step (d), and a step (e) of The method includes a step (f) of forming a second resist covering the gate electrode, and a step (g) of selectively removing the dummy pattern using the second resist as a mask.

In the first method for manufacturing a semiconductor device, after the step (g), ion implantation is performed on the semiconductor substrate using the gate electrode as a mask to form an extension region (h) and step (h). After the step (i) of forming a sidewall on the side surface of the gate electrode, and after the step (i), ion implantation is performed on the semiconductor substrate using the gate electrode and the sidewall as a mask to form the source / drain regions. Forming step (j).

In the first semiconductor device manufacturing method, in the step (c), the gate electrode forming resist and the dummy pattern forming resist are formed at the minimum space interval of the design rule.

In the first method for manufacturing a semiconductor device, in the step (f), the second resist is formed so as to cover a part of the dummy pattern adjacent to the gate electrode,
In step (g), the dummy pattern is removed by isotropic etching using the second resist as a mask.

A second semiconductor device manufacturing method of the present invention is
A step (a) of forming a gate insulating film on at least a gate electrode forming region and forming an insulating film having a thickness larger than that of the gate insulating film on a source / drain forming region on an active region of a semiconductor substrate; After (a), a step (b) of forming a gate electrode film on the semiconductor substrate, and forming a first resist composed of a gate electrode forming resist and a dummy pattern forming resist on the gate electrode film. The step (c), the step (d) of forming the gate electrode and the dummy pattern by etching the gate electrode film by using the first resist as a mask, and the step (d) after the step (d). A step (e) of removing the resist, a step (f) of forming a second resist covering the gate electrode and the exposed gate insulating film after the step (e), and a second step
Step (g) of selectively removing the dummy pattern using the resist as a mask.

In the second method of manufacturing a semiconductor device, the dummy pattern adjacent to the gate electrode is formed on the insulating film.

In the second method of manufacturing a semiconductor device, the step (a) includes a step of forming an insulating film on the active region of the semiconductor substrate and a step of removing the gate electrode forming region in the insulating film to form an opening. The method includes a step of forming and a step of forming a gate insulating film on the active region exposed by the opening.

[0026]

(First Embodiment) First Embodiment of the Present Invention
A method for manufacturing the semiconductor device according to the embodiment will be described. 1 (a) to 1 (c) and 2 (a) to 2
(C) is an n-type MISF according to the first embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of the semiconductor device which has ET. 3A is a plan view of FIG. 1C, and FIG. 3B is a plan view of FIG. 2C.

First, in a step shown in FIG. 1A, a groove type element isolation region 2 surrounding an active region is formed on a p-type semiconductor substrate 1. After that, a gate insulating film 3 is formed on the active region, and then a polycrystalline silicon film 4 is formed on the entire surface of the semiconductor substrate 1. At this time, after forming the n-well region and the p-well region in the semiconductor substrate 1, the trench type element isolation region 2 is formed, and then predetermined channel implantation is performed, and then the gate insulating film 3 and the polycrystalline silicon film 4 are sequentially formed. You may form.

Next, in the step shown in FIG. 1B, a resist 5 is formed on the polycrystalline silicon film 4 by photolithography. At this time, at the same time as forming the gate electrode forming resist 5a above the active region, the dummy pattern forming resist 5b is formed above the active region and the groove type element isolation region 2 at the minimum space interval of the design rule. At this time, the dummy pattern forming resist 5b
It is preferable to form the pattern width of the same as that of the gate electrode forming resist 5a. Next, using the resist 5 as a mask, the polycrystalline silicon film 4 is anisotropically etched to form the gate electrode 4a on the gate insulating film 3 and, at the same time, on the active region and the trench type element isolation region 2. A dummy pattern 4b is formed on the.

Next, in the step shown in FIG. 1C, after removing the resist 5, a resist 6 is formed by photolithography to expose the dummy pattern 4b and cover the gate electrode 4a. Next, using the resist 6 as a mask, anisotropic etching or isotropic etching of the dummy pattern 4b is performed to leave only the gate electrode 4a on the gate insulating film 3. At this time, the resist 6 is formed so as to completely cover the gate electrode 4a, as shown in FIG.

Next, in the step shown in FIG. 2A, the resist 6 is removed. Then, using the gate electrode 4a and the groove-type element isolation region 2 as a mask, ion implantation of n-type impurities is performed to form an n-type extension region 7. At this time, in the present embodiment, the gate insulating film 3 on the source / drain regions is removed by etching, but it may be left.

Next, in the step shown in FIG. 2B, after depositing an insulating film on the entire surface of the semiconductor substrate 1, the insulating film is etched by anisotropic etching to form a sidewall on the side surface of the gate electrode 4a. 8 is formed. Next, the gate electrode 4
Using the a, the sidewall 8 and the trench type element isolation region 2 as a mask, ion implantation of n-type impurities is performed on the semiconductor substrate 1 to form a high concentration source / drain region 9.

Next, in a step shown in FIG. 2C, the interlayer insulating film 10 is formed on the entire surface of the semiconductor substrate 1. Then, the interlayer insulating film 10 on the source / drain region 9
After forming the contact hole reaching the drain region 9, a metal plug 11 made of a metal film such as tungsten is selectively formed in the contact hole. This allows
An n-type MISFET having an isolated gate electrode 4a as shown in FIG. 3B can be formed.

In the step shown in FIG. 2A, ion implantation was carried out by using the gate electrode 4a as a mask to form the n-type extension region 7. However, it is thin (about 5 nm to 30 nm) on the side surface of the gate electrode 4a. After forming the insulating sidewall, the n-type extension region 7 may be formed by performing ion implantation using the gate electrode 4a and the thin insulating sidewall as a mask. As a result, the amount of overlap between the gate electrode 4a and the n-type extension region 7 can be reduced.

According to the method of manufacturing the semiconductor device of the first embodiment, when the gate electrode 4a is formed as shown in FIG. 1B, first, in the photolithography process, the resist for forming the gate electrode is formed. Simultaneously with forming 5a, a dummy pattern forming resist 5b is formed above the active region and the groove type element isolation region 2 at the minimum space interval of the design rule. Thereby, the proximity effect in the photolithography process can be suppressed. After that, anisotropic dry etching of the polycrystalline silicon film 4 is performed using the gate electrode forming resist 5a and the dummy pattern forming resist 5b as a mask.
Since the space between a and the dummy pattern 4b is formed at the minimum space interval of the design rule, the loading effect in the etching process can be suppressed. As a result, the gate electrode in the region where the isolated gate electrode and the plurality of gate electrodes are densely arranged can be formed with the same finished dimension (gate length).

As described above, the gap between the gate electrode 4a and the dummy pattern 4b can be formed at the minimum space of the design rule, as shown in FIG. 1C, when the gate electrode 4a and the dummy pattern 4b are formed. This is to selectively remove only the dummy pattern 4b later.

Further, by removing the dummy pattern 4b, the parasitic capacitance is not generated through the dummy pattern 4b, so that the parasitic capacitance can be reduced.

(Second Embodiment) A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described. Figure 4
4A to 4C are cross-sectional views showing a manufacturing process of a semiconductor device having an n-type MISFET according to the second embodiment of the present invention.

In the step shown in FIG. 4A, an active region is formed on the p-type semiconductor substrate 1 by using the same method as the step shown in FIGS. 1A and 1B of the first embodiment. A trench type element isolation region 2 surrounding the is formed. Then, after forming the gate insulating film 3 on the active region, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 1. Then, a resist 5 is formed on the polycrystalline silicon film by photolithography. At this time, at the same time as forming the gate electrode forming resist 5a above the active region, the dummy pattern forming resist 5b is formed above the active region and the groove type element isolation region 2 at the minimum space interval of the design rule. Next, using the resist 5 as a mask, the polycrystalline silicon film is anisotropically etched to form the gate electrode 4a on the gate insulating film 3 and, at the same time, on the active region and the trench type element isolation region 2. The dummy pattern 4b is formed.

Next, in the step shown in FIG. 4B, after removing the resist 5, the gate electrode 4a and a part of the dummy pattern 4b formed adjacent to the gate electrode 4a are covered by photolithography. The resist 12 is formed. At this time, the resist 12 is formed so as to completely cover the gate electrode 4a and to cover at least one dummy pattern 4b of the two dummy patterns 4b formed adjacent to the gate electrode 4a. Just do it.

Next, in the step shown in FIG. 4C, the dummy pattern 4b is isotropically etched using the resist 12 as a mask to leave only the gate electrode 4a on the gate insulating film 3.

Then, after removing the resist 12, the first
2 (a) to 2 (c) of the embodiment, the n-type extension region 7, the sidewall 8, the high-concentration source / drain region 9, and
An n-type M having an interlayer insulating film 10 and a metal plug 11
Form ISFET.

According to the method of manufacturing the semiconductor device of the second embodiment, the same effect as that of the first embodiment can be obtained. Further, by forming the resist 12 so as to cover a part of the dummy pattern 4b in the step shown in FIG. 4B, a margin is created in the alignment margin of the resist 12 to the gate electrode 4a. Thereby, even if the distance between the gate electrode 4a and the dummy pattern 4b is the minimum space distance of the design rule, the resist 12 can be formed with a sufficient alignment margin. Furthermore, since the dummy pattern 4b is etched using isotropic etching, even if a part of the dummy pattern 4b is covered with the resist 12, it can be completely removed.
Moreover, since the selection ratio can be increased as compared with the anisotropic etching, the dummy pattern 4b can be formed without exposing the surface of the semiconductor substrate 1 even if the gate insulating film is thin.
Can be etched.

(Third Embodiment) A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described. Figure 5
5A to 5D are cross-sectional views showing a manufacturing process of a semiconductor device having an n-type MISFET according to the third embodiment of the present invention.

First, in the step shown in FIG. 5A, the groove type element isolation region 2 surrounding the active region is formed in the p type semiconductor substrate 1. Then, after forming an insulating film 13 having a thickness of 10 nm on the active region, the insulating film 13 in the gate electrode forming region is removed by photolithography and etching.
Exposing the surface of the active region. At this time, the opening width Y of the insulating film 13 is preferably set to a width that matches the width of the gate electrode to be formed and the alignment margin of the gate electrode.

Next, in the step shown in FIG. 5B, the insulating film 1
After the gate insulating film 14 having a thickness of 2 nm is formed on the active region exposed by the opening 3, the polycrystalline silicon film 4 is formed on the entire surface of the semiconductor substrate 1.

Next, in the step shown in FIG. 5C, a resist 5 is formed on the polycrystalline silicon film 4 by photolithography. At this time, the gate insulating film 1 in the active region
4, a gate electrode forming resist 5a is formed, and at the same time, a dummy pattern forming resist 5b is formed above the insulating film 13 in the active region and the groove type element isolation region 2 at the minimum space interval of the design rule. Next, using the resist 5 as a mask, the polycrystalline silicon film 4 is anisotropically etched to form the gate electrode 4a on the gate insulating film 14, and at the same time, on the insulating film 13 in the active region and the trench element. A dummy pattern 4b is formed on the isolation region 2.

Next, in the step shown in FIG. 5D, after removing the resist 5, the dummy pattern 4b is exposed and a resist 15 covering the gate electrode 4a is formed by photolithography. At this time, the width of the resist 15 is set so as to cover the exposed gate insulating film 14 in FIG.
It is formed wider than the opening width Y of the insulating film formed in the step. Next, using the resist 15 as a mask, anisotropic etching or isotropic etching of the dummy pattern 4b is performed to leave only the gate electrode 4a on the gate insulating film 14.

After that, the resist 15 is removed, and the exposed insulating film 13 and the exposed gate insulating film 14 are removed. Then, the same steps as those shown in FIGS. 2A to 2C of the first embodiment are performed. The n-type extension region 7, the side wall 8, and the high-concentration source / drain region 9
Then, an n-type MISFET having the interlayer insulating film 10 and the metal plug 11 is formed.

In the step shown in FIG. 5D, the second
4B of the above embodiment, the resist 15 is a dummy pattern 4 formed adjacent to the gate electrode 4a.
It may be formed so as to cover a part of b and the gate electrode 4a. At this time, it is preferable to remove the dummy pattern 4b using isotropic etching.

According to the method of manufacturing the semiconductor device of the third embodiment, the same effect as that of the first embodiment can be obtained. Further, the insulating film 13 in the active region in which the dummy pattern 4b is formed is formed thicker than the gate insulating film 14 in which the gate electrode 4a is formed, and is exposed in the step shown in FIG. Gate electrode 4a
The gate insulating film 14 is covered with the resist 15. Therefore, when the dummy pattern 4b is etched using the resist 15 as a mask, the insulating film 13 serves as an etching stopper, so that the gate insulating film 14 has a thickness of 1 to
Even if the thickness is as thin as about 5 nm, it can be removed without exposing the surface of the semiconductor substrate 1.

In the method of manufacturing the semiconductor device according to the third embodiment, two or more MIs having different gate insulating film thicknesses are used.
When applied to the manufacture of a semiconductor device having an SFET, it is more effective without increasing the number of process steps.

In the first to third embodiments described above,
Although the space between the gate electrode and the dummy pattern is formed with the minimum space interval of the design rule, it may be formed with a space interval of the minimum space interval or more. Further, the gate length of the gate electrode and the width of the dummy pattern do not necessarily have to be the same, and the pattern intervals do not have to be equal intervals.

Further, in the first to third embodiments, the n-type MISFET has been described, but the p-type MISFET can be similarly formed by reversing the conductivity types.

[0054]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after the gate electrode and the dummy pattern are simultaneously formed, the dummy pattern is selectively removed. Can be formed with the minimum space interval of the design rule. Therefore, since the proximity effect in the photolithography process and the loading effect in the etching process can be suppressed, a semiconductor device having a highly uniform gate electrode can be formed without depending on the density of the gate electrode.

Moreover, in order to remove the dummy pattern,
Since the parasitic capacitance is not generated through the dummy pattern, the parasitic capacitance can be reduced.

[Brief description of drawings]

1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3A is a plan view in FIG. 1C showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIG. 3B is a semiconductor according to the first embodiment of the present invention. FIG. 2C is a plan view showing the manufacturing process of the device.

4A to 4C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

5A to 5D are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

6A to 6C are cross-sectional views showing manufacturing steps of a conventional semiconductor device.

7A and 7B are cross-sectional views showing a manufacturing process of a conventional semiconductor device.

FIG. 8 is a diagram showing a conventional semiconductor device manufacturing process.
Plan view of

[Explanation of symbols]

1 Semiconductor substrate 2 Groove type element isolation region 3 Gate insulation film 4 Polycrystalline silicon film 4a Gate electrode 4b dummy pattern 5 resist 5a Resist for forming gate electrode 5b Dummy pattern forming resist 6 resist 7 Extension area 8 sidewalls 9 Source / drain regions 10 Interlayer insulation film 11 Metal plug 12 Resist 13 Insulating film 14 Gate insulating film 15 Resist

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/088 H01L 21/30 514A 29/417 F term (reference) 4M104 BB01 CC05 DD03 DD63 GG09 GG14 5F046 AA11 AA13 AA20 5F048 AC01 BA01 BB05 BB16 BC06 BF11 BG14 DA23 5F140 AA00 AA11 AB01 BF04 BG08 BG37 BG41 BG45 BH14 BH15 BJ01 BJ07 BJ27 BK02 BK13 CB01 CB04 CB08 CC03 CF00

Claims (7)

[Claims] 1. A step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a gate electrode film on the gate insulating film, and a gate electrode on the gate electrode film. A step (c) of forming a first resist consisting of a forming resist and a dummy pattern forming resist; and etching the gate electrode film by using the first resist as a mask to thereby form the gate electrode and the dummy. A step (d) of forming a pattern; a step (e) of removing the first resist after the step (d); and a step of forming a second resist covering the gate electrode after the step (e). A method of manufacturing a semiconductor device, comprising: a forming step (f); and a step (g) of selectively removing the dummy pattern using the second resist as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (g), ions are implanted into the semiconductor substrate by using the gate electrode as a mask to form an extension region (h). A step (i) of forming a sidewall on a side surface of the gate electrode after the step (h), and the semiconductor substrate using the gate electrode and the sidewall as a mask after the step (i). A step (j) of forming a source / drain region by implanting ions into the semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), a distance between the gate electrode forming resist and the dummy pattern forming resist is set to a minimum space distance of a design rule. A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (f), the second resist is a dummy pattern adjacent to the gate electrode. A method for manufacturing a semiconductor device, wherein the dummy pattern is removed by isotropic etching using the second resist as a mask in the step (g). 5. A gate insulating film is formed on at least a gate electrode formation region on an active region of a semiconductor substrate,
A step (a) of forming an insulating film having a thickness larger than that of the gate insulating film in the source / drain formation region, and a step of forming a gate electrode film on the semiconductor substrate after the step (a) ( b), a step (c) of forming a first resist composed of a gate electrode forming resist and a dummy pattern forming resist on the gate electrode film, and the gate using the first resist as a mask. A step (d) of forming a gate electrode and a dummy pattern by etching the electrode film; a step (e) of removing the first resist after the step (d); and a step (e). ), Forming a second resist covering the gate electrode and the exposed gate insulating film (f), and using the second resist as a mask to selectively form the dummy pattern. Method of manufacturing a semiconductor device characterized in that it comprises a step (g) that support. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the dummy pattern adjacent to the gate electrode is formed on the insulating film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the step (a) includes forming the insulating film on an active region of the semiconductor substrate, and forming a gate electrode in the insulating film. A method of manufacturing a semiconductor device, comprising: a step of removing a region to form an opening; and a step of forming the gate insulating film on the active region exposed by the opening.