KR100319634B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
- Publication number
- KR100319634B1 KR100319634B1 KR1019990054738A KR19990054738A KR100319634B1 KR 100319634 B1 KR100319634 B1 KR 100319634B1 KR 1019990054738 A KR1019990054738 A KR 1019990054738A KR 19990054738 A KR19990054738 A KR 19990054738A KR 100319634 B1 KR100319634 B1 KR 100319634B1
- Authority
- KR
- South Korea
- Prior art keywords
- gates
- substrate
- gate
- forming
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004886 process control Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000012072 active phase Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 장치 제조방법에 관한 것으로, 종래 반도체 장치 제조방법은 다른 소자형성영역에서 게이트로 사용하는 더미게이트라인이 특정 소자형성영역의 필드산화막을 지나게 되며, 공정관리의 이상으로 상기 더미게이트가 커패시터 형성영역인 셀 트랜지스터의 드레인측에 형성되는 경우, 커패시터 형성의 공정마진 확보가 용이하지 않은 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 게이트를 형성한 후, 그 게이트의 주변부에 필드산화막을 형성하여 각 소자영역에만 위치하는 게이트를 형성하고, 후속공정에서 독립적인 게이트를 상호 연결하는 금속배선을 형성하는 단계를 포함하여 더미게이트를 형성하지 않아 커패시터 형성의 공정 여유도를 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In the conventional method of manufacturing a semiconductor device, a dummy gate line used as a gate in another device formation region passes through a field oxide film in a specific device formation region, and the dummy gate is damaged due to abnormal process control. When formed on the drain side of the cell transistor, which is a capacitor formation region, there is a problem that it is not easy to secure the process margin of capacitor formation. In view of the above problems, the present invention forms a field oxide film on the periphery of the gate to form a gate located only in each device region, and forms a metal wiring interconnecting independent gates in a subsequent process. Including the step does not form a dummy gate has the effect of improving the process margin of the capacitor formation.
Description
본 발명은 반도체 장치 제조방법에 관한 것으로, 특히 각각의 액티브 상에만 위치하는 게이트를 형성한 후, 필드산화막을 형성하고, 이후의 금속배선공정에서 상기 게이트간의 접속을 행함으로써 반도체 장치의 공정 여유도를 향상시키는데 적당하도록 한 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, after forming gates located only on respective active phases, a field oxide film is formed, and subsequent gate connection is performed in a subsequent metal wiring process, thereby providing a process margin of the semiconductor device. The present invention relates to a method for manufacturing a semiconductor device that is suitable for improving the efficiency.
도1a 내지 도1d는 종래 반도체 장치의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 패드산화막(2)과 질화막(3)을 순차적으로 증착한 후, 사진식각공정을 통해 상기 질화막(3)과 패드산화막(2)의 일부를 제거하여 기판(1)의 상부일부를 노출시킨 다음, 그 노출된 기판(1)에 필드산화막(4)을 형성하는 단계(도1a)와; 상기 질화막(3)과 패드산화막(2)를 제거하여 기판(1)인 소자형성영역을 노출시킨 후, 그 필드산화막(4)에 더미게이트(D1,D2)를 형성함과 아울러 상기 소자형성영역에 셀트랜지스터의 게이트(G1,G2)를 형성한 다음, 그 셀트랜지스터의 게이트(G1,G2)의 측면 기판(1) 하부에 불순물 이온을 이온주입하여 저농도 소스 및 드레인(5)을 형성 하는 단계(도1b)와; 상기 게이트(G1,G2)와 더미게이트(D1,D2)의 측면에 절연막 측벽(6)을 형성한 후, 불순물 이온주입을 통해 고농도 소스 및 드레인(7)을 형성하는 단계(도1c)와; 상기 구조의 상부전면에 절연막(8)을 증착한 후, 상기 고농도 드레인에 각각 접하는 커패시터(9)를 형성하는 단계(도1d)를 포함하여 구성된다.1A to 1D are cross-sectional views of a manufacturing process of a conventional semiconductor device. As shown in FIG. 1, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the substrate 1, and then a photolithography process is performed. Removing portions of the nitride film 3 and the pad oxide film 2 to expose a portion of the upper surface of the substrate 1, and then forming a field oxide film 4 on the exposed substrate 1 (FIG. 1A); ; After removing the nitride film 3 and the pad oxide film 2 to expose the device forming region, which is the substrate 1, dummy gates D1 and D2 are formed in the field oxide film 4 and the device forming region is formed. Forming gates G1 and G2 of the cell transistors in the cell transistor, and then implanting impurity ions into the lower side substrate 1 of the gates G1 and G2 of the cell transistors to form a low concentration source and drain 5 (FIG. 1B); Forming an insulating film sidewall 6 on side surfaces of the gates G1 and G2 and the dummy gates D1 and D2, and then forming a high concentration source and drain 7 through impurity ion implantation (FIG. 1C); And depositing an insulating film 8 on the upper surface of the structure, and then forming a capacitor 9 in contact with the high concentration drain (FIG. 1D).
이하, 상기와 같이 구성된 종래 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a conventional semiconductor device configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 패드산화막(2)과 질화막(3)을 순차적으로 증착한다.First, as shown in FIG. 1A, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the substrate 1.
그 다음, 상기 질화막(3)의 상부전면에 포토레지스트(도면미도시)를 도포하고, 노광 및 현상하여 상기 질화막(3)의 일부를 노출시키는 패턴을 형성한다.Then, a photoresist (not shown) is applied to the upper surface of the nitride film 3, and exposed and developed to form a pattern for exposing a part of the nitride film 3.
그 다음, 상기 패턴이 형성된 포토레지스트를 식각마스크로 하는 식각공정으로 상기 노출된 질화막(3)과 그 하부의 패드산화막(2)을 제거하여 기판(1)의 상부일부를 노출시킨다.Thereafter, the exposed nitride film 3 and the pad oxide film 2 below are removed by an etching process using the photoresist on which the pattern is formed as an etching mask to expose a portion of the upper portion of the substrate 1.
그 다음, 상기 포토레지스트 패턴을 제거하고, 노출된 기판(1)을 산화시켜 필드산화막(4)을 형성한다.Next, the photoresist pattern is removed, and the exposed substrate 1 is oxidized to form a field oxide film 4.
그 다음, 도1b에 도시한 바와 같이 상기 잔존하는 질화막(3)과 그 하부의 패드산화막(2)을 제거하여 소자형성영역인 기판(1)의 상부를 노출시킨 후, 게이트사화막과 다결정실리콘을 순차적으로 증착하고, 그 다결정실리콘과 게이트산화막을 패터닝하여 셀트랜지스터의 게이트(G1,G2)를 기판(1) 상에 형성함과 아울러 상기 필드산화막(4)의 상부에 더미게이트(D1,D2)를 형성한다.Then, as shown in FIG. 1B, the remaining nitride film 3 and the pad oxide film 2 below it are removed to expose the upper portion of the substrate 1, which is an element formation region, and then the gate silicide film and the polycrystalline silicon Are sequentially deposited, and the polysilicon and the gate oxide film are patterned to form gates G1 and G2 of the cell transistor on the substrate 1 and the dummy gates D1 and D2 on the field oxide film 4. ).
도2는 종래 반도체 장치의 평면도로서, 이에 도시한 바와 같이 횡방향으로 위치하는 소자형성영역(ACTIVE1)의 사이 영역에 그 하단의 횡방향으로 위치하는 소자형성영역(ACTIVE2)의 측면 일부가 위치하게 되어 일렬의 소자형성영역(ACTIVE1)의 더미게이트는 그 하단 일렬의 소자형성영역(ACTIVE2)의 셀트랜지스터 게이트가 된다.FIG. 2 is a plan view of a conventional semiconductor device in which a portion of the side surface of the element formation region ACTIVE2 located in the transverse direction at the lower end thereof is located in an area between the element formation regions ACTIVE1 positioned in the lateral direction as shown in FIG. As a result, the dummy gates of one row of element formation regions ACTIVE1 become cell transistor gates of the bottom row of element formation regions ACTIVE2.
이와 같이 게이트의 형성시 그 게이트의 사이영역의 면적이 결정됨으로써, 이후의 공정에서 커패시터 형성시 그 공정 여유도의 확보가 용이하지 않게 된다.As such, when the gate is formed, the area of the interregion of the gate is determined, so that the process margin is not easily secured when the capacitor is formed in a subsequent process.
그 다음, 상기 게이트(G1,G2)의 측면 기판(1)에 저농도 불순물 이온을 주입하여 저농도 소스 및 드레인(5)을 형성한다.Next, low concentration impurity ions are implanted into the side substrate 1 of the gates G1 and G2 to form the low concentration source and drain 5.
그 다음, 도1c에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트(G1,G2)와 더미게이트(D1,D2)의 측면에 측벽(6)을 형성한다.Next, as shown in FIG. 1C, an insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form sidewalls 6 on the sides of the gates G1 and G2 and the dummy gates D1 and D2. Form.
그 다음, 상기 측벽(6)의 측면 기판(1) 하부에 불순물 이온을 이온주입하여 고농도 소스 및 드레인(7)을 형성한다.Next, impurity ions are implanted under the side substrate 1 of the sidewall 6 to form a high concentration source and drain 7.
그 다음, 도1d에 도시한 바와 같이 상기 구조의 상부전면에 절연막(8)을 증착하고, 그 절연막(8)에 콘택홀을 형성하여 상기 고농도 드레인을 노출시킨 다음, 상기 노출된 드레인에 접속되는 커패시터(9)를 형성하게 된다.Then, as shown in FIG. 1D, an insulating film 8 is deposited on the upper surface of the structure, a contact hole is formed in the insulating film 8 to expose the high concentration drain, and then connected to the exposed drain. The capacitor 9 is formed.
그러나, 상기와 같은 종래 반도체 장치 제조방법은 다른 소자형성영역에서 게이트로 사용하는 더미게이트라인이 특정 소자형성영역의 필드산화막을 지나게 되며, 공정관리의 이상으로 상기 더미게이트가 커패시터 형성영역인 셀 트랜지스터의 드레인측에 형성되는 경우, 커패시터 형성의 공정마진 확보가 용이하지 않은 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, a dummy gate line used as a gate in another device formation region passes through a field oxide layer of a specific device formation region, and the cell transistor is a capacitor formation region due to an abnormal process control. When formed on the drain side, there is a problem that it is not easy to secure the process margin of capacitor formation.
이와 같은 문제점을 감안한 본 발명은 특정 소자형성영역의 측면인 필드산화막의 상부에 게이트라인을 형성하지 않는 반도체 장치 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor device in which a gate line is not formed on the field oxide layer, which is a side surface of a specific device formation region.
도1a 내지 도1d는 종래 반도체 장치의 제조공정 수순단면도.1A to 1D are cross-sectional views of a manufacturing process of a conventional semiconductor device.
도2는 종래 반도체 장치의 평면도.2 is a plan view of a conventional semiconductor device.
도3a 내지 도3d는 본 발명 반도체 장치의 제조공정 수순단면도.3A to 3D are cross-sectional views of a manufacturing process of the semiconductor device of the present invention.
도4는 본 발명 반도체 장치의 평면도.4 is a plan view of the semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
30:기판 31:산화막30: substrate 31: oxide film
32:필드산화막 33:저농도 소스 및 드레인32: field oxide film 33: low concentration source and drain
34:측벽 35:고농도 소스 및 드레인34: side wall 35: high concentration source and drain
36,38:절연막 37:금속배선36,38: insulating film 37: metal wiring
39:커패시터39: Capacitor
상기와 같은 목적은 소자형성영역 각각에만 위치하는 게이트를 형성하고, 이후의 공정에서 금속배선을 이용하여 각 게이트를 연결함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is achieved by forming gates located only in each of the device formation regions, and connecting the gates by using metal wires in a subsequent process. The present invention will be described in detail with reference to the accompanying drawings. Same as
도3a 내지 도3d는 본 발명 반도체 장치 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(30)의 상부에 셀트랜지스터의 게이트(G1,G2)를 형성하고, 그 게이트(G1,G2)의 상부, 그 사이 및 측면 기판(1)의 일부영역상에 산화막(31) 패턴을 형성하는 단계(도3a)와; 상기 산화막(31) 패턴이 형성되지 않은 기판(1)을 산화시켜 필드산화막(32)을 형성하는 단계(도3b)와; 상기 산화막(31) 패턴을 제거하고, 노출되는 기판(30)에 불순물 이온을 이온주입하여 저농도 소스 및 드레인(33)을 형성하고, 그 게이트(G1,G2)의 측면에 측벽(34)을 형성한 후, 그 측벽(34)의 측면 기판(30)에 고농도 소스 및 드레인(35)을 형성하는 단계(도3c)와; 상기 구조의 상부전면에 절연막(36)을 증착하고, 상기 게이트(G1,G2)를 노출시키는 콘택을 형성한 다음, 다른 소자형성영역에 위치하는 게이트와 연결하는 금속배선(37)을 형성한 후, 다시 절연막(38)을 증착하고, 그 절연막(38)에 상기 고농도 드레인을 노출시키는 콘택홀을 형성한 다음, 그 콘택홀을 통해 상기 노출된 고농도 드레인에 접속되는 커패시터(39)를 형성하는 단계(도3d)를 포함하여 구성된다.3A to 3D are cross-sectional views of a semiconductor device manufacturing process according to an embodiment of the present invention. As shown therein, gates G1 and G2 of a cell transistor are formed on an upper portion of a substrate 30, and upper portions of the gates G1 and G2 are formed. Forming an oxide film 31 pattern therebetween and on a partial region of the side substrate 1 (FIG. 3A); Oxidizing the substrate (1) on which the oxide film (31) pattern is not formed to form a field oxide film (32); The oxide layer 31 is removed, and impurity ions are implanted into the exposed substrate 30 to form a low concentration source and drain 33, and sidewalls 34 are formed on side surfaces of the gates G1 and G2. Then forming a high concentration source and drain 35 in the side substrate 30 of the sidewall 34 (FIG. 3C); After depositing an insulating film 36 on the upper surface of the structure, forming a contact to expose the gate (G1, G2), and then forming a metal wiring 37 for connecting to the gate located in the other device formation region And depositing an insulating film 38 again, forming a contact hole exposing the high concentration drain in the insulating film 38, and then forming a capacitor 39 connected to the exposed high concentration drain through the contact hole. It consists of (FIG. 3D).
이하, 상기와 같이 구성된 본 발명 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, the semiconductor device manufacturing method of the present invention configured as described above will be described in more detail.
먼저, 도3a에 도시한 바와 같이 기판(30)의 상부에 게이트산화막과 다결정실리콘을 증착한 후, 사진식각공정을 통해 패터닝하여 게이트(G1,G2)를 형성한다.First, as illustrated in FIG. 3A, a gate oxide film and polysilicon are deposited on the substrate 30, and then patterned through a photolithography process to form gates G1 and G2.
그 다음, 상기 구조의 상부전면에 산화막(31)을 증착하고, 사진식각공정을 통해 패터닝하여 상기 게이트(G1,G2)의 상부와 그 게이트(G1,G2)의 사이 기판영역 및 측면부의 소정면적의 기판상에 위치하는 산화막(31) 패턴을 형성한다.Next, an oxide film 31 is deposited on the upper surface of the structure, and patterned by a photolithography process, and a predetermined area of the substrate region and the side portion between the gates G1 and G2 and the gates G1 and G2. An oxide film 31 pattern formed on a substrate is formed.
그 다음, 도3b에 도시한 바와 같이 상기 산화막(31) 패턴이 형성되지 않은 기판(1)을 산화시켜 필드산화막(32)을 형성한다.Subsequently, as shown in FIG. 3B, the field oxide film 32 is formed by oxidizing the substrate 1 on which the oxide film 31 pattern is not formed.
도4는 본 발명 반도체 장치의 평면도로서, 상기와 같이 필드산화막(32)을 형성하여 소자형성영역을 정의하면, 각 소자영역에만 위치하는 게이트(G1,G2)가 존재하도록 상기 게이트(G1,G2) 패턴을 형성한다.FIG. 4 is a plan view of the semiconductor device according to the present invention. When the field oxide film 32 is formed to define the device formation region as described above, the gates G1 and G2 exist so that the gates G1 and G2 are located only in each device region. ) Form a pattern.
그 다음, 도3c에 도시한 바와 같이 상기 산화막(31) 패턴을 제거하고, 노출되는 기판(30)에 불순물 이온을 이온주입하여 저농도 소스 및 드레인(33)을 형성한다.Next, as shown in FIG. 3C, the oxide layer 31 pattern is removed, and impurity ions are implanted into the exposed substrate 30 to form a low concentration source and drain 33.
그 다음, 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 게이트(G1,G2)의 측면에 측벽(34)을 형성한 후, 불순물 이온주입공정을 통해 상기 측벽(34)의 측면 기판(30)에 고농도 소스 및 드레인(35)을 형성한다.Next, an insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form sidewalls 34 on the side surfaces of the gates G1 and G2, and then the impurity ion implantation process A high concentration source and drain 35 is formed on the side substrate 30.
그 다음, 도3d에 도시한 바와 같이 상기 구조의 상부전면에 절연막(36)을 증착하고, 상기 게이트(G1,G2)를 노출시키는 콘택을 형성한 다음, 다른 소자형성영역에 위치하는 게이트와 연결하는 금속배선(37)을 형성한다.Next, as shown in FIG. 3D, an insulating film 36 is deposited on the upper surface of the structure, a contact is formed to expose the gates G1 and G2, and then connected to a gate located in another device formation region. The metal wiring 37 is formed.
이때, 금속배선(37)은 상기 도4에 도시한 바와 같이 소자형성영역의 측면측에 형성되도록 상기 게이트에 대하여 사선의 형태를 갖도록 형성한다.At this time, the metal wiring 37 is formed to have a shape of an oblique line with respect to the gate so as to be formed on the side of the device formation region as shown in FIG.
그 다음, 상기 구조의 상부전면에 절연막(38)을 증착하고, 사진식각공정을 통해 그 절연막(38)에 상기 고농도 드레인을 노출시키는 콘택홀을 형성한 다음, 그 콘택홀을 통해 상기 노출된 고농도 드레인에 접속되는 커패시터(39)를 형성한다.Then, an insulating film 38 is deposited on the upper surface of the structure, and a contact hole for exposing the high concentration drain is formed in the insulating film 38 through a photolithography process, and then the exposed high concentration through the contact hole. The capacitor 39 connected to the drain is formed.
상기한 바와 같이 본 발명은 각 소자형성영역에만 위치하는 게이트를 형성하고, 후속공정으로 금속배선을 이용하여 각 게이트를 연결함으로써, 더미게이트를 형성하지 않아 커패시터 형성의 공정 여유도를 향상시키는 효과가 있다.As described above, the present invention has the effect of improving the process margin of capacitor formation without forming dummy gates by forming gates located only in each device formation region and connecting each gate using a metal wiring in a subsequent process. have.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990054738A KR100319634B1 (en) | 1999-12-03 | 1999-12-03 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990054738A KR100319634B1 (en) | 1999-12-03 | 1999-12-03 | Manufacturing method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010054094A KR20010054094A (en) | 2001-07-02 |
| KR100319634B1 true KR100319634B1 (en) | 2002-01-05 |
Family
ID=19623409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990054738A KR100319634B1 (en) | 1999-12-03 | 1999-12-03 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100319634B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070213067A1 (en) | 2006-03-09 | 2007-09-13 | Patrick Li | Wireless communication handoffs within a macrocell |
-
1999
- 1999-12-03 KR KR1019990054738A patent/KR100319634B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010054094A (en) | 2001-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100610465B1 (en) | Method for fabricating semiconductor device | |
| JPH05166835A (en) | Self-aligning polysilicon contact | |
| KR20010056888A (en) | Manufacturing method for semiconductor memory | |
| KR100319634B1 (en) | Manufacturing method for semiconductor device | |
| KR100273296B1 (en) | Method for fabricating mos transistor | |
| KR100280539B1 (en) | Semiconductor device manufacturing method | |
| KR100525114B1 (en) | Manufacturing method of semiconductor device | |
| KR100273321B1 (en) | Semiconductor device manufacturing method | |
| KR100307541B1 (en) | Manufacturing method for mos transistor | |
| KR100271661B1 (en) | Method for fabricating semiconductor device | |
| KR100280527B1 (en) | MOS transistor manufacturing method | |
| KR100334963B1 (en) | Method of forming semiconductor device with contact plug | |
| KR100618676B1 (en) | Manufacturing method for semiconductor memory | |
| KR100273299B1 (en) | Method for fabricating mos transistor | |
| KR100215871B1 (en) | Method for fabricating semiconductor device | |
| KR100295664B1 (en) | Manufacturing method for semiconductor memory | |
| KR100280526B1 (en) | Semiconductor Memory Manufacturing Method | |
| KR100313505B1 (en) | Manufacturing method for semiconductor memory | |
| KR100313786B1 (en) | Manufacturing method for plug in semiconductor memory | |
| KR100280522B1 (en) | Semiconductor Memory Manufacturing Method | |
| KR100280511B1 (en) | Semiconductor memory manufacturing method | |
| KR100567043B1 (en) | Plug formation method of semiconductor device | |
| KR20010056069A (en) | Manufacturing method for semiconductor memory | |
| KR19990047003A (en) | Manufacturing method of plug of semiconductor memory | |
| KR19990080191A (en) | MOS transistor manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |