JPH02241081A - Manufacture of printed board - Google Patents
Manufacture of printed boardInfo
- Publication number
- JPH02241081A JPH02241081A JP6478089A JP6478089A JPH02241081A JP H02241081 A JPH02241081 A JP H02241081A JP 6478089 A JP6478089 A JP 6478089A JP 6478089 A JP6478089 A JP 6478089A JP H02241081 A JPH02241081 A JP H02241081A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- tin
- layers
- resist
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 57
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 23
- 239000004020 conductor Substances 0.000 abstract description 11
- 230000005496 eutectics Effects 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- TXUICONDJPYNPY-UHFFFAOYSA-N (1,10,13-trimethyl-3-oxo-4,5,6,7,8,9,11,12,14,15,16,17-dodecahydrocyclopenta[a]phenanthren-17-yl) heptanoate Chemical compound C1CC2CC(=O)C=C(C)C2(C)C2C1C1CCC(OC(=O)CCCCCC)C1(C)CC2 TXUICONDJPYNPY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021626 Tin(II) chloride Inorganic materials 0.000 abstract description 2
- 235000011150 stannous chloride Nutrition 0.000 abstract description 2
- 239000001119 stannous chloride Substances 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000001235 sensitizing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
ヒユージング仕様のプリント基板の製造方法に関し、
ソルダーレジストの現像によって組成比が共晶比からず
れた半田層を正常な共晶半田にする方法を提供すること
を目的とし、
フォトソルダーレジストパターンを形成した基板面に露
出する半田層上に錫めっき層を形成し、その後に半田を
再溶融する構成とした。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a printed circuit board with fuser specifications, and the present invention provides a method for converting a solder layer whose composition ratio deviates from the eutectic ratio by developing a solder resist into a normal eutectic solder. For this purpose, a tin plating layer was formed on the solder layer exposed on the substrate surface on which a photo solder resist pattern was formed, and then the solder was remelted.
この発明はプリント基板の製造方法に関し、特にヒユー
ジング仕様のプリント基板の製造方法に関する。The present invention relates to a method for manufacturing a printed circuit board, and particularly to a method for manufacturing a printed circuit board with fusing specifications.
プリント基板は実装部品の半田付は性、導体パターンの
露出した胴部分の耐食性を向上させるために半田処理が
なされる。Printed circuit boards are soldered to improve the solderability of mounted components and the corrosion resistance of exposed conductor patterns.
半田処理にはヒユージング仕様基板に対するものと、ソ
ルダーコート仕様基板に対するものがあり、それぞれ少
し工程を異にしている。There are two types of soldering process: one for fusing specification boards and one for solder coat specification boards, and the processes for each are slightly different.
第2図はこの発明が適用されるヒユージング仕様基板の
プリント基板の製造工程を示したものである。FIG. 2 shows the manufacturing process of a printed circuit board of a fusing specification board to which the present invention is applied.
スルーホール等の穴明加工後、パネルメッキが施され、
その後、表面層に対してドライフィルム等を用いて表面
導体パターン予定域以外にメンキレジスト層4が形成さ
れるいわゆるイメージ処理がなされる(ステップ511
)。After drilling holes such as through holes, panel plating is applied,
Thereafter, so-called image processing is performed on the surface layer using a dry film or the like to form a menki resist layer 4 in areas other than the planned surface conductor pattern area (step 511).
).
その後、電解めっきによって導体パターン部5゛が形成
され(ステップ512)、下記のエツチング処理のエツ
チングレジストとして該導体パターン部5゛に対して電
解半田めっきによって半田層6が形成される(ステップ
513)。この後、上記ドライフィルム等のメツキレジ
スト4が剥離されて(ステップ514)、上記表面導体
パターン部5゛以外の下層の下層導体2がエツチングさ
れて表面導体パターン5が形成される(ステップ515
)。Thereafter, a conductor pattern portion 5'' is formed by electrolytic plating (step 512), and a solder layer 6 is formed by electrolytic solder plating on the conductor pattern portion 5'' as an etching resist for the etching process described below (step 513). . Thereafter, the plating resist 4 such as the dry film is peeled off (step 514), and the lower layer conductor 2 other than the surface conductor pattern portion 5'' is etched to form the surface conductor pattern 5 (step 515).
).
上記半田層6は電解半田めっきで形成されているために
、多孔質であること及び上記エツチング処理によって表
面が粗面化され、後の工程でのソルダーレジストの付着
性が悪いこと、更に、表面導体パターン5の側面にも半
田を被覆する必要があること等の理由で、この後、該半
田層6がヒユージングされている(ステップ516)。Since the solder layer 6 is formed by electrolytic solder plating, it is porous and the surface is roughened by the etching process, resulting in poor adhesion of solder resist in subsequent steps. Thereafter, the solder layer 6 is fused (step 516) because it is necessary to coat the side surfaces of the conductive pattern 5 with solder as well.
このように半田がコーティングされたプリント基板1を
そのまま部品実装工程に適用すると、半田が融けて各配
線間が短絡するおそれがあるので、部品実装部以外の部
分にソルダーレジストパターン8がコーティングされ(
ステップ517)、その後に外形処理がなされる。If the printed circuit board 1 coated with solder is applied as it is to the component mounting process, there is a risk that the solder will melt and short circuit between each wiring.
Step 517), followed by contour processing.
上記のヒユージング仕様基板の製造工程において、ソル
ダーレジストパターン8をコーティングする際、近年該
ソルダーレジストパターン8の精密性が問題とされるよ
うになり、旧来の印刷による方法に代わってドライフィ
ルムや液状の感光剤が使用されるようになっている。と
ころが、このドライフィルム等がアルカリ現像液で現像
するタイプの場合、半田中の錫が該現像液に溶は込んで
半田層6の表面が鉛リッチとなる。In the manufacturing process of the above-mentioned fusing specification board, when coating the solder resist pattern 8, the accuracy of the solder resist pattern 8 has become a problem in recent years, and dry film or liquid coating has been used instead of the traditional printing method. Photosensitizers are now being used. However, if this dry film or the like is of a type that is developed with an alkaline developer, tin in the solder dissolves into the developer and the surface of the solder layer 6 becomes lead-rich.
従って、この半田層6は共晶半田ではなくなり、融点(
共晶半田で183℃)の上昇を来たし、部品実装時の温
度管理に不都合を来すという難点がある。Therefore, this solder layer 6 is no longer a eutectic solder, and its melting point (
The temperature rises (183°C) with eutectic solder, which poses a problem in that temperature control during component mounting is inconvenient.
本発明は上記従来の事情に鑑みて提案されたものであっ
て、ヒユージング仕様のプリント基板製造工程中、ソル
ダーレジストの現像によって組成比が共晶比からずれた
半田層を正常な共晶半田にする方法を提供することを目
的とするものである。The present invention has been proposed in view of the above-mentioned conventional circumstances. During the manufacturing process of printed circuit boards with fusing specifications, a solder layer whose composition ratio deviates from the eutectic ratio due to solder resist development is converted into normal eutectic solder. The purpose is to provide a method to do so.
この発明は上記目的を達成するために例えば第1図に示
すように、ヒユージング仕様のプリント基板において、
アルカリ現像液で現像される形式のフォトソルダーレジ
スト8を形成後の基板面に露出する半田層6上に錫めっ
き層7を形成し、その後に半田を再溶融するようにした
ものである。In order to achieve the above object, the present invention includes, for example, a printed circuit board with fusing specifications, as shown in FIG.
A tin plating layer 7 is formed on the solder layer 6 exposed on the substrate surface after a photo solder resist 8 developed with an alkaline developer is formed, and the solder is then remelted.
上記方法によって新たにめっきされた錫層7と鉛リッチ
の下層部の半田層4とが溶融によって混ざり合って共晶
半田を形成することになる。By the above method, the newly plated tin layer 7 and the lead-rich lower solder layer 4 are mixed by melting to form eutectic solder.
第1図はこの発明の1実施例を示す工程図である。エツ
チングレジストとしての半田層6を形成して導体パター
ン5が形成され、その後、この導体パターン5の表面の
半田層6がヒユージングされ(ステップS1)、この後
、ドライフィルムが貼り付けられたり、あるいは液状の
感光剤が塗付されてソルダーレジストパターン8が現像
される(ステップS2)工程迄は従来と同様である。こ
のとき上記のようにアルカリ現像液が用いられるので、
半田層6の錫が現像液に溶は出して表面は鉛リッチにな
る。このような鉛リッチの半田層6に対して塩化第1錫
を主成分とする溶液を用いて無電解錫めっきが施され、
錫層7が形成される(ステップS3)。この無電解錫め
っきは上記現像工程(ステップS2)でアルカリ現像液
中に溶は出した錫を補う意味で0.5〜1μm程度の厚
みとなる。この後、半田を再溶融する(ステップS4)
と共晶半田が得られることになる。FIG. 1 is a process diagram showing one embodiment of the present invention. A conductor pattern 5 is formed by forming a solder layer 6 as an etching resist, and then the solder layer 6 on the surface of the conductor pattern 5 is fused (step S1), and then a dry film is pasted or The process up to the step of applying the liquid photosensitive agent and developing the solder resist pattern 8 (step S2) is the same as the conventional process. At this time, as mentioned above, an alkaline developer is used, so
The tin in the solder layer 6 is dissolved into the developer, and the surface becomes lead-rich. Electroless tin plating is applied to such a lead-rich solder layer 6 using a solution containing stannous chloride as a main component.
A tin layer 7 is formed (step S3). This electroless tin plating has a thickness of about 0.5 to 1 μm in order to compensate for the tin dissolved into the alkaline developer during the development step (step S2). After this, the solder is remelted (step S4)
Thus, eutectic solder is obtained.
この後、外形処理が施されることは従来と同じである。After this, the external shape processing is performed as in the conventional case.
以上説明したようにこの発明は、プリント基板の半田を
正常な共晶半田にすることが可能であり、部品実装時に
おいて半田が溶けにくいという問題が解決され、温度管
理を容易にする。As described above, the present invention makes it possible to use normal eutectic solder for the solder on a printed circuit board, solving the problem of the solder being difficult to melt during component mounting, and facilitating temperature control.
第1図は本発明の手順を示す工程図、第2図は従来のソ
ルダーレジスト仕様の製造手順を示す工程図である。
図中、
6・・・半田層、 7・・・錫めっき層、8・
・・フォトソルダーレジストパターン。
エツチング
本発明の一実施例工程図
111図FIG. 1 is a process diagram showing the procedure of the present invention, and FIG. 2 is a process diagram showing the manufacturing procedure of a conventional solder resist specification. In the figure, 6...Solder layer, 7...Tin plating layer, 8...
...Photo solder resist pattern. Etching process diagram of an embodiment of the present invention 111
Claims (1)
ストパターン(8)を形成した基板面に露出する半田層
(6)上に錫めっき層(7)を形成し、その後に半田を
再溶融することを特徴とするプリント基板の製造方法。A tin plating layer (7) is formed on the solder layer (6) exposed on the substrate surface on which a photo solder resist pattern (8) developed with an alkaline developer is formed, and then the solder is remelted. Features of printed circuit board manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6478089A JPH02241081A (en) | 1989-03-15 | 1989-03-15 | Manufacture of printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6478089A JPH02241081A (en) | 1989-03-15 | 1989-03-15 | Manufacture of printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02241081A true JPH02241081A (en) | 1990-09-25 |
Family
ID=13268072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6478089A Pending JPH02241081A (en) | 1989-03-15 | 1989-03-15 | Manufacture of printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02241081A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101005501B1 (en) * | 2008-06-16 | 2011-01-04 | (주)국민전자 | Method of making High Confidential PCB |
-
1989
- 1989-03-15 JP JP6478089A patent/JPH02241081A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101005501B1 (en) * | 2008-06-16 | 2011-01-04 | (주)국민전자 | Method of making High Confidential PCB |
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