JPH0548242A - Etching method of metal copper film - Google Patents

Etching method of metal copper film

Info

Publication number
JPH0548242A
JPH0548242A JP3205090A JP20509091A JPH0548242A JP H0548242 A JPH0548242 A JP H0548242A JP 3205090 A JP3205090 A JP 3205090A JP 20509091 A JP20509091 A JP 20509091A JP H0548242 A JPH0548242 A JP H0548242A
Authority
JP
Japan
Prior art keywords
etching
film
copper film
metal copper
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3205090A
Other languages
Japanese (ja)
Inventor
Akira Muraki
明良 村木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP3205090A priority Critical patent/JPH0548242A/en
Publication of JPH0548242A publication Critical patent/JPH0548242A/en
Pending legal-status Critical Current

Links

Landscapes

  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To provide an etching method which enables a soldering film to be used as an etching mask and side etching of a metal copper film which is to be etched to be reduced. CONSTITUTION:A copper foil 10 which is formed on a glass epoxy substrate 1 and a metal copper film which consists of a copper plating layer 2 are subjected to etching by using a soldering film 3 which is placed on a surface of the above metal copper film as an etching mask, etching is stopped temporarily when a film thickness of the metal copper film reaches the half, the soldering film 3 is heated and fused and then an end face 15 of the metal copper film is coated by this melted solder, and then etching is restarted, thus enabling the remaining metal copper film to be etched. When this method is used and the etching treatment of a later stage is performed, the end face 15 of the metal copper film which is exposed by the etching treatment at the previous stage is coated by the fused solder, thus preventing that portion from being subjected to side etching and enabling an amount of the side etching to be reduced as compared with a case where an entire film thickness is subjected to etching all at once.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、金属銅皮膜の面上にパ
ターン状に形成されたはんだ皮膜をエッチングマスクに
して、例えばプリント配線板の製造等に利用される金属
銅皮膜のエッチング方法に係り、特に、エッチング対象
である金属銅皮膜のサイドエッチングを低減できるエッ
チング方法の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a metallic copper film used for manufacturing a printed wiring board, for example, by using a solder film formed in a pattern on the surface of the metallic copper film as an etching mask. In particular, the present invention relates to improvement of an etching method capable of reducing side etching of a metallic copper film which is an etching target.

【0002】[0002]

【従来の技術】この種のエッチング方法は上述したよう
にプリント配線板の製造等に広く利用されているが、以
下、『パネルメッキ法』と称される方法を例に挙げてそ
の概略を説明すると、図9に示すようにその両面に厚さ
35μm程度の銅箔aが一様に成膜されたガラスエポキ
シ基板bの適宜部位にドリル加工を施してスルーホール
cを穿設し、かつ、スルーホールc内壁面を高圧水洗浄
機により水洗すると共にそのドリルかすを適宜処理剤で
溶解除去した後(図10参照)、銅による無電解メッキ
処理を施して図11に示すように厚さ30μm程度の銅
メッキ層dを上記銅箔a上とスルーホールc内壁面に夫
々形成する。
2. Description of the Related Art This type of etching method is widely used in the production of printed wiring boards, etc., as described above, and the outline thereof will be described below by taking a method called "panel plating method" as an example. Then, as shown in FIG. 9, a glass epoxy substrate b, on which copper foil a having a thickness of about 35 μm is uniformly formed on both surfaces thereof, is drilled at appropriate portions to form through holes c, and After washing the inner wall surface of the through hole c with a high-pressure water washing machine and dissolving and removing the drill residue with a treating agent as appropriate (see FIG. 10), electroless plating with copper is performed to obtain a thickness of 30 μm as shown in FIG. A copper plating layer d of a certain degree is formed on the copper foil a and on the inner wall surface of the through hole c, respectively.

【0003】次いで、この銅メッキ層dの面上に図12
に示すようにドライフィルムパターンeを形成すると共
にこのドライフィルムパターンeから露出する部位には
んだメッキ層fを形成(図13参照)し、かつ、上記ド
ライフィルムパターンeを除去した(図14参照)後、
このはんだメッキ層fをエッチングマスクにしこのマス
クから露出する銅メッキ層dと銅箔aとをエッチングに
より順次除去してパターン状に配線層gを形成し(図1
5〜図16参照)、かつ、上記はんだメッキ層fを加熱
溶融して共晶はんだ組織を完成させると共にオーバーハ
ング(図15〜図16においてはんだメッキ層fのはみ
出し部分f0)を消滅させる(図17参照)等してプリ
ント配線板を求めている。
Next, the surface of the copper plating layer d is shown in FIG.
As shown in FIG. 5, a dry film pattern e is formed, a solder plating layer f is formed on a portion exposed from the dry film pattern e (see FIG. 13), and the dry film pattern e is removed (see FIG. 14). rear,
Using the solder plating layer f as an etching mask, the copper plating layer d and the copper foil a exposed from this mask are sequentially removed by etching to form a wiring layer g in a pattern (see FIG. 1).
5 to 16), and the above-mentioned solder plating layer f is heated and melted to complete the eutectic solder structure and the overhang (protruding portion f0 of the solder plating layer f in FIGS. 15 to 16) is eliminated (FIGS. 17)) to obtain a printed wiring board.

【0004】[0004]

【発明が解決しようとする課題】しかし、このようなエ
ッチング法にて上記配線層gを形成した場合、図15〜
図16に示すようにガラスエポキシ基板bとはんだメッ
キ層fとで挾まれた銅メッキ層dと銅箔aの厚み方向の
露出寸法が大きいため(この例では厚さ65μmとな
る)、厚さ65μmの銅メッキ層dと銅箔aとをエッチ
ング処理する際にこれ等銅メッキ層dと銅箔aの端面が
サイドエッチングを受け易く、その線幅寸法精度が悪く
なる欠点があり、配線密度を高める上で大きな妨げとな
る問題点があった。
However, when the wiring layer g is formed by such an etching method as shown in FIG.
As shown in FIG. 16, since the exposed dimension in the thickness direction of the copper plating layer d and the copper foil a sandwiched between the glass epoxy substrate b and the solder plating layer f is large (thickness is 65 μm in this example), When the copper plating layer d and the copper foil a having a thickness of 65 μm are etched, the end faces of the copper plating layer d and the copper foil a are susceptible to side etching, and the line width dimension accuracy is deteriorated. There was a problem that greatly hindered the increase of the.

【0005】本発明はこのような問題点に着目してなさ
れたもので、その課題とするところは、エッチング対象
である金属銅皮膜のサイドエッチングを低減できるエッ
チング方法を提供することにある。
The present invention has been made in view of such problems, and an object thereof is to provide an etching method capable of reducing side etching of a metallic copper film to be etched.

【0006】[0006]

【課題を解決するための手段】すなわち請求項1に係る
発明は、金属銅皮膜の面上にパターン状にはんだ皮膜を
形成し、このはんだ皮膜をエッチングマスクにして上記
金属銅皮膜をエッチングする金属銅皮膜のエッチング方
法を前提とし、上記金属銅皮膜をエッチングしその全膜
厚の途中までエッチング処理を施した時点で一旦エッチ
ングを停止し、次いで金属銅皮膜上のはんだ皮膜を加熱
溶融しかつエッチング処理にて露出した金属銅皮膜の端
面をこの溶融はんだにより被覆した後エッチングを再開
させて残りの金属銅皮膜をエッチングすることを特徴と
するものであり、他方、請求項2に係る発明は請求項1
に係る発明を前提とし、金属銅皮膜の膜厚がその全膜厚
の半分になった時点でエッチング処理を一旦停止するこ
とを特徴とするものである。
That is, the invention according to claim 1 is a metal for forming a solder film in a pattern on a surface of a metal copper film and etching the metal copper film by using the solder film as an etching mask. Assuming the copper film etching method, the above-mentioned metal copper film is etched, and when the etching process is performed up to the middle of the entire film thickness, the etching is temporarily stopped, and then the solder film on the metal copper film is heated and melted and etched. The invention is characterized in that the end surface of the metal copper film exposed by the treatment is covered with this molten solder and then etching is restarted to etch the remaining metal copper film. Item 1
On the premise of the invention according to (1), the etching process is temporarily stopped when the film thickness of the metallic copper film becomes half of the total film thickness.

【0007】このような技術的手段においてエッチング
の対象となる金属銅皮膜としては、適宜基板上に接着剤
を介して積層された銅箔でもよいしメッキ処理にて成膜
された銅メッキ層でもよくその形成手段にかかわらず任
意の金属銅皮膜がその対象となる。
The metallic copper film to be etched by such a technical means may be a copper foil laminated appropriately on a substrate with an adhesive or a copper plating layer formed by plating. Often, any metallic copper coating is the target, regardless of its formation means.

【0008】また、この金属銅皮膜の面上にはんだ皮膜
をパターン状に形成する手段としては、上記金属銅皮膜
の面上にドライフィルムパターンやフォトレジストパタ
ーンを予め形成しこのパターンから露出する金属銅皮膜
面上にメッキ法にて選択的に形成する方法を採ってもよ
いし、あるいは金属銅皮膜の面上に適宜方法にてはんだ
皮膜を一様に成膜しかつこの皮膜上にドライフィルムパ
ターンやフォトレジストパターンを形成した後このパタ
ーンから露出するはんだ皮膜を適宜エッチング剤により
溶解除去して選択的に形成する方法を採ってもよくその
形成手段についても任意である。
As a means for forming a solder film in a pattern on the surface of the metal copper film, a dry film pattern or a photoresist pattern is previously formed on the surface of the metal copper film, and a metal exposed from this pattern is formed. A method of selectively forming on the copper film surface by plating method may be adopted, or a solder film may be uniformly formed on the surface of the metal copper film by an appropriate method and a dry film may be formed on this film. A method of forming a pattern or a photoresist pattern and then selectively removing the solder film exposed from the pattern by dissolving and removing it with an etching agent may be adopted, and the forming means is also arbitrary.

【0009】尚、上記はんだ皮膜を構成する『はんだ』
としては、従来法にて利用されているPb−Sn合金、
Pb−Ag合金、Bi−Sn合金等が適用できる。
[Solder] that constitutes the above-mentioned solder film
As a Pb-Sn alloy used in the conventional method,
A Pb-Ag alloy, a Bi-Sn alloy, etc. can be applied.

【0010】次に、前段のエッチング処理を停止するタ
イミングについては、金属銅皮膜のエッチングが開始さ
れてその膜厚が減少し始めた後において任意に設定でき
るが、その停止タイミングの具合により前段と後段のエ
ッチングすべき金属銅皮膜の膜厚寸法の差が大きくなる
とその膜厚の大きい分のエッチング処理の際にそのサイ
ドエッチング量が大きくなり好ましくない。従って、金
属銅皮膜の膜厚が全膜厚分の略半分程度になった時点で
停止する方法が望ましい。
Next, the timing of stopping the etching process of the former stage can be arbitrarily set after the etching of the metal copper film is started and the film thickness thereof starts to decrease. If the difference in the film thickness dimension of the metallic copper film to be etched in the subsequent stage becomes large, the side etching amount becomes large during the etching treatment for the large film thickness, which is not preferable. Therefore, a method of stopping when the film thickness of the metal copper film becomes about half of the total film thickness is desirable.

【0011】請求項2に係る発明はこのような技術的背
景から創作されており、上記金属銅皮膜の膜厚がその全
膜厚の半分になった時点でエッチング処理を一旦停止す
ることを特徴とするものである。
The invention according to claim 2 is created from such a technical background, and the etching process is temporarily stopped when the film thickness of the metal copper film becomes half of the total film thickness thereof. It is what

【0012】尚、この技術的手段は、片面プリント配線
板、両面プリント配線板、及び多層プリント配線板等プ
リント配線板の製造法に適用できるが、他の用途の金属
銅皮膜のエッチング法にも当然のことながら適用するこ
とができる。
Although this technical means can be applied to a method for manufacturing a printed wiring board such as a single-sided printed wiring board, a double-sided printed wiring board, and a multilayer printed wiring board, it can also be applied to an etching method of a metal copper film for other purposes. Of course, it can be applied.

【0013】[0013]

【作用】請求項1に係る発明によれば、金属銅皮膜をエ
ッチングしその全膜厚の途中までエッチング処理を施し
た時点で一旦エッチングを停止し、次いで金属銅皮膜上
のはんだ皮膜を加熱溶融しかつエッチング処理にて露出
した金属銅皮膜の端面をこの溶融はんだにより被覆した
後エッチングを再開させて残りの金属銅皮膜をエッチン
グしていることから、後段のエッチング処理の際、前段
のエッチング処理にて露出した金属銅皮膜の端面が溶融
はんだにより被覆されているためその部位のサイドエッ
チングを防止でき、従って、金属銅皮膜の全膜厚分を一
度にエッチング処理した場合と較べそのサイドエッチン
グ量の低減を図ることが可能となる。
According to the first aspect of the invention, the etching of the metallic copper film is stopped once the metallic copper film is etched and the etching treatment is performed up to the middle of the entire film thickness, and then the solder film on the metallic copper film is heated and melted. In addition, since the end surface of the metal copper film exposed by the etching process is covered with this molten solder and then the etching is restarted to etch the remaining metal copper film, the etching process of the first stage is performed during the etching process of the second stage. Since the end surface of the metal copper film exposed at step is covered with molten solder, side etching at that part can be prevented. Therefore, the side etching amount compared to the case where the entire film thickness of the metal copper film is etched at once. Can be reduced.

【0014】また、請求項2に係る発明によれば、金属
銅皮膜の膜厚がその全膜厚の半分になった時点でエッチ
ング処理を一旦停止していることから、前段と後段のエ
ッチングすべき金属銅皮膜の膜厚寸法が同一となり、各
エッチング時におけるサイドエッチング量が略等しくな
るためこれ等のサイドエッチング量を最少限に抑えるこ
とが可能となる。
Further, according to the second aspect of the invention, since the etching process is temporarily stopped when the film thickness of the metallic copper film becomes half of its total film thickness, the etching of the former stage and the latter stage is performed. Since the film thicknesses of the metallic copper films to be formed are the same and the side etching amounts at each etching are substantially equal, it is possible to minimize these side etching amounts.

【0015】[0015]

【実施例】以下、本発明を両面プリント配線板の製造に
適用した実施例について図面を参照して詳細に説明す
る。
Embodiments of the present invention applied to the manufacture of a double-sided printed wiring board will be described in detail below with reference to the drawings.

【0016】まず、その両面に厚さ35μmの銅箔10
が貼り合されたガラスエポキシ基板1の適宜部位にドリ
ルマシーンにてスルーホール11を穿設し、このスルー
ホール11内壁面を高圧水洗浄機により水洗し、かつ、
内壁面に融着したドリルかすを過マンガン酸カリと水酸
化ナトリウムの混合溶剤で溶解除去(デスミア処理)し
た後、銅による無電解メッキ処理を施して上記銅箔10
とスルーホール11内壁面に薄膜の銅メッキ層を成膜
し、続いて硫酸銅による電解メッキ処理を施し全体とし
て厚さ25μmの銅メッキ層2を成膜した(図2参
照)。
First, a copper foil 10 having a thickness of 35 μm is formed on both sides thereof.
Through holes 11 are drilled by a drill machine at appropriate portions of the glass epoxy substrate 1 to which is adhered, and the inner wall surface of the through holes 11 is washed with a high pressure water washing machine, and
After removing the drill residue fused to the inner wall surface with a mixed solvent of potassium permanganate and sodium hydroxide (desmear treatment), electroless plating treatment with copper is applied to the copper foil 10.
Then, a thin copper plating layer was formed on the inner wall surface of the through hole 11, followed by electrolytic plating with copper sulfate to form a copper plating layer 2 having a total thickness of 25 μm (see FIG. 2).

【0017】次に、上記銅メッキ層2の面上にメッキ処
理にてPb−Sn合金より成る厚さ30μmのはんだ皮
膜3を一様に成膜し(図3参照)、かつ、この面上に通
常の処理にて厚さ20μmのドライフィルム4をラミネ
ータ機により貼り合わせた(図4参照)後、このドライ
フィルム4面へ回路パターンを露光しかつ現像処理を施
して図5に示すようにドライフィルムパターン40を形
成した。
Next, a 30 μm thick solder coating 3 of Pb—Sn alloy is uniformly formed on the surface of the copper plating layer 2 by plating (see FIG. 3), and on this surface. After the dry film 4 having a thickness of 20 μm is laminated by a laminator by a normal process (see FIG. 4), a circuit pattern is exposed on the surface of the dry film 4 and a development process is performed to form a dry film 4 as shown in FIG. A dry film pattern 40 was formed.

【0018】次いで、市販のはんだエッチング液を用い
て上記ドライフィルムパターン40から露出するはんだ
皮膜3をエッチングにより除去し、かつ、ドライフィル
ムパターン40を剥離して図6に示すように残留するは
んだ皮膜3を露出させた後、このはんだ皮膜3をエッチ
ングマスクとし銅エッチング剤を用いて25μm厚の銅
メッキ層2と35μm厚の銅箔10より成る全膜厚60
μmの金属銅皮膜をエッチング処理した。そして、エッ
チングされた膜厚がその全膜厚の半分(すなわち30μ
m)になった時点でエッチング処理を一旦停止し、か
つ、エッチング部位を水洗処理にて十分に洗浄すると共
に残留する非水溶性の不純物を希硫酸にて数秒間溶解処
理した後、再度水洗処理により十分な洗浄を行った(図
7参照)。この際、上記エッチング処理を金属銅皮膜の
膜厚が半分になった時点で一旦停止しているため、金属
銅皮膜の全膜厚を一度にエッチング処理する場合と較べ
てエッチングすべき皮膜の膜厚が相対的に薄くなり、そ
の分、図1(A)に示すようにそのサイドエッチングを
低減できる利点を有している。
Next, the solder film 3 exposed from the dry film pattern 40 is removed by etching using a commercially available solder etching solution, and the dry film pattern 40 is peeled off to leave the solder film remaining as shown in FIG. 3 is exposed, and then the solder coating 3 is used as an etching mask and a copper etching agent is used to form a copper plating layer 2 having a thickness of 25 μm and a copper foil 10 having a thickness of 35 μm.
The metallic copper film having a thickness of μm was etched. The etched film thickness is half of the total film thickness (that is, 30 μm).
When m) is reached, the etching process is temporarily stopped, and the etching site is thoroughly washed with water, and the remaining non-water-soluble impurities are dissolved in dilute sulfuric acid for several seconds, and then washed again. Was used for sufficient washing (see FIG. 7). At this time, since the etching process is temporarily stopped when the film thickness of the metal copper film is halved, the film film of the film to be etched as compared with the case where the entire film thickness of the metal copper film is etched at once. The thickness is relatively thin, and as a result, there is an advantage that side etching can be reduced as shown in FIG.

【0019】次いで、金属銅皮膜上のはんだ皮膜3を遠
赤外加熱装置により加熱溶融し、かつ、エッチング処理
にて露出した金属銅皮膜の端面15(図1A参照)をこ
の溶融はんだにより被覆した(図1B参照)。尚、上記
金属銅皮膜の端面15を溶融はんだにより確実に被覆さ
せるため、上記加熱処理条件は230℃、3分間とし
た。
Next, the solder coating 3 on the metallic copper coating is heated and melted by a far infrared heating device, and the end surface 15 (see FIG. 1A) of the metallic copper coating exposed by the etching treatment is coated with this molten solder. (See Figure 1B). The heat treatment condition was 230 ° C. for 3 minutes in order to surely coat the end surface 15 of the metallic copper film with the molten solder.

【0020】そして、上記金属銅皮膜の端面15を溶融
はんだにより被覆した状態でエッチング処理を再開し、
残り30μm厚の金属銅皮膜をエッチング(図8参照)
し、かつ、市販のはんだ剥離液にてはんだ皮膜3を剥離
させて銅箔と銅メッキ層から成る回路パターンを得た。
この後段のエッチング処理の際、上記金属銅皮膜の端面
15が溶融はんだにより被覆されているためこの部位の
サイドエッチングは防止されることになる。そして、後
段のエッチング処理においてサイドエッチングを受ける
部位は、この後段のエッチング対象である残り30μm
厚の金属銅皮膜の端面のみになるため、前段のエッチン
グ処理と同様、図1(C)に示すようにそのサイドエッ
チングを低減できる利点を有している。
Then, the etching process is restarted with the end surface 15 of the metallic copper film covered with the molten solder,
Etching the remaining 30 μm thick copper metal film (see FIG. 8)
Then, the solder coating 3 was peeled off with a commercially available solder peeling liquid to obtain a circuit pattern composed of a copper foil and a copper plating layer.
During the subsequent etching process, since the end surface 15 of the metallic copper film is covered with the molten solder, side etching of this portion is prevented. Then, the portion that undergoes side etching in the latter-stage etching treatment is the remaining 30 μm which is the target of the latter-stage etching.
Since only the end face of the thick metal copper film is formed, it has an advantage that side etching can be reduced as shown in FIG.

【0021】従って、25μm厚の銅メッキ層2と35
μm厚の銅箔10より成る金属銅皮膜の全膜厚分(60
μm)を一度にエッチング処理した場合に較べてそのサ
イドエッチング量を低減できるため、線幅寸法精度が向
上しその配線密度を高められる利点を有している。事
実、銅箔と銅メッキ層から成る上記回路パターンはドラ
イフィルムパターン40の再現性が良く、35μm銅箔
にて50μmラインアンドスペースを良好に形成でき
た。
Therefore, the copper plating layers 2 and 35 having a thickness of 25 μm are formed.
The total film thickness of the metallic copper film composed of the copper foil 10 having a thickness of μm (60
Since the side etching amount can be reduced as compared with the case where the etching treatment is performed at a time, the line width dimension accuracy is improved and the wiring density can be increased. In fact, the above-mentioned circuit pattern composed of a copper foil and a copper plating layer had a good reproducibility of the dry film pattern 40, and a 50 μm line and space could be formed well with a 35 μm copper foil.

【0022】[0022]

【発明の効果】請求項1に係る発明によれば、後段のエ
ッチング処理の際、前段のエッチング処理にて露出した
金属銅皮膜の端面が溶融はんだにより被覆されているた
めその部位のサイドエッチングを防止でき、上記金属銅
皮膜の全膜厚分を一度にエッチング処理した場合と較べ
そのサイドエッチング量の低減を図ることが可能とな
る。
According to the first aspect of the present invention, during the subsequent etching process, since the end face of the metallic copper film exposed in the previous etching process is covered with the molten solder, the side etching of that portion is prevented. This can be prevented, and the side etching amount can be reduced as compared with the case where the entire film thickness of the metal copper film is etched at once.

【0023】従って、従来法に較べてエッチング精度の
向上が図れるため、例えばプリント配線板の製造等にこ
の方法を適用した場合に配線密度を高められる効果を有
している。
Therefore, since the etching accuracy can be improved as compared with the conventional method, there is an effect that the wiring density can be increased when this method is applied to, for example, the manufacture of a printed wiring board.

【0024】また、請求項2に係る発明によれば、前段
と後段のエッチングすべき金属銅皮膜の膜厚寸法が同一
で各エッチング時におけるサイドエッチング量が略等し
くなるためこれ等のサイドエッチング量を最少限に抑え
ることが可能となり、従って、エッチング精度を更に向
上できる効果を有している。
Further, according to the second aspect of the invention, since the film thickness dimensions of the metal copper film to be etched in the front and rear stages are the same and the side etching amounts at each etching are substantially equal, these side etching amounts are the same. Can be suppressed to a minimum, and therefore, the etching accuracy can be further improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1Aは実施例に係る前段のエッチング工程の
説明図、図1Bははんだ皮膜の加熱溶融工程の説明図、
図1Cは後段のエッチング工程の説明図。
FIG. 1A is an explanatory diagram of a first-stage etching process according to an embodiment, FIG. 1B is an explanatory diagram of a heating and melting process of a solder film,
FIG. 1C is an explanatory diagram of a subsequent etching process.

【図2】実施例に係るエッチング方法の工程図。FIG. 2 is a process drawing of an etching method according to an embodiment.

【図3】実施例に係るエッチング方法の工程図。FIG. 3 is a process drawing of an etching method according to an embodiment.

【図4】実施例に係るエッチング方法の工程図。FIG. 4 is a process drawing of an etching method according to an embodiment.

【図5】実施例に係るエッチング方法の工程図。FIG. 5 is a process drawing of an etching method according to an embodiment.

【図6】実施例に係るエッチング方法の工程図。FIG. 6 is a process drawing of an etching method according to an embodiment.

【図7】実施例に係るエッチング方法の工程図。FIG. 7 is a process drawing of the etching method according to the embodiment.

【図8】実施例に係るエッチング方法の工程図。FIG. 8 is a process drawing of the etching method according to the embodiment.

【図9】実施例に係るエッチング方法の工程図。FIG. 9 is a process drawing of the etching method according to the embodiment.

【図10】従来のエッチング方法の工程図。FIG. 10 is a process diagram of a conventional etching method.

【図11】従来のエッチング方法の工程図。FIG. 11 is a process diagram of a conventional etching method.

【図12】従来のエッチング方法の工程図。FIG. 12 is a process diagram of a conventional etching method.

【図13】従来のエッチング方法の工程図。FIG. 13 is a process diagram of a conventional etching method.

【図14】従来のエッチング方法の工程図。FIG. 14 is a process diagram of a conventional etching method.

【図15】従来のエッチング方法の工程図。FIG. 15 is a process diagram of a conventional etching method.

【図16】図15の部分拡大図。16 is a partially enlarged view of FIG.

【図17】はんだメッキ層を加熱溶融させた状態を示す
説明図。
FIG. 17 is an explanatory view showing a state in which a solder plating layer is heated and melted.

【符号の説明】[Explanation of symbols]

1 ガラスエポキシ基板 2 銅メッキ層 3 はんだ皮膜 10 銅箔 15 端面 1 Glass epoxy substrate 2 Copper plating layer 3 Solder film 10 Copper foil 15 Edge surface

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 金属銅皮膜の面上にパターン状にはんだ
皮膜を形成し、このはんだ皮膜をエッチングマスクにし
て上記金属銅皮膜をエッチングする金属銅皮膜のエッチ
ング方法において、 上記金属銅皮膜をエッチングしその全膜厚の途中までエ
ッチング処理を施した時点で一旦エッチングを停止し、
次いで金属銅皮膜上のはんだ皮膜を加熱溶融しかつエッ
チング処理にて露出した金属銅皮膜の端面をこの溶融は
んだにより被覆した後エッチングを再開させて残りの金
属銅皮膜をエッチングすることを特徴とする金属銅皮膜
のエッチング方法。
1. A method for etching a metal copper film, comprising forming a solder film in a pattern on a surface of the metal copper film and etching the metal copper film by using the solder film as an etching mask. Then, when the etching process is performed halfway through the entire film thickness, the etching is temporarily stopped,
Next, the solder film on the metallic copper film is heated and melted, and the end surface of the metallic copper film exposed by the etching treatment is covered with this molten solder, and then etching is restarted to etch the remaining metallic copper film. Etching method for metallic copper film.
【請求項2】 上記金属銅皮膜の膜厚がその全膜厚の半
分になった時点でエッチング処理を一旦停止することを
特徴とする請求項1記載の金属銅皮膜のエッチング方
法。
2. The etching method for a metal copper film according to claim 1, wherein the etching process is temporarily stopped when the film thickness of the metal copper film becomes half of the total film thickness.
JP3205090A 1991-08-15 1991-08-15 Etching method of metal copper film Pending JPH0548242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3205090A JPH0548242A (en) 1991-08-15 1991-08-15 Etching method of metal copper film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3205090A JPH0548242A (en) 1991-08-15 1991-08-15 Etching method of metal copper film

Publications (1)

Publication Number Publication Date
JPH0548242A true JPH0548242A (en) 1993-02-26

Family

ID=16501267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3205090A Pending JPH0548242A (en) 1991-08-15 1991-08-15 Etching method of metal copper film

Country Status (1)

Country Link
JP (1) JPH0548242A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7546681B2 (en) 1999-10-12 2009-06-16 Tessera Interconnect Materials, Inc. Manufacturing method for wiring circuit substrate
CN104233298A (en) * 2014-09-12 2014-12-24 昆山科森科技股份有限公司 Manufacture method for metal material strip continuous etching processing
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7546681B2 (en) 1999-10-12 2009-06-16 Tessera Interconnect Materials, Inc. Manufacturing method for wiring circuit substrate
US7721422B2 (en) 1999-10-12 2010-05-25 Tessera Interconnect Materials, Inc. Methods of making microelectronic assemblies
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates
US10283484B2 (en) 2013-10-04 2019-05-07 Invensas Corporation Low cost substrates
CN104233298A (en) * 2014-09-12 2014-12-24 昆山科森科技股份有限公司 Manufacture method for metal material strip continuous etching processing

Similar Documents

Publication Publication Date Title
JP2006344921A (en) Manufacturing method for printed circuit board
JPH1187931A (en) Manufacture of printed circuit board
JPH0548242A (en) Etching method of metal copper film
JPS59215793A (en) Method of reproducing copper conductor with defect on outer surface of outer layer circuit
JPH1187886A (en) Production of printed wiring board
JPH0964538A (en) Production of printed wiring board
JP3123109B2 (en) Multilayer wiring board and its manufacturing method
JP2713037B2 (en) Printed wiring board and manufacturing method thereof
JPS6182497A (en) Manufacture of printed circuit board
EP0488299B1 (en) Method of manufacturing a multi-layered wiring board
JP3202840B2 (en) Multilayer printed wiring board
JPH05110254A (en) Manufacture of multilayer printed wiring board
JPS6337515B2 (en)
JP3217563B2 (en) Manufacturing method of printed wiring board
JP3747897B2 (en) Manufacturing method of tape carrier for semiconductor device and semiconductor device using the same
JP2874330B2 (en) Method for manufacturing multilayer printed wiring board
JPH08139435A (en) Manufacture of printed wiring board
JPH0621611A (en) Manufacture of printed wiring board
JP3123107B2 (en) Method for manufacturing multilayer wiring board
JPH08186357A (en) Printed wiring board and manufacture thereof
JPH07115275A (en) Manufacture of multilayer printed wiring board
JPH0521954A (en) Manufacture of printed wiring board
JPS59175797A (en) Method of producing multilayer printed plate
JPH0613753A (en) Manufacture of aluminium substrate for semiconductor use
JPS6170790A (en) Method of producing printed circuit board

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees