JPH0223649A - Semiconductor device - Google Patents

Abstract

PURPOSE:To lower a base resistance and realize a high speed operation of elements by forming the first and second base regions separately and forming metal silicide layers on surfaces of the base regions and a base electrode. CONSTITUTION:Side wall spacers 30 consisting of phosphoglass films are formed on emitter and collector electrodes 5 and 6 and, further, at the side wall of a base electrode 7 and they are used as masks when impurities are introduced in an Si layer. Moreover, metal silicide layers 31 are formed selectively on the surface of a base region as well as surfaces of the emitter, collector, and base electrodes 5, 6 and 7. The above-mentioned structure allows the first and second regions 4a and 4b to be formed separately and causes an impurity concentration of the second base region 4b to be higher than that of the first base region 4a and, further, lowers a base resistance rbb'. The formation of the metal silicide layers 31 on the surfaces of base regions and the base electrode lowers the base resistance and improves the operating speed of a transistor.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically to a bipolar transistor and a bipolar-CMO3 (hereinafter referred to as B1-C
It is abbreviated as MOS. ) Regarding the structure of the element.

[Prior art] In order to achieve higher speed and higher density, the bipolar transistor in conventional bipolar transistor ICs employs a polycrystalline silicon emitter (sometimes called a washed emitter) structure. ing. The second example of the structure of this type of bipolar transistor is
As shown in the figure.

In FIG. 2, the bipolar transistor is of the npn type and is formed within an n-type evixaxially grown S1 layer 2 formed on the main surface of a p-type Si substrate 1. The n-type epitaxially grown Si layer 2 forms a collector region, and an n"-type buried layer 3 is formed below it. Further, a p-type base region 4 is formed in this n-type epitaxially grown Si layer 2, and furthermore, a p-type base region 4 is formed in this n-type epitaxially grown Si layer 2. 4, an n9 type emitter region 8 is formed by diffusion from the n9 type polycrystalline Si layer 5.

Further, in another part of this n-type epitaxially grown Si layer 2, an n+-type collector diffusion layer 9 reaching the n-type buried layer 3 is provided.
is formed.

In addition, in the figure, 10 is a p + type channel stopper region, 11
12 is an oxide (Sin) film, 5 is for forming a polycrystalline Si emitter electrode made of the above-mentioned n-type polycrystalline Si layer, and 6 is the same (n+-type polycrystalline Si layer).
This is a collector region consisting of an i layer. 4a is a first base region, 4b is a second base region, and 4c is a p'' type diffusion layer for drawing out the base electrode.

[Problem to be solved by the invention] However, in the conventional semiconductor device as described above,
There are problems in device characteristics mainly caused by base resistance, parasitic capacitance, etc. as listed below.

(1) In the structure of a conventional bipolar transistor, the base resistance r bb' and the base-collector capacitance C
The high cB has an adverse effect on the high frequency characteristics of the transistor, and is an obstacle to increasing the speed of the device.

(2) To lower the base resistance r bb', it is sufficient to increase the impurity concentration in the base region.
According to the structure of the conventional bipolar transistor shown in the figure, since the impurity concentration of the p-type base region 4 is uniform, the impurity concentration of the entire base region 4 is equal to the current amplification factor (current amplification factor) below the emitter region 8, which affects IFE. It must be determined based on the impurity concentration of the first base region 4a. That is,
Since the impurity concentration of the second base region 4b is determined according to the impurity concentration of the first base region 4a required to obtain the desired hFE, the base resistance can only be lowered to a certain extent, which increases the speed of the bipolar transistor. There are limits to what you can do.

(3) As junctions become shallower due to miniaturization of elements in order to increase the degree of integration of ICs, the base resistance increases, which slows down the operating speed of the elements as in the case described above.

(4) The distance between the emitter electrode 5 and the P1 type diffusion layer 4c for protruding the base electrode is determined due to the limit of mask overlay accuracy in the element manufacturing process, and there is a limit to reducing the area of the base region. , base-collection capacitance CC
This makes it impossible to reduce the capacitance Ccs between B and the collector substrate, which becomes an obstacle to increasing the density and speed of transistors.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and an object of the present invention is to provide a semiconductor device suitable for high integration in which the operating speed of a bibora transistor is significantly improved.

[Means for Solving the Problems] A semiconductor device of the present invention includes a first semiconductor device formed on a semiconductor substrate.
a base region made of a conductivity type impurity diffusion layer; an emitter region made of a second conductivity type impurity diffusion layer formed in the base region; and a second conductivity type polycrystalline silicon provided on the emitter region. an emitter electrode consisting of a layer;
In the semiconductor device, the base electrode includes a polycrystalline silicon layer of a first conductivity type, which is provided from the base region to the inter-element insulation isolation region and is the same layer as the polycrystalline silicon layer. The semiconductor device is characterized by having a sidewall spacer formed on a sidewall, and a metal silicide layer formed on the surfaces of the emitter electrode, the base electrode, and the base region.

Further, the semiconductor device of the present invention includes the above-mentioned bipolar transistor, a first channel type MO3I-transistor having a gate electrode made of a first conductivity type polycrystalline silicon layer in the same layer as the above-mentioned polycrystalline silicon layer, and the above-mentioned polycrystalline silicon layer. In a semiconductor device comprising, on the same semiconductor substrate, a second channel type MOS transistor having a gate electrode made of a polycrystalline silicon layer of a second conductivity type in the same layer as a crystalline silicon layer, and a second channel type MOS transistor formed on a side wall of the gate electrode. The semiconductor device is characterized by comprising a sidewall spacer and a metal silicide layer formed on the surface of the impurity diffusion layer forming the source and drain regions formed on the gate electrode and the semiconductor substrate.

[Example] Hereinafter, typical examples of the present invention will be specifically described using the drawings.

FIG. 1 is a sectional view showing an embodiment in which the present invention is applied to a bipolar transistor in a bipolar IC.

In FIG. 1, the bipolar transistors are of the npn type, and numerals 1 to 6 and 8 to 12 in the figure are exactly the same as those of the conventional semiconductor device shown in FIG. 2 above. 7 is a p''' provided from the base region 4 to the inter-element insulating isolation film 11.
The base electrode is a polymorphic crystalline Si layer. Note that these emitter electrode 5, collector electrode 6, and base electrode 7
The polycrystalline Si layers that form the same layer.

In the configuration shown in FIG. 1, the second base region 4b has a deeper impurity diffusion depth than the first base region 4a due to the diffusion of p-type impurities from the base electrode 7 made of a p+-type polycrystalline Si layer. It is also formed to have a high concentration.

Further, sidewall spacers 30 made of a phosphorus glass (PSG) film are formed on the side walls of the emitter electrode 5 and collector electrode 6 made of an n" type polycrystalline Si layer and the base electrode 7 made of a p4 type polycrystalline Si layer. This sidewall spacer 30 is used as part of a mask when introducing impurities into the polycrystalline Si layer.

Further, a metal silicide layer 3 is provided on the surface of the base region and the surfaces of the emitter electrode 5, collector electrode 6, and base electrode 7.
1 is selectively formed.

Note that the metal silicide layer 31 is made of titanium, tungsten, molybdenum, platinum, cobalt, or the like. Here, sidewall spacers are also used to separate metal silicide layers.

According to the structure of the above embodiment, the first base region 4a and the second base region 4b of the bipolar transistor are formed separately, and the impurity concentration of the second base region 4b is higher than that of the first base region 4a. (Since the base resistance r bb' can be
By forming a metal silicide layer on the surface of the base region and base electrode, the base resistance can be further lowered and the operating speed of the transistor can be improved.

Further, the emitter electrode 5 and the base electrode 7 are made of the same polycrystalline S1 layer, and the second base region is made of p+ type polycrystalline Si7.
Since the base area is positioned in a self-aligned manner by impurity diffusion from the substrate, the base area can be significantly reduced without having to consider mask overlay accuracy during the manufacturing process as in conventional structures. As a result, high integration is possible, as well as base-to-collection capacitance CCB and collector-to-substrate capacitance C6.
This has the effect of reducing parasitic capacitance such as 8, etc., improving the high frequency characteristics of the transistor, and increasing the speed of the device.

Furthermore, since the second base region can be stably formed by diffusion from the p9 type polycrystalline Si layer, problems caused by shallow junctions can be avoided.

In addition, since the steps of the polycrystalline silicon layer are alleviated by the side wall spacers, the step coverage of the wiring layer formed thereon is good (this improves the reliability of the wiring layer, such as electromigration resistance and stress migration resistance). improves.

Next, a method for manufacturing the semiconductor device of the above embodiment is shown in FIG.
) to (e) will be explained in order.

(1) FIG. 3(a) shows a part of a semiconductor substrate that has been preprocessed by a conventional technique in order to manufacture a semiconductor device according to the present invention. In the figure, the p-type Si substrate 1 has n″″
A mold buried layer 3 and a p'' type channel stopper region 10 are formed, an n type epitaxially grown Si layer 2 and an inter-element insulating isolation film 11 are formed thereon, and an n+ type collector diffusion layer 9 is diffused. Note that 12 in the figure is an oxide (Si02) film.

Furthermore, boron (B) is added to the base forming area at 10 to 25K.
After ion implantation of approximately 1 x 10'' to 5 x 1014 cm-2 using e■, the 5-ins film in the emitter formation area, collector electrode formation area, and base electrode formation area was selectively removed, and the entire surface was subjected to chemical vapor deposition (CVD). Polycrystalline Si
An emitter electrode 5a made of a polycrystalline Si layer is formed by depositing a layer of about 0.2 to 0.4 μm and then photo-etching.
A state in which a base electrode 7a and a collector electrode 6a are formed is shown. Note that 4 in the figure is a p-type base region.

(2) In Fig. 3(b), a PSG film is deposited on the entire surface shown in (b) by the CVD method, and then anisotropic etching (R
IE) method, and PS is selectively applied to the side walls of the emitter type 5a, base type 7a, and collector type 6a.
A state in which a sidewall spacer 30 made of a G film is formed is shown.

(3) In FIG. 3(C), a photoresist film 13 is formed except for the emitter electrode formation region and the collector electrode formation region, and 60% of arsenic (As) or phosphorus (P) is applied to the polycrystalline Si layers 5a and 6a. ~100Ke■, 5X 10"~IX
The figure shows the state where ion implantation of 016 cm-'' has been performed. In the figure, 14 indicates AS or P ions. At this time, the sidewall spacer 30 is used as a part of the mask for ion implantation, and the mask The alignment accuracy can be made looser.

(4) In FIG. 3(d), a photoresist film 13 is formed except for the base electrode formation region, and polycrystalline S1 layer 7a Heboron (B) is 30 to 60 Ke■, 1 to 5 X l 015
cm”2 or 80 to 1 of boron fluoride (BF2)
00Ke■, 1~5xlQ"5cm-" ion implantation is shown.

In addition, in the figure, 15 represents B or BFa ion. In this case, as in (3), sidewall spacer 3
0 is used as part of the mask for ion implantation.

(5) Figure 3(e) is 800~1000°Cl2O~
Heat treatment for about 30 minutes or 1000-1050℃,
After lamp annealing for about 10 to 60 seconds, a metal silicide layer 31 is formed on the surfaces of the base region, emitter electrode 5, collector electrode 6, and base electrode 7. That is, removing unnecessary oxide film on the base region,
After exposing the Si substrate, titanium is applied to the entire surface of the substrate at a coating temperature of 200~
After 1000 people adhered, 600-800℃, 10-6
Silicide treatment of titanium is performed by lamp annealing for 0 seconds. In this case, only the regions where the Si and polycrystalline S1 layers are exposed are silicided, and the other regions remain titanium. Furthermore, unreacted titanium was removed using sulfuric acid/hydrogen peroxide (H
2SO4/H20□) solution or NH40H/H20
□/H20 solution etc. to selectively remove unnecessary titanium and create titanium silicide (TiSi2
) layers are formed.

At this stage, a bipolar transistor structure is formed, and the depths of the n+ type emitter region 8 and first base region 4a are approximately 0.05 to 0.15 μm and 01 to 0.3 μm, respectively. Note that the depth of this junction can be set to a desired depth by heat treatment.

Thereafter, the electrodes are drawn out by a conventional method, and a semiconductor device having the above-mentioned effects is obtained.

FIG. 4 is another embodiment of the present invention, which is a sectional view of an IC semiconductor device, ie, B1-CMOSIC, which includes a bipolar element and a CMO3 element on the same substrate.

In FIG. 4, the same reference numerals as in FIG. 1 are used for parts 1 and 3 to 12, 30, and 31. The separation between the bipolar transistor region and the P-channel MOS transistor region and between the bipolar transistor region and the bipolar transistor region is achieved by forming a p1 type buried layer 10 formed on a p type Si substrate 1 and an n type epitaxially grown Si layer. and a field oxide film 11 selectively formed on the surface of the p-type channel stopper layer 18 whose bottom portion is in contact with the p + type buried layer 10 . In addition, in the figure,
16 is an n-type well, 17 is an n-type well, 19 is an n1-type polycrystalline Si gate electrode, 20 is a p1-type polycrystalline Si gate electrode, 21 is a gate oxide film, 22 is an n+ type source/drain region, 22a is n − type offset region, and 23 is a p+ type sos drain region.

Regarding the structure of NMO3 and PMO3 constituting the CMOS, NMO3 adopts an LD'D (lightly doped drain) structure as a countermeasure against hot electrons accompanying miniaturization, whereas PMO5 has a normal structure. Note that there is no problem in making PMO8 also have an LDD structure.

The bipolar transistor is of the npn type, and has an emitter electrode 5 and a collector electrode 6 made of an n+ type polycrystalline S1 layer.
and p+ type polycrystalline Si in the same layer as the n1 type polycrystalline S1 layer.
It has a base electrode 7 made of layers. Further, the N-channel type MO3I- transistor has a gate electrode 19 made of an n+ type polycrystalline Si layer which is the same layer as the n+ type polycrystalline Si layer.

The P channel type MOS transistor has a gate electrode 20 made of a p'' type polycrystalline Si layer which is the same layer as the p'' type polycrystalline Si layer. Furthermore, the polycrystalline S of each transistor
Sidewall spacers 30 are formed on the side walls of the electrodes 5, 6, 7, 19, and 20 made of the i-layer, and metal silicide layers are formed on the surfaces of these electrodes, the base region, and the source/drain 22, 23. ing.

Next, a method for manufacturing the semiconductor device shown in FIG. 4 is shown in FIGS.
The cross-sectional views according to manufacturing steps in (e) will be sequentially explained. In addition, in the figure, the symbols are the same as those in FIG. 4.

(1) First, FIG. 5(a) shows a part of a semiconductor substrate that has been preliminarily processed to manufacture this semiconductor device. In the figure, an n'''-type buried layer 3 and a p4-type buried layer 10 are formed on a p-type Si substrate, and an n-type epitaxially grown Si layer is formed thereon. n-type well 16 and n-type well 17
is formed. Note that the n + type buried layer 3 and n type well 16 are in the bipolar element and PMO3 element formation region, and the p + type buried layer 10 and n type well 17 are in the NMO3 element formation region.
It is formed in the three element formation region. Furthermore, a p3 type buried layer 10, a channel stopper layer 18, and a field oxide film 11 are formed in the element isolation region. Further, FIG. 5(a) also shows a state in which an n+ type collector diffusion layer 9 is formed. In this method, phosphorus (P) is selectively ion-implanted into this portion and then heat-treated and diffused.

(2) In FIG. 5(b), the gate oxide film 21 is
After the formation of about 0.00 people, a resist film 13 with openings only in the base formation region is formed, and boron ion implantation is performed at 10 to 30Ke, IX 1 to form the base region.
013-5x This shows the state where the test was carried out at about 10"Cm-".

(3) In FIG. 5(C), the gate oxide film in the emitter formation region, collector electrode formation region, and base electrode formation region is selectively removed, and a polycrystalline Si layer is deposited on the entire surface by CVD.
The emitter electrode 5a and the base electrode 7 made of a polycrystalline S1 layer are deposited to a thickness of about 0.04 μm and then photo-etched.
a shows the state in which the collector electrode 6a and gate electrodes 19a and 20a are formed.

(4) In FIG. 5(d), a photoresist film 13 is formed except for the NMO3 formation region, and
, ion implantation of 1 to 5 x 1013 cm-2 was performed to form n-
A state in which a mold offset region is formed is shown.

(5) In FIG. 5(e), after removing the resist film 13 in FIG. 5(d), a PSG film of 04 to 0.8 μm is deposited by the CVD method.
A state in which sidewall spacers 30 are formed on the side walls of each polycrystalline S1 electrode 5a, 6a, 7a, 19a, and 20a by performing etchback using the RIE method is shown.

(6) Next, as shown in FIG. 5(f), a photoresist film 13 is formed except for the emitter electrode formation region, collector electrode formation region, and NMO3 formation region, and using the sidewall spacer as a mask, 60 to 60% of As or P is formed. 1OOKe
The figure shows the state where ion implantation was performed at v, 5×10 16 to 1×10” cm −2 .

(7) Figure 5(g) shows the base electrode formation area and the PMO
A photoresist film 13 is formed except for the S formation region, and using the sidewall spacer as a mask, 30 to 6
0Kev, 1-5xlO” cml or BP, 80
This shows the state where ion implantation was performed at ~100Ke■, 1~5 x 10 "cm-".

The B1-CMOSIC device shown in FIG. 4 is obtained by carrying out the same process as described in FIG. 3(e).

As described above with reference to FIGS. 4 and 5, according to the present invention, a bipolar transistor having the above-mentioned effects,
CMOS elements (n-type in the case of NMOS, p-type in the case of PMO3) consisting of source/drain regions having the same polarity as the polarity of each gate electrode are arranged on the same substrate.

The result is a high-speed bipolar element and a high-speed short channel MOS with low resistance source/train regions and excellent subthreshold characteristics and hot electron resistance.
The elements can also be realized simultaneously on the same substrate. Therefore, B
It is planned to increase the speed of the entire i-CMO3 element. Furthermore, n+
Since the p+ type polycrystalline silicon layer and the p+ type polycrystalline silicon layer can be electrically connected through the metal silicide layer, it becomes possible to significantly increase the integration of the device.

In the above example, a PSG film was used as the sidewall spacer, but in addition to this, a 5iOa film, a boron phosphorus glass (BPSG) film, or a composite film such as a SiO□ film and a nitride (S i N) film may be used. You can. moreover,
Instead of the etch-back method, the sidewall spacers may be formed by thermal oxidation, etc. In addition to the lamp annealing described above, the heat treatment for silicidation is performed using
It can also be carried out by a heat treatment method at 00 to 1000°C for 20 to 40 minutes.

In the above-described embodiment, the collector electrode was formed from an nI type polycrystalline silicon layer, but there is no problem in using a metal layer such as aluminum instead.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

[Effects of the Invention] As described above, according to the semiconductor device of the present invention, the first base region and the second base region of the bipolar transistor are formed separately, and the impurity concentration of the external base region is lowered by the impurity concentration of the intrinsic base region. Since the impurity concentration can be made higher than the impurity concentration, the base resistance rb' can be lowered without causing a decrease in hrt, and the base region can be further lowered by forming a metal silicide layer on the surface of the base region and base electrode. , a high-speed operating element with excellent high frequency characteristics can be realized.

Furthermore, the emic electrode and the base electrode are made of the same polycrystalline S
Consisting of an i-layer, the diffusion layer for extending the electrode from the base region is positioned in a self-aligned manner by impurity diffusion from the polycrystalline Si layer, so it is necessary to consider mask overlay accuracy during the manufacturing process. Therefore, the element area of the transistor can be significantly reduced, and parasitic capacitance can be reduced. As a result, higher speed and higher density transistors can be achieved at the same time.

Further, since the wiring metal layer is formed in the shallow junction diffusion layer via the polycrystalline Si layer, a stable low contact resistance can be obtained, and the reliability of the device can be improved.

Furthermore, since the sidewall spacer is provided on the side wall of the polycrystalline silicon layer, the step difference is gentle, and the step coverage of the wiring layer formed thereon through the insulating layer is good, making the wiring layer resistant to electromagnetic waves. Reliability such as migration property and stress migration resistance is greatly improved.

Furthermore, since the manufacturing process is simple, it has the effect of enabling application to Bi-CMIS devices, etc., which are composite devices with CMOS.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention;
Figure 2 is a cross-sectional view showing a conventional semiconductor device, Figure 3 (a)
~(e) are cross-sectional views according to manufacturing steps of the semiconductor device shown in FIG. 1, and FIG. 4 is a B1-CMOS showing another embodiment of the present invention.
5A to 5G are cross-sectional views of the IC semiconductor device according to manufacturing steps of the semiconductor device shown in FIG. 1 ・ ・ 2 ・ 3 . . 4 . 2 Base region 4c...p1 type diffused 5...n++ polycrystalline S1 layer (emitter electrode) 6...n3 type polycrystalline S1 layer (collector electrode) 7...p+ Type polycrystalline Si layer (base electrode) 5a... Polycrystalline Si layer (emitter electrode) 6a...
・Polycrystalline Si layer (collector electrode) 7a...polycrystalline S
i-layer (base electrode) 8...n" type emic region 9...n+ type collector diffusion layer 10...p1 type channel stopper region (p" type buried layer) 11... ...Inter-element insulation isolation film (field oxidation l1
x) 12...SiO□ film 13...Photoresist film 14...As or P ion 15...16...16...17...18... l 9, 19a 20, 20a 2 l ・ ・ ・ ・ 22 ・ ・ ・ 22a ・ ・ ・ 23 ・ ・ ・ ・ 24 ・ ・ ・ ・ 25 ・ ・ ・ ・ 26 ・ ・ ・ ・ 27 ・ ・ ・ ・ 28 ・ ・・ ・ 30 ・ ・ ・ ・ 31 ・ ・ ・ ・B or BF2 ion・n type well・p type well・p“ type channel stopper layer・n++ polycrystalline Si gate electrode・p9 type polycrystalline Si gate electrode・gate oxide film・n++ source/drain region ・n-type offset region ・p++ source/drain region ・n++ polycrystalline Si electrode ・High resistance polycrystalline Si layer ・p++ polycrystalline Si electrode ・n+ type scattered layer p1 type diffused ・Side Wall spacer/metal silicide layer or above procedural amendment (method) Case description 1988 Patent Application No. 174121 2 Title of invention Semiconductor device 3゜Relationship with the amended person case Patent applicant ◎ 163 Tokyo 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236)
Seiko Epson Corporation Representative Director Nakamura
Kouya contact number 348-8531 extension 300-302

Claims (2)

[Claims] (1) a base region made of a first conductivity type impurity diffusion layer formed on a semiconductor substrate; an emitter region made of a second conductivity type impurity diffusion layer formed within the base region; an emitter electrode made of a polycrystalline silicon layer of a second conductivity type provided in the base region, and a polycrystalline silicon layer of the first conductivity type provided in the same layer as the polycrystalline silicon layer from the base region to the inter-element isolation region. A semiconductor device having a base electrode comprising: a sidewall spacer formed on the sidewalls of the emitter electrode and the base electrode; and a metal silicide layer formed on the surfaces of the emitter electrode, the base electrode and the base region. A semiconductor device comprising: (2) The semiconductor device according to claim 1, comprising: a bipolar transistor; and a first channel type M having a gate electrode made of a polycrystalline silicon layer of a first conductivity type and the same layer as the polycrystalline silicon layer.
a second channel type M having an OS transistor and a gate electrode made of a polycrystalline silicon layer of a second conductivity type that is the same layer as the polycrystalline silicon layer;
A semiconductor device including an OS transistor on the same semiconductor substrate, comprising: a sidewall spacer formed on a side wall of the gate electrode; and an impurity diffusion layer forming a source and drain region formed on the gate electrode and the semiconductor substrate. 1. A semiconductor device comprising: a metal silicide layer formed on a surface of the semiconductor device.