JPH10321730A - Semiconductor device and its manufacturing method and communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a bipolar transistor of a high current amplifying rate and high resistant-presure and a bipolar transistor which is capable of operating at a high speed on the same semiconductor substrate. SOLUTION: In an opening 7 of a silicon nitride film 6 provided on a surface of an N-type epitaxial layer 3, a bipolar transistor of a high-current amplifying rate and high resistant-pressure forming a base layer 18 of comparatively low concentration by ion implantation is formed. In addition, in an opening 14 of the silicon nitride film 6, a bipolar transistor capable of operating a high-speed formation of a base layer 15 of comparatively high concentration and shallow junction by epitaxial base technique is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of forming a bipolar transistor requiring a high current amplification factor and a high breakdown voltage and a bipolar transistor requiring a high-speed operation on the same semiconductor substrate, and a method of manufacturing the same. And a communication device including the semiconductor device.

[0002]

2. Description of the Related Art For example, a high-frequency bipolar transistor used for a frequency converter or the like of a communication device is required to operate at a high speed. In order to increase the speed of the bipolar transistor, it is important to shorten the base transit time and reduce the resistance of the base by making the base shallower.

However, in the method of forming a base by ion implantation, which has been widely used, it is difficult to make a shallow junction due to the problem of a channeling tail of an impurity concentration profile. When ions are implanted at a high concentration, there is also a problem that crystal defects occur due to damage caused by the ion implantation.

Therefore, an epitaxial base technique of forming a base layer of a bipolar transistor by an epitaxial technique makes it possible to form a base layer having a thickness of about 50 nm with high concentration and high precision, and to increase the speed of the bipolar transistor. It is attracting attention as a key technology. In fact, with this epitaxial base technology,
High-speed bipolar transistors having a maximum cutoff frequency exceeding 50 GHz have been realized.

[0005]

On the other hand, the performance required of the bipolar transistor is not only high-speed but also, for example, a bipolar transistor for electric power and a cathode ray tube (C).
There is a demand for a bipolar transistor used in a drive circuit such as a RT) to have a high current amplification factor, a high breakdown voltage, and the like.

At this time, the above-mentioned high concentration of the base layer is achieved by:
While this is an important technology for increasing the speed of a bipolar transistor, it also has the following disadvantages.

That is, (1) The current amplification factor β decreases due to the decrease in emitter injection efficiency, and the emitter accumulation time τ _e increases. (2) The electric field intensity increases due to the increase in the emitter-base junction concentration, and the emitter-base breakdown voltage BV _eb0 decreases.

Therefore, in applications requiring high current amplification factor (high β) and high withstand voltage (high BV _eb0 ), _{increasing the} concentration of the base layer is rather inappropriate. That is, the bipolar transistor for this purpose is preferably formed by a normal ion implantation method rather than the above-described epitaxial base technique.

However, conventionally, a technique has not been established in which the process of forming a bipolar transistor by the above-described epitaxial base technique and the process of forming a bipolar transistor by a normal ion implantation method are aligned in parallel with each other. It was extremely difficult to form them on the same chip.

As a result, conventionally, a circuit in which a bipolar transistor is required to have a high speed and a circuit in which a bipolar transistor is required to have a high current amplification factor and a high withstand voltage are formed on separate chips. For this reason, for example, a frequency conversion circuit or the like that requires high-speed operation,
When manufacturing a communication device including a drive circuit for a CRT, which requires a high withstand voltage, an input / output circuit for an external storage device, and the like, chips mounted with these circuits are individually incorporated into the device, or the distance between the chips is reduced. A step of connecting with wiring is required, which is inconvenient.

Therefore, an object of the present invention is to provide a semiconductor device in which a bipolar transistor having a high current amplification factor and a high withstand voltage by an ion implantation method and a bipolar transistor capable of operating at high speed by an epitaxial base technique are formed on the same semiconductor substrate. An object of the present invention is to provide a simple manufacturing method and a communication device including the semiconductor device.

[0012]

According to the present invention, there is provided a semiconductor device according to the present invention, wherein a first conductive type substrate surface portion of a semiconductor substrate is a collector and a second conductive type provided in a surface region of the substrate surface portion. A first bipolar transistor having a first diffusion layer of a base as a base and a second diffusion layer of a first conductivity type provided in a surface region of the first diffusion layer as an emitter; A second conductive type semiconductor epitaxial layer provided on the substrate surface portion, and a first conductive type semiconductor epitaxial layer provided on a surface region of the semiconductor epitaxial layer.
A second bipolar transistor having a conductive third diffusion layer as an emitter.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a first element forming region and a second element forming region on a first conductive type substrate surface of a semiconductor substrate, respectively; and forming a first element forming region and a second element forming region on the substrate surface including the first and second element forming regions. Forming a first insulating film; forming a first opening in the first insulating film at a predetermined position in the first element forming region; and forming the first surface of the substrate in the first opening. After forming a first conductive film on the first insulating film and on the first insulating film, the first conductive film is patterned, and in the first element forming region, a predetermined region including the first opening is formed. Leaving the first conductive film in a predetermined region in the second element forming region; and forming the first conductive film on the first conductive film and the second conductive film left in the first and second element forming regions, respectively. Forming a second insulating film on the first insulating film; and forming the first element forming region Forming a first through-hole penetrating the second insulating film and the first conductive film at a predetermined position in the first opening; and forming a first through-hole at a predetermined position in the second element formation region. Forming a second through-hole penetrating the second insulating film and the first conductive film; and forming the second through-hole exposed in the first through-hole at least in the first element formation region. The surface of the substrate surface and the first
Forming a third insulating film on a side surface of the conductive film, and etching the first insulating film through the second through-hole in the second element formation region to form a third insulating film on the first insulating film. Forming a second opening larger than the through-hole; and forming a semiconductor epitaxial layer containing a second conductivity type impurity on the surface of the substrate in the second opening in the second element formation region. Forming a layer;
In a state where the element formation region is masked, a second conductivity type impurity is introduced into the surface region of the substrate surface portion through the first through hole in the first element formation region to form the first through hole. Forming a first diffusion layer of a second conductivity type in a surface region of the substrate surface portion below the first and second substrates;
After forming a fourth insulating film on the entire surface of the second insulating film including the inside of the through hole, the fourth insulating film is anisotropically etched to form the first and second through holes. Leaving the fourth insulating film only on the side wall; and forming the fourth insulating film over the entire surface of the second insulating film including the inside of the first and second through holes left on the side wall. After forming a second conductive film containing an impurity of one conductivity type, the second conductive film is patterned to form the first and second through holes in the first and second element formation regions, respectively. Leaving the second conductive film in a region including: and diffusing a first conductivity type impurity from the second conductive film to form a first element forming region.
A second diffusion layer of a first conductivity type is formed in a surface region of the first diffusion layer below the second conductive film, and the second conductive film is formed in the second element formation region. Forming a third diffusion layer of the first conductivity type in a surface region of the semiconductor epitaxial layer below the third diffusion layer.

A semiconductor device according to another aspect of the present invention includes a first conductive type first substrate surface portion and a second conductive type second substrate type.
A first substrate surface portion of a semiconductor substrate having a first substrate surface portion and a first diffusion layer of a second conductivity type provided in a surface region of the first substrate surface portion;
A first bipolar transistor having a second diffusion layer of the first conductivity type provided as an emitter in a surface region of the first diffusion layer, a collector serving as the second substrate surface portion, and a A second bipolar transistor having a first conductive type semiconductor epitaxial layer provided as a base and a second conductive type third diffusion layer provided as an emitter in a surface region of the semiconductor epitaxial layer.

Further, in the communication device of the present invention, the first conductive type substrate surface portion of the semiconductor substrate is a collector, and the second conductive type first diffusion layer provided in the surface region of the substrate surface portion is a base. A first circuit including a first bipolar transistor having a first conductivity type second diffusion layer provided in a surface region of the first diffusion layer as an emitter; A second bipolar transistor having a second conductive type semiconductor epitaxial layer provided on the portion as a base and a first conductive type third diffusion layer provided in a surface region of the semiconductor epitaxial layer as an emitter. A second circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

[First Embodiment] First, FIGS.
The semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

In each of FIGS. 1 to 11, a region for forming a bipolar transistor having a high current amplification factor and a high withstand voltage is shown on the left side, and a region for forming a bipolar transistor capable of high-speed operation is shown on the right side. .

First, as shown in FIG. 1, an N ⁺ buried layer 2 is formed in a surface region of a P-type single-crystal silicon semiconductor substrate 1 by, for example, an ion implantation method. The epitaxial layer 3 is grown.

Next, for example, the N-type epitaxial layer 3 constituting the surface portion of the substrate is selectively thermally oxidized to form a field oxide film 4, thereby being relatively surrounded by the field oxide film 4. The formed element formation regions A and B are respectively formed. Further, an N ⁺ layer 5 for taking out the collector is formed in the N-type epitaxial layer 3 of each of the element formation regions A and B by, for example, an ion implantation method.

Thereafter, a silicon nitride film 6 having a thickness of about 100 nm is formed on the entire surface by, for example, a chemical vapor deposition (CVD) method. Instead of the silicon nitride film 6, for example, a stacked film of a silicon nitride film and a relatively thin silicon oxide film, a so-called NO composite film may be used.

Next, as shown in FIG. 2, an opening 7 is formed in the silicon nitride film 6 at a predetermined position in the element formation region A by photolithography and etching.

Next, as shown in FIG. 3, a polysilicon film 8 having a relatively high concentration of P-type impurities, for example, about 200 nm thick is formed on the entire surface by CVD, and then photolithography is performed. The polysilicon film 8 is patterned by dry etching to form a base layer of a bipolar transistor in a predetermined region including the opening 7 in the element formation region A and later in the element formation region B as shown in the drawing. The polysilicon films 8a and 8b are left in predetermined regions including the regions, respectively.

The introduction of the P-type impurity into the polysilicon film 8 may be performed simultaneously with the CVD, or may be performed by ion implantation after the film formation. For example, after film formation,
Acceleration energy about 20 KeV, dose 5 × 10 ¹⁵ /
By implanting boron (B) ions under the condition of about cm ² , the impurity concentration in the polysilicon film 8 is reduced to 1 × 10 ^20.
/ Cm ³ or more.

Next, as shown in FIG. 4, a silicon oxide film 9 having a thickness of, for example, about 300 nm is formed on the entire surface by the CVD method.

Next, the silicon oxide film 9 and the polysilicon films 8a and 8b are sequentially processed by photolithography and dry etching to form openings at predetermined positions thereof. That is, in the element forming region A, a through hole 10 penetrating the silicon oxide film 9 and the polysilicon film 8a is formed in the region of the opening 7 of the silicon nitride film 6, and the N-type epitaxial layer Expose 3 On the other hand, in the element formation region B, a through hole 11 penetrating through the silicon oxide film 9 and the polysilicon film 8b is formed in a region where a base layer of the bipolar transistor will be formed later. At this time, in the element formation region B, since the silicon nitride film 6 functions as an etching stopper when etching the polysilicon film 8b, the through holes 11 are formed.
Is formed through only the silicon oxide film 9 and the polysilicon film 8b on the silicon nitride film 6.

Next, as shown in FIG. 5, the side portion of the polysilicon film 8a exposed in the through hole 10, the surface portion of the N-type epitaxial layer 3, and the inside of the through hole 11 are exposed. The side portions of the polysilicon film 8b are each thermally oxidized, and the thickness is, for example, 10 to 30 nm.
Silicon oxide films 12 and 13 are formed. For example, when an insulating film is not provided on the side surface of the polysilicon film 8b in the element formation region B, the polysilicon film in the through hole 10 in the element formation region A is kept in a state where the element formation region B is masked. A silicon oxide film may be formed on the side surface 8a and the N-type epitaxial layer 3 by a CVD method.

Next, as shown in FIG. 6, the silicon nitride film 6 is wet-etched with, for example, a heated phosphoric acid solution through the through-holes 11 in the element formation region B. An opening 14 wider than that is formed. As described above, the opening 14 is formed in a self-aligned manner (self-alignment) with the through-hole 11 without requiring a mask process. During this wet etching,
The inside of the through hole 10 in the element formation region A is substantially not affected.

Next, as shown in FIG.
Through the through hole 11 and the opening 14, a P-type epitaxial base layer 15 is grown on the N-type epitaxial layer 3 exposed in the opening 14 by selective epitaxial technology.

For example, H ₂ / SiH ₂ Cl ₂ / HCL /
For example, using a mixed gas of GeH ₄ / B ₂ H ₆ ,
By performing epitaxial growth at 5 ° C. and 10 Torr, a P-type epitaxial base layer 15 made of SiGe containing boron (B) can be formed. It is preferable that the base layer contains Ge (germanium) from the viewpoint of the high speed of the bipolar transistor. However, by changing the composition of the above-mentioned mixed gas, the P-type epitaxial base of Si (silicon) alone can be used. It is of course possible to form layers.

By forming the opening 14 of the silicon nitride film 6 wider than the opening of the polysilicon film 8b formed by the through hole 11, the polysilicon film 8 in the opening 14 is formed.
In the gap between b and the N-type epitaxial layer 3, a crystal grows also from the lower surface of the polysilicon film 8b.
As a result, there is an effect that the P-type impurity diffuses from the polysilicon film 8b into the epitaxial base layer 15 and the crystallinity of the entire epitaxial base layer 15 is improved.

Further, the polysilicon film 8 on the inner surface of the through hole 11
Since the silicon oxide film 13 provided on the side surface b prevents epitaxial growth from the side surface of the polysilicon film 8b, the epitaxial base layer 15 grows substantially only from below. An epitaxial base layer 15 having good properties is formed. The insulating film on the side surface of the polysilicon film 8b is not always necessary.

During the epitaxial processing, the silicon oxide film 12 formed previously functions as a protective film in the through hole 10 in the element forming region A, so that the epitaxial layer does not grow.

Next, as shown in FIG.
Is covered with a photoresist 16, and in this state, a P-type impurity 17 such as boron (B) is ion-implanted over the entire surface. As a result, the P-type impurity 17 is introduced into the surface region of the N-type epitaxial layer 3 through the through hole 10 in the element formation region A. Then, thereafter, a heat treatment is performed to activate the P-type impurities 17 introduced into the surface region of the N-type epitaxial layer 3, thereby forming the through-hole 10 in the surface region of the N-type epitaxial layer 3 as shown in the figure. A substantially matched P-type base layer 18 is formed. The P-type impurity 17
The heat treatment for the activation may be also used, for example, as the heat treatment in the various CVD steps to be performed later.

At the time of this ion implantation, the silicon oxide film 1 previously formed on the surface of the N-type epitaxial layer 3 in the through hole 10 is formed.
2 functions as a buffer layer for ion implantation.
Damage due to ion implantation into the surface region of the type epitaxial layer 3 is reduced.

As described above, in the present embodiment, the base layer of the bipolar transistor in the element formation region A is formed by the ion implantation method, and the base layer of the bipolar transistor in the element formation region B is formed by the epitaxial technique. Therefore, a bipolar transistor having a high current amplification factor and a high withstand voltage and a high-speed bipolar transistor can be formed on the same substrate.

For example, in the element formation region B,
Bipolar transistors forming base layer with char technology
Due to the demand for high-speed, high-density and shallow junction
For example, a DC
Flow amplification factor h_FEBut at most several hundred, emitter-base
Inter-breakdown voltage BV_eb0However, while the maximum is about 5V,
Form a base layer by ion implantation in the element formation region A
In a bipolar transistor, for example, boron (B)
Ion implantation conditions were set at an acceleration voltage of 30 to 70 KeV,
1 × 10¹²~ 5 × 10¹³/ Cm^TwoControl in the range
By h _FEIn the range of 70 to 1500, BV_eb0To
It is possible to control each in the range of 4 to 15V.

The formation of the P-type base layer 18 in the element formation region A may be performed by, for example, thermal diffusion from a solid-phase diffusion source such as doped SiO ₂ or doped polysilicon or vapor-phase deposition other than the ion implantation method described above. Alternatively, the doping may be performed.

Next, as shown in FIG.
After the photoresist 16 is removed, the CVD method is used.
The silicon oxide film 1 is formed on the entire surface including the insides of the through holes 10 and 11.
9, silicon oxide film 19 is then anisotropically etched to leave side wall oxide film 19 only inside through holes 10 and 11, as shown. After the silicon oxide film 19 is formed, a heat treatment is performed to
9, the surface of the P-type epitaxial base layer 15 in the element formation region B may be oxidized. Thereby, the breakdown voltage of the high-speed bipolar transistor in the element formation region B is improved, and the quality of the silicon oxide film 19 formed by the CVD method is also improved.

At the time of the above-described anisotropic etching of the silicon oxide film 19, the silicon oxide film 12 formed on the surface of the N-type epitaxial layer 3 in the element formation region A is also partially removed, and as shown in FIG. In the opening surrounded by the sidewall oxide film 19, the surface of the N-type epitaxial layer 3 is exposed.

Next, as shown in FIG.
An N-type polysilicon film 20 is formed by CVD on the entire surface of the silicon oxide film 9 including the sidewall oxide film 19 in the substrate 11, and thereafter, the polysilicon film 20 is patterned by photolithography and etching. Then, as shown in the figure, emitter extraction electrodes 20a and 20b made of the polysilicon film 20 are formed in predetermined regions including the regions of the through holes 10 and 11, respectively. The introduction of the N-type impurity into the polysilicon film 20 may be performed simultaneously with the formation of the polysilicon film 20.
It may be performed by ion implantation after the film formation of 0.

Thereafter, a heat treatment is performed. In the element formation region A, N-type impurities are introduced from the emitter extraction electrode 20a to the surface region of the P-type base layer 18 formed in the surface region of the N-type epitaxial layer 3 therebelow. Spread that P
An N-type emitter region 21 is formed in the surface region of the base layer 18, and a P-type impurity is diffused from the polysilicon film 8a serving as a base extraction electrode to the surface region of the N-type epitaxial layer 3 therebelow. A P ⁺ external base region 22 for lowering the base connection resistance is formed in the surface region of the N-type epitaxial layer 3 around the base layer 18. On the other hand, in the element formation region B, the P-type epitaxial base layer 15
N-type impurities are diffused into the surface region of P-type epitaxial base layer 15 so that N-type
3 is formed, and a P-type impurity is diffused from the polysilicon film 8b serving as a base extraction electrode to a surface region of the P-type epitaxial base layer 15 therebelow.
In the surface region of the type epitaxial base layer 15, a higher concentration P ⁺ external base region 24 for lowering the base connection resistance is also formed.

The formation of the P ⁺ external base region 22 in the element formation region A may be performed before the formation of the P-type base layer 18.

Next, as shown in FIG. 11, a polysilicon film 8 serving as a base extraction electrode is formed at a predetermined position of the silicon oxide film 9 by photolithography and etching.
a, 8b are formed, and at the predetermined positions of the silicon oxide film 9 and the silicon nitride film 6, the through holes 2a reaching the N ⁺ layer 5 for taking out the collector are formed.
6a and 26b are formed.

Next, the through holes 25a, 25b, 2
A metal film made of aluminum (Al) or an Al-based alloy is formed on the entire surface so as to bury the electrodes 6a and 26b, and the metal film is patterned by photolithography and etching. Base electrodes 28a and 28b electrically connected to polysilicon films 8a and 8b through emitter electrodes 27a and 27b, through holes 25a and 25b, and N ⁺ layer 5 through through holes 26a and 26b. To be formed, respectively.

Through the above steps, a bipolar transistor having a high current amplification factor and a high withstand voltage in which the base layer 18 is formed by ion implantation in the element formation region A, and a base layer 15 in the element formation region B formed by the epitaxial technique. A high-speed bipolar transistor can be formed on the same silicon semiconductor substrate 1.

At this time, in the present embodiment, the openings 7 and 14 of the silicon nitride film 6 provided on the N-type epitaxial layer 3 which is the substrate surface portion are skillfully used, so that the base layer as described above is formed. Two types of bipolar transistors having different structures can be easily formed by processes having relatively good matching with each other.

In the first embodiment described above, the NPN-type bipolar transistor is formed in each of the element forming regions A and B. For example, one of the element forming regions A and B is formed on the substrate surface. Are formed in the N-well and the other is formed in the P-well, respectively, and the ion species of ion implantation into the polysilicon film 8 serving as a base take-out electrode and the polysilicon film 20 serving as an emitter take-out electrode are respectively defined in each region. By separately punching, it is possible to form an NPN-type bipolar transistor in one of the element forming regions A and B and a PNP-type bipolar transistor in the other. However,
Since the P-type conductivity type of the base layer has a higher operating speed, it is preferable that at least the bipolar transistor in the element formation region B requiring high-speed be an NPN type.

FIG. 16 shows an example of a communication apparatus having a circuit including each of the two types of bipolar transistors according to the first embodiment.

A high frequency signal of, for example, several hundred KHz to several GHz received by the antenna 101 is converted into an intermediate frequency by the frequency converter of the communication control circuit 102, and the signal processing circuit 10
In step 3, signal processing such as MPEG is performed. The information obtained as a result is stored in a memory 106 which is an external storage device such as a hard disk drive (HDD) or a floppy disk drive (FDD) via a memory input / output (I / O) circuit 104, or Display 10 such as CRT via driver circuit 105
7 is displayed. Also, for example, after information read from the memory 106 via the memory I / O circuit 104 is signal-processed by the signal processing circuit 103, the information is transmitted from the communication control circuit 102 via the antenna 101. The communication is not limited to the wireless communication as in this example, but may be, for example, a wired communication such as ISDN.

At this time, for example, a bipolar transistor used for a frequency converter or the like of the communication control circuit 102 is required to operate at a high speed to cope with a high-frequency signal, while a memory I / O circuit 104 and a display driver circuit 105 Bipolar transistors used for
High current amplification, high withstand voltage, etc. are required. It is to be noted that the signal processing circuit 103 is generally constituted by a MOS type element such as a MOS transistor.

According to the first embodiment described above, the MO
The communication control circuit 102, the memory I / O circuit 104, and the display driver circuit 105, including the signal processing circuit 103 composed of an S-type element, can all be mounted on one silicon semiconductor chip 100 (note that MO
The signal processing circuit 103 including the S-type element may be a separate chip. ). Therefore, the step of assembling the individual chips and the troublesome wiring step between the chips, which are necessary when they are mounted on separate chips, become unnecessary, and the manufacturing cost can be greatly reduced.

[Second Embodiment] Next, FIGS.
With reference to FIG. 5, a second embodiment of the present invention will be described.
In the second embodiment, portions corresponding to those in the above-described first embodiment are denoted by the same reference numerals as those in the above-described first embodiment.

As shown in FIG. 12, in the second embodiment, the steps up to FIG. 10 of the above-described first embodiment are performed. However, as shown in FIG. 12, the formation region of each of the emitter extraction electrodes 20a and 20b is set to be smaller than the formation region of the polysilicon films 8a and 8b serving as the base extraction electrodes.

Next, as shown in FIG. 13, the silicon oxide film 9 is anisotropically etched using the emitter extraction electrodes 20a and 20b as an etching mask to expose at least the surfaces of the polysilicon films 8a and 8b.

Next, as shown in FIG. 14, the exposed polysilicon films 8a and 8b and the emitter extraction electrode 2
On the entire surface including the surfaces 0a and 20b, for example, titanium (T
i), a high melting point metal film 30 of cobalt (Co), molybdenum (Mo), platinum (Pt) or the like is formed.

Next, as shown in FIG. 15, heat treatment is performed, and the refractory metal film 30 and the emitter extraction electrode 20 are formed.
a, 20b and the polysilicon films 8a, 8b are alloyed to silicide the emitter extraction electrodes 20a, 20b and the polysilicon films 8a, 8b, respectively. Thereafter, unnecessary portions of the refractory metal film 30 are removed, and as shown in the figure, silicide films 31a and 31b in which the emitter extraction electrodes 20a and 20b are silicided, and the polysilicon film 8a and
8b remains silicide films 32a and 32b which are silicided. Note that the polysilicon films 8a and 8b may have only a part of which is the silicide films 32a and 32b.

Further, the silicide films 31a, 31b, 32
Each of a and 32b may be a film having a so-called polycide structure in which only the surface portion is silicided.

Thereafter, although illustration is omitted, after an insulating film to be an interlayer film is formed again on the entire surface, a through hole is formed at a predetermined position of the interlayer insulating film, and an emitter, a base and a base are formed at the position of the through hole. Each electrode of the collector is formed.

In the second embodiment, the resistance can be reduced by siliciding the emitter extraction electrode and the base extraction electrode of each bipolar transistor. In particular, by lowering the resistance of the base extraction electrode, the base resistance is reduced, and the speed of each bipolar transistor is improved.

The silicidation step according to the second embodiment is a silicidation step at another location, for example, the silicidation of the surface of the contact portion of a polysilicon resistance element disclosed in Japanese Patent No. 270749. It can be performed simultaneously with the step and the like.

[0062]

According to the present invention, on the same semiconductor substrate,
For example, a first conductivity type substrate surface portion is provided as a collector, a second conductivity type first diffusion layer provided in a surface region of the substrate surface portion as a base, and provided in a surface region of the first diffusion layer. A first bipolar transistor having a first conductive type second diffusion layer as an emitter, and a collector of a first conductive type substrate surface portion and a second conductive type semiconductor provided on the substrate surface portion, for example; A second bipolar transistor can be formed based on the epitaxial layer and using, as an emitter, a third diffusion layer of the first conductivity type provided in a surface region of the semiconductor epitaxial layer.

Therefore, for example, a bipolar transistor having a high current amplification factor and a high withstand voltage for forming a base by an ion implantation method and a bipolar transistor capable of operating at a high speed for forming a base by an epitaxial base technique are formed on the same semiconductor substrate. Can be. As a result, a circuit including a bipolar transistor that requires a high current amplification factor and a high withstand voltage and a circuit including a bipolar transistor that requires a high-speed operation can be mounted on one semiconductor chip. Can be reduced in assembly cost, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a block diagram illustrating a configuration of a communication device to which the present invention has been applied.

[Explanation of symbols]

1. P-type silicon semiconductor substrate 2. N ⁺ buried layer
3 ... N-type epitaxial layer, 4 ... Field oxide film, 5
... N ⁺ layer (for taking out collector), 6 ... silicon nitride film, 7, 14 ... opening, 8a, 8b ... polysilicon film (base taking out electrode), 9 ... silicon oxide film, 10, 11
... Through holes, 12, 13 ... Silicon oxide film, 15 ... P-type epitaxial base layer, 18 ... P-type base layer, 19 ... Sidewall oxide film, 20a, 20b ... Emitter extraction electrode, 2
1, 23 ... N-type emitter region, 22, 24 ... P ⁺ external base region, 31a, 31b, 32a, 32b ... silicide film

Claims (18)

[Claims] A first conductive type substrate surface portion of a semiconductor substrate; and a second conductive type substrate provided in a surface region of the substrate surface portion.
A first bipolar transistor having a first diffusion layer of a conductivity type as a base and a second diffusion layer of a first conductivity type provided in a surface region of the first diffusion layer as an emitter; A collector, based on a semiconductor epitaxial layer of a second conductivity type provided on the surface of the substrate;
A second bipolar transistor having a third diffusion layer of a first conductivity type provided as an emitter in a surface region of the semiconductor epitaxial layer. 2. The semiconductor device according to claim 1, wherein an impurity concentration of said first diffusion layer is lower than an impurity concentration of said semiconductor epitaxial layer. 3. A first insulating film is provided on the surface of the substrate, and the first diffusion layer is provided on the surface of the substrate in a first opening provided in the first insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is provided in a surface region, and the semiconductor epitaxial layer is provided in a second opening provided in the first insulating film. 4. A first conductive film is provided on the surface of the substrate in the first opening and on at least the first insulating film around the first opening. A third opening is provided in the first conductive film in
4. A diffusion layer is provided in a surface region of the substrate surface portion substantially in alignment with the third opening.
3. The semiconductor device according to claim 1. 5. A fourth diffusion layer of a second conductivity type is provided in contact with the first diffusion layer in a surface region of the surface of the substrate below the first conductive film. Item 5. The semiconductor device according to item 4. 6. A second insulating film having a fourth opening substantially aligned with the third opening is provided on the first conductive film, and a second insulating film is provided on the third and fourth openings. A third insulating film is provided on the side wall, and an emitter extraction electrode electrically connected to the second diffusion layer through a fifth opening formed by being surrounded by the third insulating film. The semiconductor device according to claim 4, wherein the semiconductor device is provided on the third insulating film. 7. A second conductive film is provided on the first insulating film in a region including the second opening, and the second conductive film is provided on the second conductive film in a region of the second opening. 4. The semiconductor according to claim 3, wherein a sixth opening smaller than the first opening is provided, and the semiconductor epitaxial layer is provided in a continuous gap formed by the second opening and the sixth opening. apparatus. 8. The second opening on a side surface of the sixth opening.
The semiconductor device according to claim 7, wherein a fourth insulating film is provided on a surface of the conductive film. 9. The semiconductor device according to claim 7, wherein a fifth diffusion layer of a second conductivity type is provided in a surface region of said semiconductor epitaxial layer below said second conductive film. 10. A fifth insulating film having a seventh opening substantially aligned with the sixth opening is provided on the second conductive film, and a fifth insulating film is provided for the sixth and seventh openings. 6th on the side wall
And an emitter extraction electrode electrically connected to the third diffusion layer through an eighth opening formed by being surrounded by the sixth insulating film.
8. The semiconductor device according to claim 7, wherein said semiconductor device is provided on said insulating film. 11. A step of forming a first element formation region and a second element formation region on a first conductivity type substrate surface portion of a semiconductor substrate, respectively, wherein the step includes the first and second element formation regions. A step of forming a first insulating film on a substrate surface portion; a step of forming a first opening in the first insulating film at a predetermined position in the first element formation region; Forming a first conductive film on the substrate surface portion and on the first insulating film, and then patterning the first conductive film to form the first opening in the first element formation region. Leaving the first conductive film in the predetermined region in the second element forming region in a predetermined region including: the first conductive film remaining in the first and second element forming regions, respectively. Forming a second insulating film on the film and on the first insulating film; A first through-hole penetrating the second insulating film and the first conductive film at a predetermined position in the first opening in the first element formation region; The second insulating film and the first
Forming a second through-hole penetrating through the conductive film; and forming the first through-hole in at least the first element formation region.
Forming a third insulating film on the surface of the substrate surface exposed in the through hole and on the side surface of the first conductive film; and forming the second through hole in the second element formation region. Etching the first insulating film through the hole to form a second opening larger than the through hole in the first insulating film; and forming the second opening in the second element forming region. Forming a semiconductor epitaxial layer containing a second conductivity type impurity on the surface of the substrate; and forming the first epitaxial layer with the second element formation region masked.
In the element formation region, a second conductivity type impurity is introduced into the surface region of the substrate surface portion through the first through hole, and a second impurity is introduced into the surface region of the substrate surface portion below the first through hole. Forming a first diffusion layer of a conductivity type; and forming a fourth insulating film on the entire surface of the second insulating film including the inside of the first and second through holes. Anisotropically etching the insulating film to leave the fourth insulating film only on the side walls of the first and second through holes; and forming the first and second insulating films left on the side walls. After forming a second conductive film containing an impurity of the first conductivity type over the entire surface of the second insulating film including the inside of the second through hole, the second conductive film is patterned, The second conductive film remains in regions including the first and second through holes in the first and second element formation regions, respectively. In the first element forming region, the first conductive type impurity is diffused from the second conductive film to form a first conductive type impurity in a surface region of the first diffusion layer below the second conductive film. A second diffusion layer of a first conductivity type is formed, and a third diffusion layer of the first conductivity type is formed in a surface region of the semiconductor epitaxial layer below the second conductive film in the second element formation region. Forming a diffusion layer. 12. In the first and second element formation regions, the second conductive film is formed in a region narrower than a region where the first conductive film is formed, respectively. The second insulating film is anisotropically etched using the film as an etching mask, thereby exposing a portion of the first conductive film, and then exposing at least the exposed first conductive film.
Forming a metal film on the conductive film and on the second conductive film,
12. The method of manufacturing a semiconductor device according to claim 11, wherein heat treatment is performed to silicide at least a part of the first conductive film and the second conductive film. 13. A first conductivity type first substrate surface portion and a second conductivity type first substrate surface portion.
A first substrate surface portion of a semiconductor substrate having a conductive type second substrate surface portion; and a second conductive type first diffusion layer provided in a surface region of the first substrate surface portion. A base, a first bipolar transistor having a first conductive type second diffusion layer provided in a surface region of the first diffusion layer as an emitter, a second substrate surface portion as a collector, the second bipolar transistor as a second bipolar transistor, A second bipolar transistor having a first conductive type semiconductor epitaxial layer provided on a substrate surface portion as a base and a second conductive type third diffusion layer provided in a surface region of the semiconductor epitaxial layer as an emitter. And a semiconductor device having: 14. A semiconductor device comprising: a first conductive type substrate surface portion of a semiconductor substrate; a collector; a second conductive type first diffusion layer provided in a surface region of the substrate surface portion; A first circuit including a first bipolar transistor having a second diffusion layer of the first conductivity type provided in a surface region as an emitter, a collector provided on the substrate surface portion, and provided on the substrate surface portion; Based on a semiconductor epitaxial layer of the second conductivity type,
A second circuit including a second bipolar transistor having a third diffusion layer of a first conductivity type as an emitter provided in a surface region of the semiconductor epitaxial layer. 15. The communication device according to claim 14, wherein an impurity concentration of said first diffusion layer is lower than an impurity concentration of said semiconductor epitaxial layer. 16. The communication device according to claim 15, wherein said first circuit is an input / output circuit for an external storage device. 17. The communication device according to claim 15, wherein the first circuit is a drive circuit of a display device. 18. The communication device according to claim 15, wherein said second circuit is a communication control circuit.