JP5944648B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique that can stably reduce an interface state existing from an emitter region to a base region in a vertical bipolar transistor.

  As this type of prior art, for example, there is one disclosed in Patent Document 1. That is, Patent Document 1 discloses a bipolar transistor having a structure in which a base region is disposed so as to surround an emitter region, and a collector region is disposed so as to surround the base region. A bipolar transistor having such a structure is called a vertical type because current flows in the depth direction (longitudinal direction). In a vertical bipolar transistor, the emitter region, the base region, and the collector region have characteristics that they want to obtain by ion implantation of impurities or introduction of impurities in the process of epitaxial growth (ie, in-situ). The density is adjusted to match.

  As a typical characteristic of the bipolar transistor, there is a current amplification factor (β value or hFE). The β value is defined as collector current (IC) / base current (IB). The larger the β value, the larger the IC obtained for the same IB. From the viewpoint of power consumption, a bipolar transistor having a large β value is usually required. Further, from the viewpoint of circuit design and operation reliability, it is preferable that the variation in β value is small.

  Here, the reason why the β value is lowered and the variation of the β value is increased is that an interface state 314 exists from the emitter region 315 to the base region 313 as shown in FIG. Patent Document 2 describes that an interface state is reduced by terminating dangling bonds (that is, dangling bonds) existing on the surface of a silicon substrate with a hydrogen element.

JP 2004-179548 A Japanese Patent No. 2764766

Patent Document 1 describes that a dangling bond is terminated with a hydrogen element (hereinafter also simply referred to as hydrogen). However, the bonding force of hydrogen to silicon is weak. Further, hydrogen easily diffuses in the silicon oxide film. For this reason, the termination of dangling bonds by hydrogen is insufficient, and there is a problem that the reduction of the interface state is not stable.
Therefore, the present invention has been made in view of such circumstances, and in a vertical bipolar transistor, a semiconductor device capable of stably reducing the interface state existing from the emitter region to the base region And its manufacturing method.

In order to solve the above problems, a method of manufacturing a semiconductor device according to one embodiment of the present invention is a semiconductor device including a vertical bipolar transistor on a silicon substrate, and the bipolar transistor is formed on the silicon substrate. A first conductivity type base region; a second conductivity type emitter region formed on the silicon substrate and in contact with the base region; and a surface of the silicon substrate on a boundary between the base region and the emitter region A silicon oxide film formed on the silicon oxide film, and a silicon film formed on the silicon oxide film, wherein a chlorine element is 1 × 10 ¹⁷ cm ⁻³ or more at an interface between the silicon oxide film and the silicon substrate. It is present in a concentration.

  With such a configuration, the dangling bonds present at the boundary between the base region and the emitter region on the surface (that is, the interface) of the silicon substrate are terminated with a chlorine element (hereinafter also simply referred to as chlorine). can do. Thereby, the interface state existing from the emitter region to the base region can be reduced. In addition, chlorine has a stronger binding force to silicon than hydrogen and is difficult to diffuse. Further, the boundary portion is covered with a silicon film via a silicon oxide film. For this reason, after the silicon film is formed and the dangling bonds at the boundary are terminated with chlorine, the boundary is etched (for example, touched with a hydrofluoric acid solution or exposed to a plasma atmosphere). There is no such a thing, and it can suppress that a dangling bond is newly formed. In this manner, the state in which the dangling bond is terminated can be maintained, and the interface state can be prevented from changing in the increasing direction, so that the interface state can be stably reduced. As a result, it is possible to realize a vertical bipolar transistor having a large β value and a small variation in β value (that is, improved characteristics relating to current amplification factor). In the present invention, the “first conductivity type” is one of P type and N type, and the “second conductivity type” is the other of P type and N type. The “polysilicon film” corresponds to, for example, a polysilicon pattern 19 or a polysilicon film 19 ′ described later.

In the above semiconductor device, a chlorine element may be present in the silicon film at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more. In such a configuration, even in a manufacturing process after terminating the dangling bond and a use environment after completion, for example, from a silicon film containing a high concentration of chlorine element through a silicon oxide film, the above-mentioned It is possible to supply chlorine to the interface.

A semiconductor device according to another aspect of the present invention is a semiconductor device including a vertical bipolar transistor and a MOS transistor on the same silicon substrate, wherein the bipolar transistor is a first conductivity type formed on the silicon substrate. A base region, a second conductivity type emitter region formed on the silicon substrate and in contact with the base region, and a surface of the silicon substrate formed on a boundary between the base region and the emitter region A silicon oxide film; and a silicon film formed on the silicon oxide film. The MOS transistor includes a gate insulating film formed on the silicon substrate and a gate formed on the gate insulating film. An electrode, an interface between the silicon oxide film and the silicon substrate, and the gate insulating film and the silicon Each of the interface with the emission substrate, wherein the chlorine element is present at a concentration of at least 1 × 10 ¹⁷ cm ^-3.

  With such a configuration, the dangling bonds existing at the boundary between the base region and the emitter region on the surface of the silicon substrate can be terminated with chlorine, and the interface state existing from the emitter region to the base region can be terminated. Can be reduced. Therefore, similarly to the semiconductor device described above, it is possible to realize a vertical bipolar transistor having a large β value and a small variation in β value. Further, dangling bonds existing at the interface between the silicon substrate and the gate insulating film can also be terminated with chlorine. For this reason, an improvement effect can be expected for the characteristics of the MOS transistor which is sensitive to the interface state such as 1 / f noise. The “gate insulating film” of the present invention corresponds to, for example, a gate oxide film 97 described later.

  A method of manufacturing a semiconductor device according to still another aspect of the present invention is a method of manufacturing a semiconductor device in which a vertical bipolar transistor is formed on a silicon substrate, and a first conductivity type base region is formed on the silicon substrate. Forming a silicon oxide film on the silicon substrate on which the base region is formed; forming a silicon film on the silicon oxide film; and forming the silicon film and the silicon oxide film. The silicon substrate is subjected to a heat treatment in an atmosphere containing phosphorus oxychloride to introduce a chlorine element contained in the phosphorus oxychloride into an interface between the silicon oxide film and the silicon substrate; and And a step of partially etching the silicon film to form an opening, and the silicon substrate through the opening. The second conductivity type impurity is introduced into, characterized in that it comprises a step of forming an emitter region of the second conductivity type in contact with the base region in the silicon substrate.

  With such a manufacturing method, chlorine can be introduced into the surface of the silicon substrate and at the boundary between the base region and the emitter region. Then, the dangling bonds existing at the boundary can be terminated with the introduced chlorine. That is, the semiconductor device described above can be manufactured. Therefore, the interface state existing from the emitter region to the base region can be stably reduced. A vertical bipolar transistor having a large β value and a small variation in β value (that is, improved characteristics relating to current amplification factor) can be realized.

  According to the present invention, dangling bonds existing on the surface of the silicon substrate and at the boundary between the base region and the emitter region can be terminated with chlorine. Thereby, the interface state existing from the emitter region to the base region can be stably reduced. A vertical bipolar transistor having a large β value and a small variation in β value (that is, improved characteristics relating to current amplification factor) can be realized.

1 is a diagram illustrating a configuration example of a semiconductor device 100 according to a first embodiment. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 (part 1); FIG. 2 is a diagram illustrating a method for manufacturing the semiconductor device 100 (No. 2). FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device 100 (No. 3). FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device 100 (part 4); FIG. 5 is a diagram illustrating a method for manufacturing the semiconductor device 100 (part 5); FIG. 6 illustrates a method for manufacturing the semiconductor device 100 (No. 6). FIG. 7 shows a method for manufacturing the semiconductor device 100 (No. 7). The figure which shows the structural example of the semiconductor device 200 which concerns on 2nd Embodiment. FIG. 10 is a diagram illustrating another configuration example of the semiconductor device 100. The figure which shows the result of having actually measured and confirmed the distribution of chlorine. The figure which shows the result of having actually measured and confirmed distribution of (beta) value. The figure which shows the presence of the interface state in a prior art example.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, portions having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
(1) Configuration of First Embodiment (1.1) FIG. 1 is a sectional view showing a configuration example of a semiconductor device 100 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a silicon (Si) substrate 1, an element isolation film 3 locally formed on and near the surface of the silicon substrate 1, and an element isolation film 3 on the silicon substrate 1. A vertical bipolar transistor 10 formed in a region surrounded by (i.e., a region where elements are isolated), an interlayer insulating film 41 formed on the silicon substrate 1 and covering the element isolation film 3 and the bipolar transistor 10; Plug electrodes 43 a to 43 c for leading terminal regions (for example, a collector region 11, a base region 13, and an emitter region 15 described later) of the bipolar transistor 10 onto the interlayer insulating film 41, and the interlayer insulating film 41 are formed. Wirings 45a to 45c connected to the plug electrodes 43a to 43c, respectively.

The silicon substrate 1 is a single crystal bulk silicon substrate. Alternatively, the silicon substrate 1 may be a substrate obtained by epitaxially growing a single crystal silicon layer on a single crystal bulk silicon substrate.
The element isolation film 3 is a silicon oxide film (that is, a LOCOS film) formed by, for example, a LOCOS (local oxidation of silicon) method. Alternatively, the element isolation film 3 may be, for example, a structure in which an insulating film is embedded in a trench (ie, STI: shallow trench isolation).

  The bipolar transistor 10 is, for example, an NPN bipolar transistor, and is formed on the silicon substrate 1 with an N-type collector region 11 formed on the silicon substrate 1, and its side and bottom surfaces are in contact with the collector region 11 (that is, the collector region 11 A P-type base region 13 formed on the inside of the silicon substrate 1, and an emitter region 15 formed on the silicon substrate 1 so that side and bottom surfaces thereof are in contact with the base region 13 (that is, formed on the inside of the base region 13); Have The bipolar transistor 10 has an N-type collector contact region 12 and a P-type base contact region 14 formed on the silicon substrate 1. The collector contact region 12 is connected to the N-type collector region 11. The concentration of the N-type impurity in the collector contact region 12 (that is, the dopant having N-type polarity) is higher than the concentration of the N-type impurity in the collector region 11. The base contact region 14 is connected to the P-type base region 13. The concentration of the P-type impurity in the base contact region 14 (that is, the dopant having P-type polarity) is higher than the concentration of the P-type impurity in the base region 13.

The bipolar transistor 10 includes a silicon oxide film (SiO ₂ film) 17 formed on the surface of the silicon substrate 1 and a polysilicon film pattern (ie, polysilicon pattern) 19 formed on the silicon oxide film 17. And having. The silicon oxide film 17 is formed, for example, by thermally oxidizing the surface of the silicon substrate 1 (that is, a thermal oxide film), and has a thickness of 6.5 nm. The polysilicon pattern 19 is formed so as to cover the boundary portion 21 with the silicon oxide film 17 interposed therebetween. Here, the boundary portion 21 is the surface of the silicon substrate 1 and is a boundary between the base region 13 and the emitter region 15 and a portion in the vicinity thereof.

  The interlayer insulating film 41 is, for example, a silicon oxide film or a silicon nitride film, or a film in which these are stacked. Further, contact holes are provided on the collector region 11, the base region 13, and the emitter region 15 in the interlayer insulating film 41. The plug electrodes 43a to 43c are connected to the collector region 11, the base region 13, and the emitter region 15, respectively, in a state of being embedded in these contact holes. The plug electrodes 43a to 43c are made of tungsten, for example. The wirings 45a to 45c connected to the plug electrodes 43a to 43c are made of, for example, aluminum (Al) or an aluminum alloy in which copper (Cu) or silicon (Si) is added to Al.

By the way, the above-described polysilicon pattern 19 contains chlorine element (that is, chlorine) at a concentration of 1 × 10 ¹⁶ cm ⁻³ or more. Further, chlorine is present at a concentration of 1 × 10 ¹⁷ cm ⁻³ or more at the interface between the silicon oxide film 17 and the silicon substrate 1. As a result, the dangling bonds existing at the boundary portion 21 are terminated with chlorine, and the interface state existing from the emitter region 15 to the base region 13 can be reduced. Next, a method for manufacturing the semiconductor device 100 will be described.

(1.2) Manufacturing Method FIGS. 2 to 8 are cross-sectional views illustrating a method of manufacturing the semiconductor device 100 according to the first embodiment of the present invention. As shown in FIG. 2, first, an N-type collector region 11 is formed on the silicon substrate 1. For example, the collector region 11 is formed by ion-implanting N-type impurities into the silicon substrate 1 and performing a heat treatment (for example, annealing or thermal oxidation). Alternatively, the collector region 11 is formed by epitaxially growing N-type single crystal silicon on the surface of the silicon substrate 1. Note that the type, concentration, and the like of the N-type impurity contained in the collector region 11 can be set to arbitrary values according to the characteristics required for the bipolar transistor 10. As an example, the N-type impurity contained in the collector region 11 is phosphorus (P), and its concentration is about 2 × 10 ¹⁶ cm ⁻³ .

  Next, the element isolation film 3 is formed on the surface of the silicon substrate 1 by, for example, the LOCOS method. By this element isolation film 3, a region where a bipolar transistor is to be formed on the silicon substrate 1 is isolated from other regions of the silicon substrate 1. As described above, the element isolation film 3 may be STI. The element isolation film 3 can take any form on the assumption that it has a function of separating elements.

Next, as shown in FIG. 3, a resist pattern 51 is formed on the silicon substrate 1 so as to open a part of the collector region 11 and cover the other region. The resist pattern 51 is formed by a photolithography technique. Then, using this resist pattern 51 as a mask, P-type impurities are ion-implanted to form a P-type base region 13 on the silicon substrate 1. The ion implantation conditions are, for example, that the ion species is B ⁺ , the acceleration energy is about 125 keV, and the dose amount is about 5 × 10 ¹² cm ⁻² . After the ion implantation, the resist pattern 51 is removed by ashing, for example.

Next, as shown in FIG. 4, the surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film 17. As described above, the thickness of the silicon oxide film 17 is, for example, 6.5 nm. Note that the method of forming the silicon oxide film 17 is not limited to thermal oxidation, and may be, for example, a CVD (chemical vapor deposition) method.
Next, a polysilicon film 19 ′ is formed on the silicon oxide film 17. The thickness of the polysilicon film 19 ′ is, for example, 350 nm. The formation method of the polysilicon film 19 'is, for example, a CVD method. Since the surface of the silicon substrate 1 is covered with the silicon oxide film 17, the polysilicon film 19 ′ is formed while being insulated from the silicon substrate 1. For example, an amorphous silicon film may be formed on the silicon oxide film 17 instead of the polysilicon film 19 ′.

Next, as shown in FIG. 5, the silicon substrate 1 on which the polysilicon film 19 'has been formed is annealed in an atmosphere containing phosphorus oxychloride (POCl ₃ ). That is, POCl ₃ annealing is performed on the silicon substrate 1 after the polysilicon film 19 ′ is formed. The conditions for the POCl ₃ annealing are, for example, an annealing temperature of 870 ° C., an annealing processing time of 30 minutes, and a flow rate of POCl ₃ of about 150 mg / min. In this POCl ₃ annealing, chlorine contained in POCl ₃ is diffused to the silicon oxide film 17 side through the polysilicon film 19 ′, and the diffused chlorine is segregated at the interface between the silicon oxide film 17 and the silicon substrate 1. .

Next, the polysilicon film 19 ′ is partially etched to form a polysilicon pattern 19 as shown in FIG. The partial etching (that is, patterning) of the polysilicon film 19 ′ is performed by, for example, a photolithography technique and a dry etching technique.
Next, as shown in FIG. 7, a resist pattern 53 is formed on the silicon substrate 1 so as to cover a part of the P-type base region 13 and open above the other regions. The resist pattern 53 is formed by a photolithography technique. Then, using the resist pattern 53 as a mask, N-type impurities are ion-implanted to form an N-type emitter region 15 and a collector contact region 12 connected to the collector region 11 in the silicon substrate 1. The ion implantation conditions are, for example, that the ion species is arsenic (As ⁺ ), the acceleration energy is about 60 keV, and the dose amount is about 5 × 10 ¹⁵ cm ⁻² . After this ion implantation, the resist pattern 53 is removed by, for example, ashing.

Note that the N-type emitter region 15 and the collector contact region 12 may be formed by different doses or different acceleration energies as necessary. Thereby, a difference can be provided in the concentration of the N-type impurity in the emitter region 15 and the collector contact region 12 or the diffusion depth thereof.
In this ion implantation process, the polysilicon pattern 19 also functions as a mask. Therefore, on the surface of the silicon substrate 1, the boundary between the region where the N-type impurity is implanted and the region where the N-type impurity is not implanted is a position immediately below the edge of the polysilicon pattern 19. In the manufacturing process of the semiconductor device 100, after removing the resist pattern 53, heat treatment such as annealing or thermal oxidation is performed. N-type impurities diffuse in the silicon substrate 1 during the heat treatment. As a result, as shown in FIG. 7, the emitter region 15 is formed so as to enter a position immediately below the polysilicon pattern 19.

Next, as shown in FIG. 8, a resist pattern 55 is formed on the silicon substrate 1 so as to cover the N-type emitter region 15 and the collector contact region 12 and open above the other regions. The resist pattern 55 is formed by a photolithography technique. Then, using this resist pattern 55 as a mask, P-type impurities are ion-implanted to form a base contact region 14 connected to the P-type base region 13 in the silicon substrate 1. The ion implantation conditions are, for example, that the ion species is boron difluoride (BF ₂ ⁺ ), the acceleration energy is about 60 keV, and the dose is about 2.5 × 10 ¹⁵ cm ⁻² . After this ion implantation, the resist pattern 55 is removed by ashing, for example.

Next, heat treatment for activating the dopant is performed. The heat treatment conditions are, for example, a heat treatment temperature of 950 ° C. and a heat treatment time of about 1 minute. Thereafter, as shown in FIG. 1, an interlayer insulating film 41 is formed on the silicon substrate 1.
Further, the interlayer insulating film 41 is partially etched to form contact holes, and plug electrodes 43a to 43c are formed in the contact holes. Then, wirings 45a to 45c are formed on the interlayer insulating film 41 so as to be connected to the plug electrodes 43a to 43c. The bipolar transistor 10 is electrically connected to, for example, other elements by the wirings 45a to 45c. Thereby, the semiconductor device 100 shown in FIG. 1 is completed.

(1.3) Effects of the First Embodiment According to the first embodiment of the present invention, the silicon oxide film 17 is formed on the surface of the silicon substrate 1 and at least on the boundary portion 21 between the emitter region 15 and the base region 13. And a polysilicon pattern 19 are formed. Chlorine is segregated at the interface between the silicon oxide film 17 and the silicon substrate 1. Thereby, dangling bonds existing at the boundary portion 21 can be terminated with chlorine, and the interface state existing from the emitter region 15 to the base region 13 can be reduced.

  In addition, chlorine has a stronger binding force to silicon than hydrogen and is difficult to diffuse. Further, the boundary portion 21 is covered with the polysilicon pattern 19 through the silicon oxide film 17. For this reason, after the polysilicon pattern 19 is formed and the dangling bonds of the boundary portion 21 are terminated with chlorine (that is, after the step of FIG. 5), the boundary portion 21 is etched (for example, the boundary portion 21). Is not exposed to the hydrofluoric acid solution or exposed to the plasma atmosphere), and the formation of new dangling bonds can be suppressed. In this manner, the state in which the dangling bond is terminated can be maintained, and the interface state can be prevented from changing in the increasing direction, so that the interface state can be stably reduced. As a result, it is possible to realize a vertical bipolar transistor having a large β value and a small variation in β value (that is, improved characteristics relating to current amplification factor).

(2) Second Embodiment In the present invention, for example, the above-described vertical bipolar transistor 10 and other elements may be mixedly mounted on the same substrate. Examples of other elements include a resistance element, a capacitance element, or a MOS (metal oxide semiconductor) transistor. In the second embodiment, a case where MOS transistors are mixedly mounted as an example of an element will be described.

FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device 200 according to the second embodiment of the present invention. As shown in FIG. 9, the semiconductor device 200 is a bi-cimos (BiCMOS) type semiconductor device including a vertical bipolar transistor 10, an NMOS transistor 70, and a PMOS transistor 80 on the same silicon substrate 1.
As shown in FIG. 9, for example, a bipolar region and a CMOS region are prepared on the silicon substrate 1. In the bipolar region, for example, the vertical bipolar transistor 10 described in the first embodiment is formed. In the CMOS region, for example, an NMOS transistor 70 and a PMOS transistor 80 are formed. Hereinafter, the NMOS transistor 70 and the PMOS transistor 80 are collectively referred to as a CMOS transistor 90.

In the semiconductor device 200 shown in FIG. 9, in the bipolar region, chlorine is present at a concentration of, for example, 1 × 10 ¹⁷ cm ⁻³ or more at the interface between the silicon substrate 1 and the silicon oxide film 17. Thereby, dangling bonds existing at the boundary portion 21 of the bipolar transistor 10 can be terminated with chlorine, and the interface state existing from the emitter region 15 to the base region 13 can be stably reduced. Therefore, 2nd Embodiment has an effect similar to 1st Embodiment.

In addition to the effects of the first embodiment, the second embodiment has the following effects.
In the manufacturing process of the semiconductor device 200 shown in FIG. 9, a part of the process for forming the bipolar transistor 10 and the part for forming the CMOS transistor 90 are combined (that is, part of the process). Can be made common). That is, the silicon oxide film 17 is a film formed in order to insulate the polysilicon pattern 19 and the silicon substrate 1, and it is sufficient if it has an insulating property. Therefore, when the bipolar transistor 10 is incorporated in a CMOS process, the silicon oxide film 17 can be formed simultaneously with the gate oxide film 97 of the CMOS transistor 90. The polysilicon pattern 19 can also be formed simultaneously with the gate electrode 99 of the CMOS transistor 90.

  For example, in the step of forming the silicon oxide film 17 (see FIG. 4), the surface of the silicon substrate 1 is thermally oxidized not only in the bipolar region but also in the CMOS region. Thereby, the silicon oxide film 17 is formed in the bipolar region, and at the same time, the gate oxide film 97 is formed in the CMOS region. The gate oxide film 97 can be formed at the same time using the process of forming the silicon oxide film 17 in the bipolar transistor 10.

Further, in the step of forming the polysilicon film 19 ′ (see FIG. 4), the polysilicon film 19 ′ is formed on the gate oxide film 97 not only in the bipolar region but also in the CMOS region. The polysilicon film 19 'formed in the CMOS region is a material film for the gate electrode. Next, for example, in the POCl ₃ annealing (see FIG. 5) described above, the surface of the polysilicon film 19 ′ is exposed not only in the bipolar region but also in the CMOS region. POCl ₃ annealing is performed simultaneously in both the bipolar region and the CMOS region. Thereby, in both the bipolar region and the CMOS region, chlorine can be introduced into the polysilicon film 19 ′ and the resistance value can be reduced with phosphorus.

  Further, in the step of forming the polysilicon pattern 19 (see FIG. 6), the polysilicon film 19 ′ is patterned simultaneously not only in the bipolar region but also in the CMOS region. Thus, the polysilicon pattern 19 is formed in the bipolar region, and at the same time, the gate electrode 99 is formed in the CMOS region. Using the process of forming the polysilicon pattern 19 in the bipolar transistor 10, it is possible to simultaneously form the low-resistance gate electrode 99.

As described above, even when the bipolar transistor 10 and the CMOS transistor 90 are mixedly mounted on the same silicon substrate 1, a plurality of processes can be shared. Therefore, an increase in manufacturing cost of the semiconductor device can be suppressed.
In the above POCl ₃ annealing, chlorine is also implanted into the interface between the gate oxide film 97 of the CMOS transistor 90 and the silicon substrate 1. As a result, chlorine is present at a concentration of, for example, 1 × 10 ¹⁷ cm ⁻³ or more at the interface between the gate oxide film 97 and the silicon substrate 1. Thereby, dangling bonds present at the interface between the gate oxide film 97 and the silicon substrate 1 can also be terminated with chlorine. For this reason, an improvement effect can also be expected for MOSFET (MOS field effect transistor) characteristics sensitive to interface states such as 1 / f noise.

(3) Other Embodiments The semiconductor device 100 described in the first embodiment or the semiconductor device 200 described in the second embodiment has the N type replaced with the P type and the P type replaced with the N type. It may be a configuration. For example, as shown in FIG. 10, the bipolar transistor 10 may be a PNP bipolar transistor instead of NPN. Even with such a configuration, by performing POCl ₃ annealing, the β value can be increased and the variation in β value can be reduced.

  In the first and second embodiments, the silicon substrate 1 is a bulk single crystal silicon substrate, or the silicon substrate 1 is a substrate obtained by epitaxially growing a single crystal silicon layer on a bulk single crystal silicon substrate. The case where However, the silicon substrate of the present invention is not limited to any of the above. The silicon substrate of the present invention may be, for example, an SOI (silicon on insulator) substrate having a structure in which a silicon layer is disposed on an insulating layer. Even in such a case, by forming the bipolar transistor 10 in the silicon layer of the SOI substrate or by forming both the bipolar transistor 10 and the CMOS transistor 90, the first and second embodiments described above can be used. The same effect is produced.

(4) Confirmation Result Figure 11 effect, having been subjected to the POCl ₃ anneals (i.e., Embodiment) those not subjected to POCl ₃ anneal (i.e., Comparative Embodiment) For the concentration distribution of the chlorine by the SIMS analysis It is a figure which shows the result of having confirmed. The embodiment and the comparative embodiment are vertical NPN bipolar transistors formed under the same conditions except for the presence / absence of POCl ₃ annealing, and the structure thereof is as shown in FIG.

The horizontal axis in FIG. 11 indicates the depth from the polysilicon surface, and the vertical axis indicates the chlorine concentration. As shown in FIG. 11, it was confirmed that chlorine was segregated in the silicon oxide film 17 between the polysilicon pattern 19 and the silicon substrate 1 by performing POCl ₃ annealing. A portion of the chlorine segregated in the silicon oxide film 17 is also present at the interface between the silicon oxide film 17 and the silicon substrate 1, and the interface state is reduced by terminating the dangling bonds of silicon. . The reduction of the interface state was confirmed in FIG.

FIG. 12 is a diagram showing the results of confirming the β value distribution with the prototype wafer for the embodiment of the present invention and the comparative embodiment. The horizontal axis in FIG. 12 represents the β value, and the vertical axis represents the cumulative degree (%) of the number of measurement samples. Table 1 below shows the average value (ave.) And variation (σ) of the β values shown in FIG.
In FIG. 12, when the embodiment (with POCl ₃ annealing) is compared with the comparative embodiment (without POCl ₃ annealing), the embodiment has a larger β value and a smaller variation in the β value. More specifically, as shown in Table 1 below, the embodiment has a β value of about 1.4 times and a β value variation (σ / ave.) Of about 1/3 compared to the comparative embodiment. It was confirmed that the characteristics were realized.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation film 10 Bipolar transistor 11 Collector region 12 Collector contact region 13 Base region 14 Base contact region 15 Emitter region 17 Silicon oxide film 19 Polysilicon pattern 19 'Polysilicon film 21 Boundary portion 41 Interlayer insulating films 43a-43c Plug electrode 45a-45c Wiring 51, 53, 55 Resist pattern 70 NMOS transistor 80 PMOS transistor 90 CMOS transistor 97 Gate oxide film 99 Gate electrode 100, 200 Semiconductor device

Claims (1)

A method of manufacturing a semiconductor device in which a vertical bipolar transistor is formed on a silicon substrate,
Forming a first conductivity type base region on the silicon substrate;
Forming a silicon oxide film on the silicon substrate on which the base region is formed;
Forming a silicon film on the silicon oxide film;
The silicon substrate on which the silicon film and the silicon oxide film are formed is subjected to a heat treatment in an atmosphere containing phosphorus oxychloride so that the chlorine element contained in the phosphorus oxychloride is converted into the silicon oxide film and the silicon substrate. A process to be introduced at the interface with
After the heat treatment is performed, partially etching the silicon film to form an opening;
Introducing a second conductivity type impurity into the silicon substrate through the opening to form a second conductivity type emitter region in contact with the base region in the silicon substrate. Manufacturing method.

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