JPH0222410B2 - - Google Patents

Info

Publication number
JPH0222410B2
JPH0222410B2 JP58152479A JP15247983A JPH0222410B2 JP H0222410 B2 JPH0222410 B2 JP H0222410B2 JP 58152479 A JP58152479 A JP 58152479A JP 15247983 A JP15247983 A JP 15247983A JP H0222410 B2 JPH0222410 B2 JP H0222410B2
Authority
JP
Japan
Prior art keywords
memory
processor
ffc
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58152479A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6045837A (ja
Inventor
Hiroshi Nishimatsu
Toshiro Fukutomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP58152479A priority Critical patent/JPS6045837A/ja
Publication of JPS6045837A publication Critical patent/JPS6045837A/ja
Publication of JPH0222410B2 publication Critical patent/JPH0222410B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
JP58152479A 1983-08-23 1983-08-23 デ−タ転送回路 Granted JPS6045837A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58152479A JPS6045837A (ja) 1983-08-23 1983-08-23 デ−タ転送回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58152479A JPS6045837A (ja) 1983-08-23 1983-08-23 デ−タ転送回路

Publications (2)

Publication Number Publication Date
JPS6045837A JPS6045837A (ja) 1985-03-12
JPH0222410B2 true JPH0222410B2 (cg-RX-API-DMAC7.html) 1990-05-18

Family

ID=15541399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58152479A Granted JPS6045837A (ja) 1983-08-23 1983-08-23 デ−タ転送回路

Country Status (1)

Country Link
JP (1) JPS6045837A (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294680A (ja) * 1985-06-20 1986-12-25 Nec Corp Ｆｉｆｏメモリの読み出し回路
FR2607648B1 (fr) * 1986-11-28 1994-03-18 Hewlett Packard France Procede et dispositif de transmission rapide de donnees entre un emetteur et un recepteur par liaison serie standard

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203135A (en) * 1981-06-10 1982-12-13 Toshiba Corp Data transfer system

Also Published As

Publication number Publication date
JPS6045837A (ja) 1985-03-12

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