JPH02220444A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02220444A
JPH02220444A JP4069689A JP4069689A JPH02220444A JP H02220444 A JPH02220444 A JP H02220444A JP 4069689 A JP4069689 A JP 4069689A JP 4069689 A JP4069689 A JP 4069689A JP H02220444 A JPH02220444 A JP H02220444A
Authority
JP
Japan
Prior art keywords
emitter
silicon
bipolar transistor
window
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4069689A
Other languages
Japanese (ja)
Inventor
Takeshi Takaishi
高石 武史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4069689A priority Critical patent/JPH02220444A/en
Publication of JPH02220444A publication Critical patent/JPH02220444A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture a heterojunction transistor by a method wherein, after a bipolar transistor has been formed by an ordinary process, silicon ions are implanted into an emitter part. CONSTITUTION:SiO2 is formed on a silicon substrate 101; after that, a window for base use is opened; a mask 102 for ion implantation use is formed; boron ions are implanted; a base layer 103 is formed. Then, an SiO2 film 106 is formed again; after that, a window for emitter use is formed; a polycrystalline silicon film is formed; after that, an emitter 104 is formed. After that, a mask 105, for ion implantation use, in which a window has been opened in a part of the emitter is formed; silicon ions are implanted; the emitter of polycrystalline silicon is made amorphous; a wide-gap emitter is formed. Thereby, it is possible to form a heterojunction bipolar transistor whose amplification factor is high and whose high-frequency characteristics are good only by adding an ion- implantation process to an existing bipolar transistor process.

Description

【発明の詳細な説明】 [産業上の利用分11F] 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial use 11F] The present invention relates to a method for manufacturing a semiconductor device.

[従来の技術] ヘテロ接合バイポーラトランジスタのワイドギャップエ
ミッタの形成方法としては、従来ガリウムヒ素糸の半導
体を用いた場合には、主としてMBIC装置が用いられ
てきた。しかし、この方法では成膜速度が非常に遅く、
また、ガリウムヒ素を用いることによって、コストも高
く、製造技術が不完全なことから、工業生産性は低い。
[Prior Art] As a method for forming a wide gap emitter of a heterojunction bipolar transistor, an MBIC device has conventionally been mainly used when a gallium arsenide thread semiconductor is used. However, this method has a very slow film formation rate;
Furthermore, the use of gallium arsenide results in high costs and poor manufacturing technology, resulting in low industrial productivity.

そこで、現在最も製造技術の進んでいるシリコン系でヘ
テロ接合バイポーラトランジスタを作製しようという研
究が盛んである。この場合にワイドギャップエミッタの
形成方法としては、量産性に優れたプラズマOVD法が
よく用いられているワイドギャップエミッタの材料とし
ては非晶質(または微結晶)シリコンやシリコンと炭素
または酸素等の化合物が用いられている。
Therefore, there is active research into manufacturing heterojunction bipolar transistors using silicon, which is currently the most advanced in manufacturing technology. In this case, as a method for forming wide gap emitters, the plasma OVD method is often used due to its excellent mass production.The materials for wide gap emitters include amorphous (or microcrystalline) silicon, silicon and carbon or oxygen. compounds are used.

[発明が解決しようとする課題] このうち、シリコンを母体とする化合物については、組
成を変化させバンドギャップに傾斜構造を持たせること
は比較的容易であるが、電気伝導度が低いことからあま
り望ましくはない。
[Problems to be solved by the invention] Of these, it is relatively easy to change the composition of silicon-based compounds to give them a gradient structure in the band gap, but it is not very easy to make them have a gradient structure in the band gap due to their low electrical conductivity. Not desirable.

一方、ワイドギャップエミッタとして非晶質(または微
結晶)シリコンを用いた場合には、膜形成時にバンドギ
ャップに傾斜構造を持たせる場合には基板温度やガス流
量等を変化させれば良いがリンやボロン等の不純物の混
入量が変化して・しまう等の問題が起こり制御が難しい
On the other hand, when amorphous (or microcrystalline) silicon is used as a wide-gap emitter, if the bandgap has a sloped structure during film formation, it is possible to change the substrate temperature, gas flow rate, etc. This causes problems such as changes in the amount of impurities such as boron and other impurities, making it difficult to control.

[課題を解決するための手段] 本発明は半導体装置製造方法は、ワイドギャップエミッ
タを持つヘテロ接合トランジスタにおいて、イオン注入
によってエミッタを非晶質化する工程を含むことを特徴
とする。
[Means for Solving the Problems] According to the present invention, a semiconductor device manufacturing method is characterized in that, in a heterojunction transistor having a wide gap emitter, the method includes a step of making the emitter amorphous by ion implantation.

[実施例] 以下にその実施例に従って本発明を説明する。[Example] The present invention will be explained below according to the examples.

第1図は本発明を用いて、エミッタ・ペース接合を傾斜
接合にしたシリコンHBTを作製した実施例である。
FIG. 1 shows an example in which the present invention was used to fabricate a silicon HBT in which the emitter paste junction was a sloped junction.

ル型拳結晶シリコン基板101上に、熱酸化によって表
面に810.を形成した後、フォトエッチ工程でペース
用の窓を開はイオン打込み用のマスク102を形成し、
ボロンイオンを打込むことkよってベース層103を形
成する。(第1図(α)) 次に、スパッタ法を用いて
再びS10゜膜106を形成した後、フォトエッチ工程
によりエミッタ用の窓を形成し、減圧0/D法を用いて
ル型の多結晶シリコンを成膜した後、再びフォトエッチ
工程によってエミッタ104を形成する。
810. After forming, a window for the paste is opened in a photo-etching process and a mask 102 for ion implantation is formed.
A base layer 103 is formed by implanting boron ions. (Fig. 1 (α)) Next, after forming the S10° film 106 again using the sputtering method, a window for the emitter is formed using the photoetching process, and a rectangular multilayer film 106 is formed using the reduced pressure 0/D method. After forming a film of crystalline silicon, an emitter 104 is formed again by a photo-etching process.

(第1図(b)) ここまでの工程で、通常のnpn型
(ホモ接合)バイポーラトランジスタが形成される。こ
こで、フォトレジストでエミッタ部分に窓を開けたイオ
ン打込用マスク105を形成し、シリコンイオンを打込
み、多結晶シリコンのエミッタを非晶質化する。(第1
図(C)) 多結晶シリコンのバンドギャップは1.0
〜1.3θVと単結晶シリコン(,1,12eV)とほ
ぼ1等しい。
(FIG. 1(b)) Through the steps up to this point, a normal npn type (homojunction) bipolar transistor is formed. Here, an ion implantation mask 105 with a window in the emitter portion is formed using photoresist, and silicon ions are implanted to make the polycrystalline silicon emitter amorphous. (1st
Figure (C)) The band gap of polycrystalline silicon is 1.0
~1.3θV, which is almost equal to single crystal silicon (,1.12eV).

しかし、非晶質化することによってバンドギャップは1
.2〜2.OeVと広がり、ワイドギャップエミッタを
形成することができる。(第2図) 本発明を用いるこ
とによって、通常工程でバイポーラトランジスタを形成
した後、エミッタ部へのシリコンイオン打込みという工
程を付は加えるのみで、ヘテロ接合トランジスタを作製
することができる。また、シリコンイオンの打込み量及
び打込み速度によってバンドギャップ構造を変化させる
・ことができる。(時間的に変化させることによって任
意のバンドギャップ分布を得ることができる。)また、
本結晶シリコン上に非晶質シリコンを形成した場合には
接合面における界面単位が問題になるが、本実施例では
接合面は多結晶と単結晶となるので良好な接合特性を得
ることができる。
However, by becoming amorphous, the band gap becomes 1
.. 2-2. It can expand to OeV and form a wide gap emitter. (FIG. 2) By using the present invention, a heterojunction transistor can be manufactured by simply adding a step of implanting silicon ions into the emitter portion after forming a bipolar transistor in a normal process. Furthermore, the bandgap structure can be changed by changing the implantation amount and implantation speed of silicon ions. (Any bandgap distribution can be obtained by changing it over time.) Also,
When amorphous silicon is formed on this crystalline silicon, the interface unit at the bonding surface becomes a problem, but in this example, the bonding surface is polycrystalline and single crystal, so good bonding characteristics can be obtained. .

(接合部付近のシリコンの未結合手を水素または弗素等
で終端してやることKよって、さらに良好な接合界面が
実現される。) ここでは絶縁膜としてS10.を用いているが81Nx
や有機膜等を用いても良く、形成方法は熱酸化とスパッ
タ法の他にも、減圧OVD法等を用いても良い、また、
多結晶シリコンの形成方法も、プラズマQVD法、常圧
OVD法、スパッタ法等を用いても良い。またベース層
形成には熱拡散法等を用いても良く、不純物をヒ素等を
用いても良い。
(An even better bonding interface is achieved by terminating the dangling bonds of silicon near the bonding portion with hydrogen, fluorine, etc.) Here, S10. I am using 81Nx
or an organic film, etc., and in addition to thermal oxidation and sputtering, a low pressure OVD method or the like may also be used.
As a method for forming polycrystalline silicon, a plasma QVD method, an atmospheric pressure OVD method, a sputtering method, or the like may be used. Further, a thermal diffusion method or the like may be used to form the base layer, and arsenic or the like may be used as an impurity.

現在良(使われているエミッタ形成方法に、多結晶シリ
コン(第1図の104)からペース領域に不純物を熱拡
散させて薄いベース層を実現するウォッシュドエミッタ
法があるが、その場合にも本発明は有効であり、さらに
良好な接合界面を得ることができる。
A currently well-used emitter formation method is the washed emitter method, which creates a thin base layer by thermally diffusing impurities from polycrystalline silicon (104 in Figure 1) into the space region; The present invention is effective and can provide a better bonding interface.

また、この方法を用いると、B10MO8回路の製造工
程をほとんど変更することなしに(エミッタ501への
シリコンイオ・ン打込工程を加えるだけで)、さら忙高
速なHBT−0M09回路を作製することができる。(
第・3図) 以上、シリコンのnpn型バイボー2トランジスタの場
合を説明してきたが、他にもゲルマニウムやセレン等の
元素半導体や、sea等の化合物半導体の場合にも同様
に応用できる。もちろんpnp型でもかまわない。また
、半導体基板上の場合のみでなく、絶縁基板もしくは絶
縁層に形成されたバイポーラトランジスタにも応用でき
、もちろん三次元工0の構成要素として用いることもで
きる。
In addition, by using this method, a faster HBT-0M09 circuit can be fabricated without changing the manufacturing process of the B10MO8 circuit (just adding a silicon ion implantation process to the emitter 501). Can be done. (
(Figure 3) Although the case of a silicon npn type bibor 2 transistor has been described above, the present invention can be similarly applied to other elemental semiconductors such as germanium and selenium, and compound semiconductors such as sea. Of course, a pnp type may also be used. Moreover, it can be applied not only to a case on a semiconductor substrate but also to a bipolar transistor formed on an insulating substrate or an insulating layer, and of course can also be used as a component of a three-dimensional process.

[発明の効果] 以上述べたように、本発明の半導体装置製造方法を用い
ると、現在のバイポーラトランジスタ工程において、ト
ランジスタ完成後にエミッタ部にイオン注入を行う工程
を付加するだけで、高い増幅率と良好な高周波特性を持
った(高速な)へテロ接合バイポーラトランジスタを形
成することができる。
[Effects of the Invention] As described above, by using the semiconductor device manufacturing method of the present invention, a high amplification factor can be achieved in the current bipolar transistor process by simply adding a step of implanting ions into the emitter section after the transistor is completed. A heterojunction bipolar transistor with good high frequency characteristics (high speed) can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(α)(b)(C)は本発明を用いてnpn型へ
テロ接合バイポーラトランジスタを製作した実施例の工
程断面図。 第2図は、第1図のnpn型へテロ接合バイポーラトラ
ンジスタのバンド図及びイオン打込み量の図。 第5図は本発明を用いて810M0!9回路を製作した
実施例の断面図。 101・・・・・・・・・コレクタ 105・・・・・・・・・ペース ↓【↓ (a) (b) 第 図 4・・・・・・・・・エミッタ
FIGS. 1(α), (b), and (C) are process cross-sectional views of an embodiment in which an npn-type heterojunction bipolar transistor was manufactured using the present invention. FIG. 2 is a diagram of the band diagram and ion implantation amount of the npn type heterojunction bipolar transistor shown in FIG. 1. FIG. 5 is a sectional view of an embodiment of an 810M0!9 circuit manufactured using the present invention. 101... Collector 105... Pace ↓ [↓ (a) (b) Figure 4... Emitter

Claims (1)

【特許請求の範囲】[Claims]  ワイドギャップエミッタを持つヘテロ接合トランジス
タにおいて、イオン注入によってエミッタを非晶質化す
る工程を含むことを特徴とする半導体装置製造方法。
A method for manufacturing a semiconductor device, comprising a step of making the emitter amorphous by ion implantation in a heterojunction transistor having a wide gap emitter.
JP4069689A 1989-02-21 1989-02-21 Manufacture of semiconductor device Pending JPH02220444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4069689A JPH02220444A (en) 1989-02-21 1989-02-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4069689A JPH02220444A (en) 1989-02-21 1989-02-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02220444A true JPH02220444A (en) 1990-09-03

Family

ID=12587722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4069689A Pending JPH02220444A (en) 1989-02-21 1989-02-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02220444A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590279A (en) * 1991-03-21 1993-04-09 Philips Gloeilampenfab:Nv Manufacture of semiconductor device
EP1282158A1 (en) * 2001-07-31 2003-02-05 STMicroelectronics S.A. Method of manufacturing a bipolar transistor in an integrated CMOS circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590279A (en) * 1991-03-21 1993-04-09 Philips Gloeilampenfab:Nv Manufacture of semiconductor device
EP1282158A1 (en) * 2001-07-31 2003-02-05 STMicroelectronics S.A. Method of manufacturing a bipolar transistor in an integrated CMOS circuit
FR2828331A1 (en) * 2001-07-31 2003-02-07 St Microelectronics Sa METHOD FOR MANUFACTURING BIPOLAR TRANSISTOR IN A CMOS INTEGRATED CIRCUIT
US6756279B2 (en) 2001-07-31 2004-06-29 Stmicroelectronics S.A. Method for manufacturing a bipolar transistor in a CMOS integrated circuit

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