JPH02220291A - Bubble file storage - Google Patents

Abstract

PURPOSE:To increase the number of bubble memories driven in parallel to realize high-speed data transfer and a large capacity by arranging while data to a data array to be written in respective bubble memory blocks in serial. CONSTITUTION:Error detection information is added to external input data Din, and error of external output data Dout is detected 11 at the time of read- out, and respective data and bubble memory means BM0 to BMn are controlled 12. Further, input data are rearranged to the data array to be supplied to respective memory means in serial at the time of data write by a data array rearranging means 13 and the read-out data array is rearranged to the data array of input data at the time of reading out data from memory means.

Description

[Detailed Description of the Invention] (Summary) Regarding a bubble file storage device, especially a device that drives multiple bubble memory blocks in parallel and performs an error check when data is continuously output, even if the number of parallel drives increases, the current Error detection means for detecting and correcting 2-pin hard errors, etc. by using the error detection means; an error detection means for adding error detection information to external input data and detecting errors in external output data when reading;
In a bubble file storage device comprising a data input/output control means for controlling the input/output of external input/output data, and a plurality of bubble memory means connected to the data input/output control means, the bubble memory means and the data A data string recombination means is provided between the input/output control means, and during data writing, the data string recombination means converts a data array of external human input data into a data array that serially supplies the external input data to each bubble memory means. and when reading data from each of the bubble memory means, the read data array is rearranged into the data array of the external input data.

[Industrial Application Field] The present invention relates to a bubble file storage device, and more specifically, to a device that drives a plurality of bubble memory blocks in parallel and performs an error check when reading data.

BACKGROUND ART In recent years, bubble file storage devices have been used that have excellent environmental resistance, have no mechanically moving parts, and are nonvolatile. Bubble file storage devices use parallel drive technology to increase the amount of data access per unit time.

By the way, there are two types of data error modes for read data errors.

The first type is a soft error mode in which the data inside the bubble memory element is normal, but the data changes when read out to the outside, or the data changes due to an error in reading. Since the data is normal, correct data can be obtained by rereading the same location.

The second is a hard error mode caused by a change in the data inside the bubble memory element. In this case, the FCC (error correction code) correction function corrects the read error data and transfers it to the host.
Write the correct data to the bubble memory again. This hard error can also occur when bubbles are not transferred normally within the minor loop on the bubble memory chip, causing bit shifts in the page direction, or when bubbles move between physically adjacent loops, causing the same There are cases where an error of 2 or more bits occurs within the page.

The former hard error is limited to a specific minor loop where the error occurs, so the output data string contains only a 1-bit error, but the latter hard error results in a 2-bit or more error. As the number of parallel drives increases, the error bit interval also increases accordingly.

The longer the error bit interval, the greater the detection capability of the ECC circuit that detects errors in successive data is required. For this reason, if the detection ability of the ECC circuit is kept constant, there is a problem in that the number of parallel drives cannot be increased and it is not possible to speed up the write/successive processing.

Therefore, there is a need for a device that can detect and correct hard errors, etc., without increasing the detection capability of the ECC circuit even if the number of parallel drives is increased.

[Conventional technology]

FIG. 6.7 is an explanatory diagram of a conventional example.

FIGS. 6(a) and 6(b) are explanatory diagrams of a conventional bubble file storage device, and FIG. 6(a) shows its configuration.

In Figure (a), the bubble file storage device has error check circuits 1. It consists of a data output buffer circuit 2 and a plurality of bubble memory blocks BMO to BM7. Also, one bubble memory block BMO is a function driver 3. Bubble memory element 4. It consists of 5 sense amplifiers.

FIG. 4B shows write data of bubble memory blocks BMO to BM7.

In the figure, DW is write data, which is 8 pins x 512 bytes (8 bits transferred on the data bus).
This is data for one page (00 byte → IFF byte).

The write operation is first performed by the error check circuit 1, for example, 1 byte (8 bits) x 512 bytes l bar 2.
An error corrector code ECC is added to the external input data Din for the minute. Next, the write data DW is sent to each bubble memory block BMO-BM7 via the data output buffer circuit 2 and the function driver/driver circuit 3 of each bubble memory block BMO-BM7.
One bit at a time is written into each bubble memory element 4 at the same time.

In addition, in the read operation, first, the read data DR of the page address specified by the host computer is read one pin at a time by the sense amplifier 5 of each bubble memory block BMO to BM7. 1 byte x 512 for error check circuit 1
Read data DR for one page of bytes is output as external output data DouL. This data arrangement is shown in FIG.

When an ECC error is detected, the error check circuit 1 corrects the successive data and writes the corrected data at the same location as the read page address. Then, the external output data Dout is transferred to the host computer.

FIG. 7 is a diagram illustrating problems related to the conventional example.
The data arrangement of read data DR in the case of parallel driving is shown.

In the figure, EBI and EB2 are error bits that occur in data DR1 read from bubble memory blocks BMO to BM7, that is, external output data Dout of 00 bytes to IFF (hexadecimal) bytes.

The error bit EBI indicates that an error has occurred in the data read from the IFD-th minor loop of the bubble memory block BM2. Similarly, error bif FEB2
An error has occurred in the data read from the IFE-th minor loop adjacent to the IFD-th minor loop of the bubble memory block BM2.

(Problem to be solved by the invention) By the way, according to the conventional example, each bubble memory block B
Parallel driving is performed to simultaneously write data to the MO-BM 7 to speed up data transfer. At this time, in one bubble memory block BM2, the influence of hard errors etc. caused by magnetic bubble exchange between mutually adjacent minor loops affects the data arrangement of successive data DR as shown in FIG. Appears in bytes like this.

Therefore, in 8-parallel drive, if an error occurs due to the above mode, the interval between error bits will be 8 bits or more, and if you try to increase the number of parallel drives, the interval will become even wider. .

Suppose that the error detection and correction function of the error check circuit l is set to 1.
If it is about 6 bits, it will be sufficient to handle 8 parallel drives. However, if, for example, 64-parallel drive is implemented with the current write data array, an error bit will occur every 8 bytes, so the error detection and correction function of the error detection means is approximately 128 bits, which is eight times that of 8-parallel drive. Is required.

As a result, when using the current error detection circuit whose error detection function is limited to the error bit interval to increase the number of parallel drives and speed up data transfer, depending on the error mode that occurs, the data There is a problem in that it may not be possible to make corrections.

The present invention was created in view of the problems of the conventional example, and even if the number of parallel drives is increased, it is possible to detect and correct 2-focus hard errors using the current error detection means. The purpose is to provide a bubble file storage device that makes it possible.

[Means to solve the problem]

FIG. 1 shows a principle diagram of the bubble file storage device of the present invention.

The device includes an error detection means 11 that adds error detection information to external input data Din and detects errors in external output data Dout during reading, and a data input/output unit that controls input/output of the external input/output data Din and Dout. In a bubble file storage device comprising a control means 12 and a plurality of bubble memory means BM0 to BMn connected to the data input/output control means 12, the bubble memory means B
A data string recombination means 13 is provided between M0 to BMn and the data input/output control means 12, and during data writing, the data string recombination means 13 changes the data array of external input data Din to each bubble memory means BMi. The above object is achieved by rearranging the external input data Din into a data array that is serially supplied each time, and rearranging each bubble memory means BMi column into the data array of the external input data Din.

[Effect]

According to the invention, bubble memory means BM0 to BMn;
Data recombination means 1 is connected to data input/output control means 12.
3 is provided.

For this reason, for example, when the external input data Din is 8-bit transfer, each minor loop of one bubble memory means BMi has the first bit of the byte of the write data and the bit of the other byte, as in the past. The first bits are no longer written adjacently, and the first, second, . . . , eighth bits of the byte can always be written serially and consecutively.

/ As a result, between the minor loops of each bubble memory means 13, 2 errors caused by start/stop errors, etc.
Even if a bit hard error occurs, the error bits causing the hard error can always be detected adjacent to each other in the read data. Therefore, even if the number of parallel drives is increased, it is possible to utilize the error detection and correction functions of the conventional error detection means.

[Example] Next, an example of the present invention will be described with reference to the drawings.

2 to 5 are diagrams for explaining a bubble file storage device according to an embodiment of the present invention, and FIG. 2 shows a block diagram of the bubble file storage device according to an embodiment of the present invention.

In the figure, 21 is an ECC circuit which is one embodiment of the error detection means 11. The ECC circuit 21 adds an error detection code to the external manual data Din when writing data, and performs 1. When reading data, errors are detected, and if there is an error bit, the error bit is corrected. In the embodiment of the present invention, an ECC circuit having the same error detection and correction functions as the conventional one is used.

22 is a data input/output buffer circuit, which controls the input/output of external input/output data Din and Dout.
For example, the external input data Din is temporarily stored in a RAM or the like.

Reference numeral 13 denotes a data string recombination means, which is a portion surrounded by a dashed line in FIG. The data string recombination means 13 includes write shift registers 31, 331-333, 341-
343. Bank selector 32 and shift registers 37, 351 to 353 . It consists of a bank selector 36.

The shift register 31 sends external input data DSn from the data input/output buffer circuit 22 to the bank selector 32 in response to the defective loop control signal BL. The bank selector 32 selects one of the eight bubble memory blocks BMO to BM7 when performing 8-parallel driving, for example.

Shift registers 331 to 333 are used for each bubble memory drive p.
It is provided for each block BMO-BM7 and temporarily registers external input data Din necessary for writing them using the clock signal φl.

Shift registers 341 to 343 are similarly provided for each bubble memory block BMO-BM7, and convert, for example, one page worth of write data DW to be written into bubble memory block BMO into a serial data array using clock signal φ2. It is something.

Shift registers 351 to 352 are provided for each bubble memory block BMO-BM7, and are used to temporarily register successive data DR. Bank selector 36
has the same function as the bank selector 32 described above.

The shift register 37 is connected to the previous shift register 31
As shown in '1, external output data Dout is sent to the human output buffer circuit 22 by the defective loop control B signal BL.

BMO-8M7 surrounded by a broken line is a bubble memory block, and is composed of funxylan driver circuits 231-233, bubble memory elements 241-243, and sense amplifier circuits 251-253 provided for each block.

The funxylan driver circuits 231 to 233 send out write data DW in a serial data array to the major loop. If one page is 8 bits x 512 bytes, the bubble memory elements 241 to 242 are composed of 512 minor loops into which write data DW is written, a spare loop, and the like. Sense amplifier circuit 2
51 to 253 convert analog signals output as read data DR from the bubble memory elements 241 to 243 into digital signals.

FIG. 3 is an explanatory diagram of the data recombination means of the embodiment of the present invention, and shows the case of 8-parallel drive to facilitate comparison with the conventional example.

Here, it is assumed that the external input data Din is 8-bit transferred from the host computer as in the conventional case.

Also, the write data for one page is 8 bits x 512 bytes, as in the conventional case.

Under these conditions, the write data DW set in the shift registers 341 to 343 of the data recombination means 13 at the time of writing is as follows.

That is, write data DWI arranged in serial data of 00 to 3F (hexadecimal) bytes is set in the write register 341 of the bubble memory block BMO. Similarly, write data DW2 of 40 to 7E bytes of serial data is set in the write register 342 of the bubble memory block BMI. In this way, the write data DW8 to be supplied to the bubble memory block BM7 is set, and the write process is performed simultaneously for eight blocks one bit at a time according to the timing of the clock signal φ2.

FIGS. 4(a) and 4(b) are diagrams comparing the data array of the embodiment of the present invention and the data array of the conventional example.

FIG. 6A shows a data arrangement of write data DW of the bubble file storage device according to the conventional example of FIG.

With this data arrangement, when write data DW is written to the minor loop of bubble memory block BM2,
For example, write bits adjacent to bit 2 of the OL byte are bit 2 of the OO byte and bit 2 of the 02 byte.

FIG. 5B shows write data DW according to the serial data array according to the embodiment of the present invention.

Write data DW in such a serial data array,
When writing to the minor loop of the bubble memory block BMO, bits O to IFF from 00 byte to 3F byte are always lined up consecutively.

FIGS. 5(a) and 5(b) are explanatory diagrams of an ECC circuit according to an embodiment of the present invention.

Figure (a) shows the external output data Dout input from the data output buffer circuit 22 to the ECC circuit 21 when data is continuously transferred when data transfer is 8 bits as in the conventional case.
It shows.

In the figure, EBI and EB2 are error bits, which are caused by some reason in the bubble memory element 2 as in the conventional example.
43, and this occurs as an error bit in the read data DR.

This is an error bit that occurred in bit 2 and bit 3 of the IFD byte, and when viewed from the minor loop of the bubble memory element, these are the 491st and 49th grains that are adjacent to each other.
The second write data DW is the one that caused the error.

FIG. 4B shows a case where the error bits FBI and EB2 span two bytes.

This is an error bit that occurs in bit 7 of the IFD byte and bit 0 of the IFB byte, and when viewed in the minor loop of the bubble memory element, the 496th bit adjacent to each other
The error occurred in the write data DW of the wood grain and the 497th wood grain.

As a result, the error bits that occur in bubble memory blocks BMO to BM7 are always located next to each other, and there is no possibility that they span more than two bytes.
C circuit 21 error detection.

The burden of correction processing is reduced.

In this way, bubble memory blocks BMO to BM7
and the data input/output buffer circuit 22, there are shift registers 31, 37, 331-333°341-343.
, 351 to 353 and a bank selector circuit 36.

Therefore, when the transfer data of the external input data Din is 8 bits, each minor loop of one bubble memory block BMO has bit 1 of the 00 byte and bit 1 of the 01 byte adjacent to each other, as in the past. The write data bits O to IFF of 00 to 3F bytes can always be written serially and continuously.

As a result, even if a 2-bit hard error occurs between the minor loops of each bubble memory block BMO to BM7 due to a start/stop error, etc., the error bit EBI that caused the hard error will be stored in the successive data DR.
, EB2, always mutually adjacent bits 491
, 492 and bits 496 and 497 as FCC circuit 2
1 can be used for detection. Therefore, even if the number of parallel drives is changed from, for example, 8 parallel drives to 64 parallel drives, it is possible to utilize the error detection and correction functions of the conventional error detection means of about 16 bits.

〔Effect of the invention〕

As explained above, according to the present invention, by arranging the write data of a bubble memory block into a data array that is written serially for each bubble memory block, error bits generated in the bubble memory block are treated as read data. They can be found in positions adjacent to each other.

Therefore, even if the number of parallel drives is increased, there is no need to increase the error detection and correction functions of the error detection means.

This allows for an increase in the number of parallel drives.
It becomes possible to produce high-speed data transfer and large-capacity bubble file storage devices.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of a bubble file storage device of the present invention, Fig. 2 is a block diagram of a bubble file storage device of an embodiment of the invention, and Fig. 3 is a data string of an embodiment of the invention. FIGS. 4(a) and 4(b) are explanatory diagrams relating to the recombination means, and FIG. 5(a) is a diagram comparing the data arrangement of the embodiment of the present invention and the data arrangement of the conventional example
, (b) are explanatory diagrams related to the ECC circuit of the embodiment of the present invention, FIG. 6<a), (b) are block diagrams related to the bubble file storage device of the conventional example, and FIG. FIG. (Explanation of symbols) 11...Error detection means, 12...Data input/output control means, 13...Data string recombination means, BMO, BMi, BMn...Bubble memory means, Di
n...External input data, Dout...External output data.

Claims (1)

[Claims] Adding error detection information to external input data (Din),
an error detection means (11) for detecting an error in external output data (Dout) during reading; a data input/output control means (12) for controlling input/output of the external input/output data (Din, Dout); In a bubble file storage device comprising a plurality of bubble memory means (BM0 to BMn) connected to an output control means (12), between the bubble memory means (BM0 to BMn) and the data input/output control means (12). Data string recombination means (1
3), and the data string rearranging means (13) changes the data array of external input data (Din) for each bubble memory means (BMI) at the time of data writing.
) into a data array that is serially supplied, and when reading data from each bubble memory means (BMi), the read data array is rearranged into a data array of the external input data (Din). Bubble file storage.