JPH0221694B2 - - Google Patents
Info
- Publication number
- JPH0221694B2 JPH0221694B2 JP57123023A JP12302382A JPH0221694B2 JP H0221694 B2 JPH0221694 B2 JP H0221694B2 JP 57123023 A JP57123023 A JP 57123023A JP 12302382 A JP12302382 A JP 12302382A JP H0221694 B2 JPH0221694 B2 JP H0221694B2
- Authority
- JP
- Japan
- Prior art keywords
- write
- pulse
- delay time
- ram
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 claims description 80
- 230000003111 delayed effect Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57123023A JPS5915323A (ja) | 1982-07-16 | 1982-07-16 | パルス遅延方法及び装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57123023A JPS5915323A (ja) | 1982-07-16 | 1982-07-16 | パルス遅延方法及び装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5915323A JPS5915323A (ja) | 1984-01-26 |
JPH0221694B2 true JPH0221694B2 (enrdf_load_stackoverflow) | 1990-05-15 |
Family
ID=14850303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57123023A Granted JPS5915323A (ja) | 1982-07-16 | 1982-07-16 | パルス遅延方法及び装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5915323A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61163437U (enrdf_load_stackoverflow) * | 1985-03-30 | 1986-10-09 |
-
1982
- 1982-07-16 JP JP57123023A patent/JPS5915323A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5915323A (ja) | 1984-01-26 |
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