JPH0221148B2 - - Google Patents

Info

Publication number
JPH0221148B2
JPH0221148B2 JP56194974A JP19497481A JPH0221148B2 JP H0221148 B2 JPH0221148 B2 JP H0221148B2 JP 56194974 A JP56194974 A JP 56194974A JP 19497481 A JP19497481 A JP 19497481A JP H0221148 B2 JPH0221148 B2 JP H0221148B2
Authority
JP
Japan
Prior art keywords
source
drain
less
annealing
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56194974A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5896763A (ja
Inventor
Juri Kato
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP56194974A priority Critical patent/JPS5896763A/ja
Publication of JPS5896763A publication Critical patent/JPS5896763A/ja
Publication of JPH0221148B2 publication Critical patent/JPH0221148B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP56194974A 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法 Granted JPS5896763A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1033138A Division JPH02353A (ja) 1989-02-13 1989-02-13 Ｃｍｏｓ型半導体装置

Publications (2)

Publication Number Publication Date
JPS5896763A JPS5896763A (ja) 1983-06-08
JPH0221148B2 true JPH0221148B2 (zh) 1990-05-11

Family

ID=16333434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56194974A Granted JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Country Status (1)

Country Link
JP (1) JPS5896763A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601862A (ja) * 1983-06-20 1985-01-08 Seiko Epson Corp 半導体装置の製造方法
JPS6077419A (ja) * 1983-10-04 1985-05-02 Seiko Epson Corp 半導体装置の製造方法
JP2534608B2 (ja) * 1993-01-18 1996-09-18 セイコーエプソン株式会社 半導体装置の製造方法
JP3221484B2 (ja) 1998-03-04 2001-10-22 日本電気株式会社 半導体装置の製造方法
JP2002332073A (ja) * 2001-05-08 2002-11-22 Rootarii Kk 微小穿孔シート

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
APPL PHYS LETT INCOHERENT-LIGHT-FLASH ANNEALING OF PHOSPHORUS-IMPLANTED SILICON=1980 *
JAPANESE JOURNAL OF APPLIED PHYSICS RADIATION ANNEALING OF BORON-IMPLANTED SILICON WITH A HALOGEN LAMP=1980 *

Also Published As

Publication number Publication date
JPS5896763A (ja) 1983-06-08

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