JPH02206933A - Phase difference absorbing system - Google Patents

Abstract

PURPOSE:To attain the phase adjustment of data between two electric circuit system with a prescribed scale of the circuit independently of the operating period of a synchronous system by always keeping the phase difference of timing signal of the systems implementing the periodic operation at one and the same period to a prescribed value. CONSTITUTION:A phase difference deciding means 6 is provided on one reception electric circuit system B to decide the phase difference between a received data DT'ab and the operating period of the system B and generate a control signal for a period corresponding to an error between the phase difference and a phase difference decided to be an object. Moreover, a phase control means 7 is provided on other transmission electric circuit system A to mask a timing signal Ta in the system A for a period of the control signal. Thus, the phase difference of the timing signals of both systems A, B is always kept to a prescribed value. Thus, the phase adjustment of data between the systems is implemented with the prescribed scale of the circuit independently of the operating period of the synchronous system.

Description

[Detailed Description of the Invention] [Summary] Regarding a phase difference absorption method in data communication between resynchronized systems that operate periodically, the phase difference of data between the systems is adjusted by a fixed circuit size regardless of the operation cycle of the synchronized system. The purpose of this system is to provide an adjustable phase difference absorption method, which operates using timing signals that are independently generated from the same basic clock and performs periodic operations at the same cycle. Data created in synchronization with the timing signal of A is transmitted to the other system B, and system B receives it in synchronization with the timing signal of system B. In both electric circuit systems A and B, the transmitted data and system B are One system B is equipped with a phase difference determining means that determines the phase difference with the operating cycle of the system B and generates a control signal for a period corresponding to the error with the target value. System A is provided with a phase control means for masking the timing signal in system A, and the phase difference between the timing signals of both systems A and B is always maintained at a predetermined value.

[Industrial application field]

The present invention relates to a method for absorbing a phase difference in data between two systems, and particularly relates to a method for absorbing a phase difference in data communication between two synchronous systems that operate periodically.

In the case of inter-frame communication in multi-connected circuit switching devices that perform time-division operations, each device synchronizes with each other and performs periodic operations.

In such data communication between both systems that operate periodically in synchronization with each other, it is possible to perform timing phase adjustment between the systems regardless of the operating cycle of the synchronous system, and
At this time, it is desired that the required circuit scale be small.

[Conventional technology]

FIG. 5 shows a conventional phase difference absorption method.

Reference numeral 11 denotes a clock generation source, which generates a clock signal and supplies timing generation circuits 12 in both electric circuit systems A and B.
．． 13. Timing ordering circuits 12 and 13 generate various control timing signals for periodically operating both electric circuit systems A and B.

The timing signals outputted from the timing generation circuits 12 and 13 indicate the division of each operation cycle, and serve as a pointer indicating the position of certain data for transmission data.

In the electric circuit system A, the data transmitting circuit 14 transmits transmission data (DTab) according to the timing signal (T a ) from the timing generating circuit 12, and the data receiving circuit 15 in the electric circuit system B transmits the transmission data (DTab) according to the timing signal (T a ) from the timing generating circuit 13. This data is received according to the timing signal (Tb).

In this case, the phase of the data transmitted from the data transmitting circuit 14 generally does not match the timing of data reception in the data receiving circuit 15 and cannot be received until then, so the phase of the received data in the electric circuit system B. Adjustments will need to be made.

The elastic memory 16 writes the transmission data in synchronization with the timing signal (Ta) and reads it out in synchronization with the timing signal (Tb) after a certain period of time, thereby determining the phase of the output transmission data (DT''ab). The timing signal (Tb) is made to match the timing signal (Tb) of the receiving circuit 15. This allows the data receiving circuit 15 to correctly receive the transmitted data.

The elastic memory 16 has a capacity for one operation period of normal data, and has a capacity for both timing signals (Ta.

Even if the phase between input and output data changes within a certain range, it is possible to adjust the phase between input and output data, but depending on the phase relationship between both timing signals (Ta, , Tb), normal data may be data is damaged and cannot be read. For example, if data is input and read at the same time, the output data becomes unstable.

In FIG. 5, the selection decision circuit 17 outputs both timing signals (
According to the phase information between Ta and Tb), a control signal is output which is "0" when the phase relationship is normal and "1" when it is not normal.

The selection circuit 18 selects the transmission data (
DTab) and the timing signal (Ta) are directly input to the elastic memory 16, and when it is '1', the output of the data delay circuit 19 is selected.In this case, the data delay circuit 1
9 is the transmission data (DTab) and the timing signal (T a
) is delayed for a predetermined period of time, thereby enabling the elastic memory 1G to always perform correct phase adjustment.

[Problem to be solved by the invention]

In the conventional phase difference absorption method shown in FIG. 5, the depth of the elastic memory (
(length) requires an amount equivalent to the operating cycle of the system.

For example, in a system with an operating period of l kb i t/the same period, an elastic memory with a depth of 1 kbtt is required,
In a system with an operating cycle of 10 kbit/cycle, the depth is 10
Required kbit of elastic memory.

As described above, the conventional system has a problem in that the circuit scale becomes large in the case of a system with a long operation cycle.

The present invention aims to solve the problems of the prior art, and provides a phase difference absorption method that can adjust the phase of data between systems using a fixed circuit scale regardless of the operating cycle of the synchronous system. The purpose is to

[Means to solve the problem]

As shown in FIG. 1, the present invention operates according to timing signals independently generated from the same basic clock circuit, and performs periodic operations at the same cycle. Both electric circuit systems A transmit the data created in synchronization with the timing signal of system A to the other system B, and receive the data in system B in synchronization with the timing signal of system B.
, B, one system B is equipped with phase difference determination means 6, and the other system A is equipped with phase control means 7, so that both systems A
, B are always kept at a predetermined value. Here, the phase difference determining means 6 determines the phase difference between the transmitted data and the operating cycle of the system B, and generates a control signal for a period corresponding to the error with the target value.

The phase control means 7 masks the timing signal in the other system A during that period in response to this control signal.

[For production]

As shown in the principle configuration diagram of FIG. 1, electric circuit system A,
Each of the circuits B is provided with a timing generation circuit 2.3, which independently generates timing signals 'l'a and Tb from the clock signal of the same clock source 1, and operates according to the respective timing signals 'l'a and 'rb. They perform periodic operations at the same cycle. Then, the data transmission circuit 4 of one system A creates data DTa b in synchronization with the timing signal Ta of system A and transmits it to the other system B, and the data reception circuit 5 of the other system B is received in synchronization with the timing signal Tb.

In this case, one system (receiving system) B is provided with phase difference determining means 6 to determine the phase difference between the received data l)'l''ab and the operating cycle of that system B, and to obtain the target phase difference. A control signal for a period corresponding to the error between the value and the determined phase difference is generated.

Further, the other system (transmission system) A is provided with phase control means 7,
In response to this control signal, the timing signal Ta in system A is masked during the period of the control signal.

By controlling in this way, the phase difference between the timing signals of both systems A and B is always maintained at a predetermined value, so the phase of data between systems can be adjusted using a fixed circuit scale regardless of the operating cycle of the synchronous system. You will be able to do this.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the same parts as in FIG. , 22 is an OR circuit.

FIG. 3 is a time chart showing the signals of each part in the embodiment of FIG.
Tb), ■ is the timing signal (Ta) of system A after passing through the elastic memory 16, ■ is the control signal output from the phase difference determining means, ■ is the clock signal of system A,
(2) is a control signal after passing through the elastic memory 21, (2) is a basic clock signal for the timing generation circuit 12, and (2) is a timing signal (T, b) output from the timing generation circuit 12, and each of these signals are also indicated in FIG. 2 by the same numbers. Although FIG. 3 describes a case where the target value of the phase difference between both timing signals ('l'a, Tb) is zero, the present invention is not limited to this.

The timing generation circuit 13 generates a timing signal (Tb) (2) consisting of a 1-bit wide positive polarity isolated pulse in response to the clock signal (2) of the system B from the clock generation source 11.

The phase difference determination circuit 20 compares the phase of this timing signal (1) with the timing signal (Ta) (2) consisting of a 1-bit width positive polarity isolated pulse after passing through the elastic memory 16, and determines the timing signal (Ta). When the timing signal (Tb) is generated before the timing signal (Tb), a control signal (2) consisting of a positive pulse having a width equal to the phase difference between the two timing signals is generated. In Figure 3, the timing signal (Ta)
is in a state where the phase is advanced by 2 bits of the clock signal from the timing signal (Tb) (2), and as a result, a 2-bit long control signal (2) is generated.

The elastic memory 21 delays the control signal (R) by a predetermined number of bits, generates a control signal ■, and inputs it to the OR circuit 22.The OR circuit 22 also receives the system A clock signal ■ from the clock generation source 11. The basic clock signal ■ is input to the timing generating circuit 12 by taking the logical sum of both signals.The basic clock signal ■ has a no-signal state based on the control signal ■ as shown by A in FIG. Contains.

The timing generation circuit 12 generates the timing signal (T a )■ in response to the clock signal ■, but since the basic clock signal ■ of the timing generation circuit 12 is masked for a 2-bit period, the timing signal (Ta)■ and the timing The phase difference with the signal (Tb) ■ was initially 4 bits + α, but because of the 2-bit timing generation circuit stop period B, the phase difference with the next timing signal (Ta) ■ becomes 2 bits + α with a delay of 2 bits. becomes.

The delay in the timing signal (Ta) is reflected linearly even after passing through the elastic memory 16, and
As shown in the figure, the phase difference between the timing signal (T a ) and the timing signal (Tb) becomes zero.

Thereafter, the control signal (2) of the phase difference determination circuit 20 is fixed at a low level, and the basic clock signal (2) for the timing generation circuit 12 of system A is no longer masked, so that the phase difference between both timing signals is fixed.

In this way, in the case of the method of the present invention, the data transmitting circuit 14
A timing signal (Ta) for the transmission data (DTab) inputted to the elastic memory 16 from
The phase relationship with (b) is always constant, so the depth (length) of the elastic memory for absorbing phase fluctuations in received data may be constant regardless of the operating cycle of the synchronous system. The same applies to the elastic memory 21. In practice, elastic memory 16.21 is only a few bits deep regardless of the operating cycle.
The circuit scale can be significantly reduced.

FIG. 4 shows a specific configuration example of the phase difference determination circuit, in which (a) shows the circuit configuration, 31.32 is an inverter, 33 to 35 are AND circuits, 36 is an OR circuit, and 37
is a D-type flip-flop. This circuit receives timing signals Ta and timing Tb as inputs, operates in response to clock inputs, and generates a control signal output according to the truth table shown in (mountain). However, this circuit produces output logic values that satisfy the same truth values. If so, it is not limited to this circuit.

〔Effect of the invention〕

As explained above, according to the present invention, the phase difference between the transmitted data and the operating cycle of the receiving system is determined, a control signal for a period corresponding to the error with the target value is generated, and the control signal is responsive to the control signal. By masking the timing signal in the other system during that period, the phase difference between the timing signals in both systems is always maintained at a predetermined value. The data created in one system is transmitted to the other thread in synchronization with the timing signal, and the data is received in synchronization with the timing signal of that system in the other system. It becomes possible to adjust the phase of data between systems by using a fixed circuit size regardless of the operating cycle.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing signals of various parts in the embodiment of Fig. 2, and Fig. 4. 5 is a diagram showing a specific configuration example of a phase difference determination circuit. FIG. 5 is a diagram showing a conventional phase difference absorption method. 11-clock generation source 12, 13-m-timing generation circuit 14-data transmission circuit 15-data reception circuit 16, 21-m-elastic memory 20-phase difference determination circuit (PC) 22-OR circuit

Claims (1)

[Claims] Operates with timing signals independently generated from the same basic clock to perform periodic operations with the same cycle, and one system (A) operates according to the timing signal of the system (A). In both electrical circuit systems (A, B), the data created in synchronization is transmitted to the other system (B), and the system (B) receives it in synchronization with the timing signal of the system (B). A phase difference determining means (6) for determining the phase difference between the data and the operating cycle of the system (B) and generating a control signal for a period corresponding to the error with the target value is provided in one system (B). and phase control means (7) for masking the timing signal in the other system (A) for the period according to the control signal.
) A phase difference absorption method characterized by always keeping the phase difference between the timing signals of both systems (A, B) at a predetermined value.