JPH02205778A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02205778A JPH02205778A JP1023870A JP2387089A JPH02205778A JP H02205778 A JPH02205778 A JP H02205778A JP 1023870 A JP1023870 A JP 1023870A JP 2387089 A JP2387089 A JP 2387089A JP H02205778 A JPH02205778 A JP H02205778A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- diagnostic observation
- observation terminal
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000523 sample Substances 0.000 abstract description 5
- 238000012360 testing method Methods 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000004458 analytical method Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子計算機システム等に使用する半導体装置
及びその故障解析方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device used in an electronic computer system and a failure analysis method thereof.
従来の半導体装置は、特開昭６２−１６５３４９号公報
に記載のように、診断容易化については配慮されていな
かった。Conventional semiconductor devices have not been designed to facilitate diagnosis, as described in Japanese Unexamined Patent Publication No. 165349/1983.
上記従来技術は、半導体装置の故障解析の点について配
慮がされておらず、故障解析工数を要する問題があった
。The above-mentioned conventional technology does not give consideration to failure analysis of semiconductor devices, and has the problem of requiring a lot of man-hours for failure analysis.
本発明は半導体装置及び印刷配線基板の故障解析工数を
低減することを目的としている。The present invention aims to reduce the number of man-hours required for failure analysis of semiconductor devices and printed wiring boards.
上記目的を達成するために、半導体装置のパッケージ上
部に診断用観測端子を付加したものである。In order to achieve the above object, a diagnostic observation terminal is added to the upper part of the package of the semiconductor device.
単導体装置単体をＬＳＩテスタで受入れテストする場合
、及び半導体装置を搭載した印刷配線基板のテストにお
いて、故障解析時に半導体装置のパッケージ上部に付加
された診断観測端子の論理値を調べる。これにより半導
体装置の不良解析が容易となり、印刷配線基板に搭載さ
れた場合においては、他の搭載部品との不良の切分けが
要易となる。When a single conductor device is accepted for an acceptance test using an LSI tester, and when a printed wiring board on which a semiconductor device is mounted is tested, the logical value of a diagnostic observation terminal attached to the top of the package of the semiconductor device is checked during failure analysis. This facilitates failure analysis of the semiconductor device, and when mounted on a printed wiring board, it becomes easy to isolate the failure from other mounted components.
以下、本発明の一実施例を第１図、第２図、第３図によ
り説明する。An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.
半導体装置５の単体テスト時、又は印刷配線基板６に搭
載してテスト時に、半導体装置５の出力値不良の場合、
テスタプローブ１０により出力ピン１の論理値を観測す
る。If the output value of the semiconductor device 5 is defective during a unit test of the semiconductor device 5 or when tested after being mounted on the printed wiring board 6,
The logic value of output pin 1 is observed by tester probe 10.
論理値不良の場合、半導体装置５の上部に付加した診断
用観測端子４及び８をテスタプローブ１０で観測するこ
とにより容易に半導体装置の不良を摘出できる。診断用
観測端子４，７．８は第１図。In the case of a logic value defect, the defect in the semiconductor device can be easily identified by observing the diagnostic observation terminals 4 and 8 added to the upper part of the semiconductor device 5 with the tester probe 10. Diagnostic observation terminals 4, 7.8 are shown in Figure 1.
第２図及び第３図に示すように入力側、内部論理及び出
力側の各論理ブロックに付加し、半導体装置５の上部樹
脂に埋め込まれてハトメ状の形となっている。本実施例
によれば、半導体装置５自身と、半導体装置５の周辺論
理の不良切分けが容易となり、故障解析工数を低減でき
る効果がある。As shown in FIGS. 2 and 3, it is added to each logic block on the input side, internal logic, and output side, and is embedded in the upper resin of the semiconductor device 5 to form an eyelet-like shape. According to this embodiment, it becomes easy to isolate faults in the semiconductor device 5 itself and the peripheral logic of the semiconductor device 5, and there is an effect that the number of man-hours for failure analysis can be reduced.
本発明によれば、半導体装置単体のテスト時の故障解析
において診断用観測端子により容易に調べることができ
るので、故障解析工数を低減する効果がある。According to the present invention, failure analysis during testing of a single semiconductor device can be easily investigated using a diagnostic observation terminal, which has the effect of reducing the number of failure analysis steps.
また、上記半導体装置を搭載した印刷配線基板において
、他の部品不良又はバタン断線等により半導体装置の出
力値が影響を受け、故障解析が困難な場合でも診断用観
測端子により、故障解析できる。Further, in the printed wiring board on which the semiconductor device is mounted, even if the output value of the semiconductor device is affected by other defective parts or disconnection of a button, and failure analysis is difficult, the failure analysis can be performed using the diagnostic observation terminal.
第１図は本発明の一実施例の半導体装置縦断面図、第２
図は第１図の平面図、第３図は半導体装置の論理回路で
ある。
１・・・リードフレーム、 ２・・・半導体素子。
３・・・ボンディングワイヤ。
４・・・診断用観測端子、 ５・・・半導体装置。
６・・・印刷配線基板、 ７・・・診断用Ｉ！測端子
。
８・・・診断用観測端子、 ９・・・論理ブロック。
１０・・・テスタプローブ。FIG. 1 is a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is a plan view of FIG. 1, and FIG. 3 is a logic circuit of the semiconductor device. 1...Lead frame, 2...Semiconductor element. 3...Bonding wire. 4...Diagnostic observation terminal, 5...Semiconductor device. 6...Printed wiring board, 7...Diagnostic I! Measuring terminal. 8...Diagnostic observation terminal, 9...Logic block. 10...Tester probe.
Claims (1)
端子を設けたことを特徴とする半導体装置。1. A semiconductor device characterized in that a diagnostic observation terminal is provided at the top of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1023870A JPH02205778A (en) | 1989-02-03 | 1989-02-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1023870A JPH02205778A (en) | 1989-02-03 | 1989-02-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02205778A true JPH02205778A (en) | 1990-08-15 |
Family
ID=12122481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1023870A Pending JPH02205778A (en) | 1989-02-03 | 1989-02-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02205778A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8963150B2 (en) | 2011-08-02 | 2015-02-24 | Samsung Display Co., Ltd. | Semiconductor device having a test pad connected to an exposed pad |
-
1989
- 1989-02-03 JP JP1023870A patent/JPH02205778A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8963150B2 (en) | 2011-08-02 | 2015-02-24 | Samsung Display Co., Ltd. | Semiconductor device having a test pad connected to an exposed pad |
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