JPH02205326A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable multichannels without generating dislocation even by using an InGaAs layer having a different lattice constant to a GaAs substrate as a channel layer by bringing the synthetic quantity of deformation to zero at every pair of a first compound semiconductor layer as the channel layer and a second compound semiconductor layer as an electron supply layer. CONSTITUTION:A non-doped i-GaAs layer 12 is formed onto a GaAs substrate 10 as a buffer layer, and three pairs of channel layers 14 and electron supply layers 16 are shaped onto the layer 12. That is, the i-In0.2Ga0.8As layers 14a-14c in thickness of 150Angstrom as the channel layers and the n-In0.68Ga0.32P layers 16a-16c in thickness of 150Angstrom as the electron supply layers are laminated alternately. Since the absolute values of positive deformation sigmax to the substrate 10 of the layers 14a-14c and the absolute values of negative deformation sigmay to the substrate 10 of the layers 16a-16c are equalized at that time, the thickness of the layers 14a-14c and the layers 16a-16c is made uniform. Accordingly, no dislocation is generated, thus realizing a change into multichannels.

Description

[Detailed Description of the Invention] [1] Regarding semiconductor devices, particularly multi-channel HEMTs (high electron mobility transistors) having multiple channel layers, a multi-channel HEMT using InGaAs as a channel layer, which is suitable for high-speed performance. The present invention aims to provide a semiconductor device that is a type HEMT, and includes a first compound semiconductor layer as a channel layer on a GaAs substrate, and a second compound semiconductor layer as an electron supply layer having a smaller electron affinity than the channel layer. A plurality of pairs are alternately formed, and the first compound semiconductor layer has a thickness dx within a critical film thickness at which dislocation does not occur independently with respect to the GaAs substrate, and a strain on the GaAs substrate. Let σx be the thickness of the second compound semiconductor layer within the critical film thickness at which no dislocation occurs independently with respect to the GaAs substrate, dy, and the strain with respect to the GaAs substrate be dy, and for each pair, the formula % is given. The composition ratio and thickness dx of the first compound semiconductor layer and the composition ratio and thickness ciy of the second compound semiconductor layer are determined so that the formula % holds true.

[Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a multichannel HEMT (high electron mobility transistor) having a plurality of channel layers.

With the recent demand for ultra-high-speed computers, higher performance semiconductor devices are required. HEMTs, which are ultra-high-speed transistors, are also required to have higher speed performance and larger current.

[Prior Art] In a GaAs/AjGaAs HEMT, it is known to use InGaAs as the material of the channel layer through which electrons travel, instead of the conventional GaAs, in order to achieve higher speeds.

FIG. 6 shows a conventional HEMT capable of high-speed operation.

As shown in FIG. 6(a), a non-doped 1-GaAs layer 52 is formed on a GaAs substrate 50 as a buffer layer. On the 1-GaAs layer 52, a 2G layer with a thickness of about 150A is formed as a channel layer to increase the speed.
ao, a AsssA is formed, and this i-T no2
On the Gao, s As layer 54, there is a n-Al! a, + sG ao
, asA 8 layer 56 is formed as an electron supply layer. n = A j o, IsG a o, ssA
A source electrode 6 is formed on the s layer 56 with a gate electrode 58 in between.
0 and a drain voltage i#A62 are formed.

This conventional HEMT is a single-channel type H
Since it is a BMT, although it can achieve high-speed performance, it cannot meet the demand for large current.

It is known that in order to realize a large iS flow of HEMT, it is sufficient to provide a plurality of channel layers to increase the number of channels.

FIG. 7 shows a multi-channel version of the HEMT shown in FIG. 6. On the 1-GaAs layer 52 as a buffer layer, a channel layer of II no, 2G a with a thickness of about 150A is formed.
o, s A 5 layers 54a, 54b, 54C, and n-AJo, IsGao with a thickness of about 300A as an electron supply layer.
, asA 8 layers 56a, 56b, 56c alternately 3
vs. laminated.

According to this conventional HEMT, three quantum wells are formed as shown in the energy band diagram of FIG. 7(b), and multi-channels can be achieved.

[Problems to be Solved by the Invention] However, 1-In0.2 on the GaAs substrate 50
G a o, * A 8 layers 54 and n Ajo, Is
When the Gao, 5sAs layers 56 are alternately multilayered,
1-In. .

The lattice constant of the G ao,s A s layer 54 is GaAs
Since the stress is different from the above, there is a problem in that the strain accumulates and exceeds the critical stress at which dislocations occur, causing dislocations near the Peter interface. This causes a significant deterioration of two-dimensional electron mobility, and the device no longer operates.

As described above, there is a problem in that the strain, which is not enough to cause dislocation in a single channel, is accumulated in multiple channels and causes dislocation that causes the device to become inoperable.

Therefore, multi-channel HEM using InGaAs, which is suitable for high-speed performance but has a different lattice constant from GaAs,
I couldn't make T.

The present invention was made in consideration of the above circumstances, and
It is an object of the present invention to provide a semiconductor device that is a multichannel HEMT using a compound semiconductor suitable for high-speed performance such as aAs for the channel layer.

[Means to solve the problem] FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1(a), for example, an undoped 1-GaAs layer 12 is formed as a buffer layer on a GaAs substrate 10. As shown in FIG. On the t-GaAs layer 12, a 1-1n Ga1-XAS layer 14 having a thickness of dx, for example, is formed as a first compound semiconductor layer which is a channel layer in order to increase the speed. The i-In GaAs layer 14 is made of G
Since the lattice constant is larger than that of the aAs substrate 1x 1-x O, a compressive stress that is a positive strain acts on the GaAs substrate 10, as shown in FIG. 1(b).

In the present invention, for example, an n-1nGaPy 1-y layer 16 having a thickness dy is formed on the 1-1nGaAs layer x 1-x 14 as a second compound semiconductor layer serving as an electron supply layer. The n-InGaPy 1-y layer 16 has a lattice constant smaller than that of the GaAs substrate 10 in the opposite direction x 1-x to the L-InGaAs layer 14, so the first
As shown in Figure (b), tensile stress, which is a negative strain, acts.

Note that on the n-1nGaP layer 16 there is a y 1-y gate electrode [! A source electrode 20 and a drain 'rjhiffA22 are formed with 18 in between.

In the present invention, the negative strain of the n-InGaPnGaA layer 16 1-y causes
The positive strain in the s-layer 14 is compensated to make the overall combined strain zero.

The lattice constant of the 1-1nGaAs layer 14 depends on the composition ratio X, and the lattice constant of the n-1nGaP layer 1y1-y6 depends on the composition ratio y. The amount of strain in each layer 14.15 is adjusted by adjusting the amount of strain in each layer 14.15, and the amount of strain is adjusted by adjusting the thickness dx and dy of each layer 14.16. In other words, depending on the composition ratio x and y, Figure 1 (
Adjust the size of the horizontal axis in b) to determine the thickness d of each layer 14.16.
Adjust the size of the vertical axis in Figure 1(b) using x and dy,
The total value of the areas Sx and Sy of each distortion is made to be approximately zero.

Composition ratio X of xi-x As layer, strain σx on GaAs nGa substrate, y of InGa P layer
1-y The relationship between the composition ratio y and the strain dy on the GaAs substrate is expressed as the second
x 1- of the InGaAs layer 14 shown in the figure
x, the strain σx is proportional to the composition ratio X, as shown in Fig. 2(a), and the InGaP layer y
In the case of 1-y 16, as shown in Figure 2(b), the composition ratio y
0.48, which is a composition that lattice matches with the GaAs substrate.
The distortion dy is proportional to the value y-0,48. Moreover, x=0.1. σ1 when y=0.58, x=0
．． 2. The absolute value of σ2 when y=0.68 is almost the same in the relationship between σx and dy.

In general, if the combined value of strain for each pair is zero, it is possible to repeatedly stack the pairs (R, Hull,
et al, “5tabilly of
semiconductor 5trained-1
ayer 5upperlatNces”, Appl,
Phys, Lett.

48(1), 6 January 1988).

Therefore, in the semiconductor device according to the present invention, a plurality of pairs of a first compound semiconductor layer as a channel layer and a second compound semiconductor layer as an electron supply layer having a smaller electron affinity than the channel layer are alternately formed on a GaAS substrate. forming the first
dx is the thickness of the compound semiconductor layer within the critical film thickness at which no dislocation occurs independently with respect to the GaAs substrate, and dx is the thickness of the compound semiconductor layer of
For each pair, let σx be the strain on the aAs substrate, dy be the thickness within the critical film thickness at which no dislocation occurs in the second compound semiconductor layer on the GaAs substrate, and dy be the strain on the GaAs substrate. The composition ratio and thickness dx of the first compound semiconductor layer and the composition ratio and thickness ciy of the second compound semiconductor layer are determined so that the formula % formula % holds true for each case.

[Function] According to the present invention, since the amount of combined strain is made zero for each pair of the first compound semiconductor layer which is the channel layer and the second compound semiconductor layer which is the electron supply layer, the GaAs Even if an InGaAs layer having a different lattice constant with respect to the substrate is used as a channel layer, multi-channel formation is possible without generating dislocations.

[Example] A semiconductor device according to a first example of the present invention is shown in FIG.

The semiconductor device according to this embodiment is a three-channel HEMT.

As shown in FIG. 3(a), a non-doped 1-GaAs layer 12 is formed on a GaAs substrate 10 as a buffer layer. Three pairs of channel layers and electron supply layers are formed on the 1-GaAs layer 12.

150mm thick i Ino as channel layer, 2G
ao, sA s layers 14a, 14b, 14c,
150 people thick n Ino as electron supply layer, 6s
Gao and s2P layers 16a, 16b, and 16c are alternately stacked. n I no, 1sGao, s2P
The impurity concentration of layers 16a, 16b, and 16c is 2×10
"cxrr-".

As shown in FIG. 3(b), i −I no, 2Gao
.

The absolute value of the positive strain σx of the aAs layers 14a, 14b, 14c on the GaAs substrate 10, n-Ino, aaG
Since the absolute values of the negative strain σy of the a o, zP layers 16a, 16b, 16c with respect to the GaAs substrate 10 are equal, these i I no, 2 Gao, s As layers 14a, 1
4b, 14c and n I no, asG a 0.3
The 2P layers 16a, 16b, and 16c may have the same thickness.

The thickness of each layer is based on the theory of HattheWS et al. (J, W
, Hatthev Is, et al.
ct in Epitaxial Multilayer
rs”, Journal of Crystal G
In this embodiment, each layer 14a, 14b, 14c, 16a, 16b, 16
The thickness of c was set to 150 people.

Top layer n I no, aaGao, izP layer 16c
An n-GaAs layer 24 is formed thereon to facilitate ohmic contact. This n-GaA
A gate electrode 18 is formed in a concave portion at the center of the s-layer 24, and a source electrode 20 and a drain electrode 2 are connected to the gate with the pole 18 in between.
2 is formed.

In this way, according to this embodiment, the combined strain of each pair of channel layer and electron supply layer becomes almost zero, so even if three pairs are stacked, no dislocation occurs, and the I layer is suitable for high-speed performance. Multi-channel HE using nGaAs for channel layer
MT can be achieved.

A semiconductor device according to a second embodiment of the present invention is shown in FIG. 4. The same components as in the first embodiment are given the same reference numerals and their explanations will be omitted.

The semiconductor device according to this embodiment is a 10-channel HBMT.

In this example, the channel layer has the same composition ratio x as in the first example.
The difference is that n I no, saG a 0.42P with a lower composition ratio y=0.58 is used as the electron supply layer. n-Ino, 5sG, which is an electron supply layer
Since the composition ratio y of aO, 42P has become lower and the absolute value of strain σy has become approximately half, n I no, aaGao,
The feature is that the thickness of the 2P layer is approximately doubled in order to increase the amount of strain in the entire 2P layer.

That is, on the 1-GaAs layer 12 which is a buffer layer,
1Ino, 2Gao with 150mm thickness as channel layer
, sAs layers 14a, 14b, and 14j, and a 300-layer-thick n-Ino, saGa layer as an electron supply layer.
0.42P layers 16a, 16b, -16j alternately 10
vs. laminated. n Ino, s.

The impurity concentration of the G a 0.42P layers 16a, 16b, -16j is I x 10 "cII-".

In this way, according to this embodiment, even if the absolute value of strain in each layer differs depending on the composition ratio of the channel layer and electron supply layer, by adjusting the amount of strain depending on the thickness, the combined strain of each equal layer can be reduced. It can be reduced to almost zero. Therefore, it is possible to realize a multi-channel HEMT using InGaAs, which is suitable for high-speed performance, for the channel layer.

A semiconductor device according to a third embodiment of the present invention is shown in FIG. 5. The same components as in the first and second embodiments are given the same reference numerals and their explanations will be omitted.

The semiconductor device according to this embodiment is a 5-channel inverse structure HEM.
It is T.

The HEMT of this example is different from the first and second examples described above, and is a HEMT partially having a so-called inverted f# structure in which a channel layer is laminated on an electron supply layer. Also,
By reducing the thickness of each layer and reducing the number of channels,
Channel.

That is, on the 1-GaAs layer 12 which is a buffer layer,
200-person thick n −I n o as electron supply layer,
ssG a O, 42P layer 16a, 16. b, -16
e and 100-layer thick 1-Ino as the channel layer,
Five pairs of tGao, sAsAs layers a, 14b, and -14e are alternately laminated. n I no, 5sGa 0
．． The impurity concentration of the 42P layers 16a, 16b, -16e is 2
X 10 "am-".

As described above, according to this embodiment, even in the case of an H EMT partially having an inverse structure, it is possible to achieve multichannelization in the high-speed performance channel layer.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, although the above embodiments are a 10-channel HEMT and a 5-channel HEMT, the number of channels can be increased or decreased as necessary.

In addition, the composition ratios X and x of the InGaAs layer
1-x thickness dx and composition ratio y and y of the InGaP layer
The thickness cty can be freely selected as long as it is within the limit thickness that does not cause dislocation in a single layer and within the range where the formula % formula % holds true.

[Effects of the Invention] As described above, according to the present invention, the amount of combined strain of the first compound semiconductor layer, which is the channel layer, and the second compound semiconductor layer, which is the electron supply layer, becomes equal to zero. Even if the first compound semiconductor layer having a different lattice constant from that of the GaAs substrate is used as the channel layer, multi-channel formation is possible without generating dislocations. Therefore, it is possible to both increase the speed and increase the current of the HEMT. In addition, the electron supply layer is made of conventional Al.
If GaAs is replaced with InGaP, DX
The center problem can also be solved, and the performance of semiconductor devices can be further improved.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle of the present invention, Figure 2 is a diagram showing the composition ratios X and x of the InGaAs layer.
1-x Strain σx and In Ga for GaAs substrate
1-y Composition ratio y of P layer and strain σy on GaAs substrate
3 is a diagram showing a semiconductor device according to a first embodiment of the present invention, FIG. 4 is a diagram showing a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a diagram showing a conventional HEMT, and FIG. 7 is a diagram showing a HEMT in which FIG. 6 is made multi-channel. 18... Gate electrode 20... Source electrode 22... Drain electrode 24 -n-GaAs layer 50--- GaAs substrate 52-i-GaAs layer 54-I Ino, 2Gao, a As layer 56...
n Ajo, +5 Gao, asAs layer 58...gate electrode 60...source electrode 62...drain electrode In the diagram, 10.-GaAs substrate 12--i-GaAs layer (buffer layer) 14.14a
, 14b, ---, 14jx 1-x As layer (channel layer)... 1-InGa 16, 16a, 16b, -=, 16J...
n-jnGaP layer (electron supply layer) y 1-y (α) Cb) (α) (b) A diagram showing a semiconductor device according to a second embodiment of the present invention.

Claims (1)

[Claims] A plurality of pairs of a first compound semiconductor layer as a channel layer and a second compound semiconductor layer as an electron supply layer having a smaller electron affinity than the channel layer are alternately formed on a GaAs substrate. , dx is the thickness of the first compound semiconductor layer within a critical film thickness at which no dislocation occurs independently with respect to the GaAs substrate.
, the strain on the GaAs substrate is σx, and the thickness of the second compound semiconductor layer within a critical thickness range at which no dislocation occurs independently with respect to the GaAs substrate is dy.
, the composition ratio and thickness dx of the first compound semiconductor layer, and the thickness dx of the second compound semiconductor layer so that the following formula dx×σx+dy×σy~0 holds for each pair, where σy is the strain on the GaAs substrate. A semiconductor device characterized in that a composition ratio and a thickness dy are determined.