JPH08279609A - High electron mobility semiconductor device - Google Patents

Abstract

PURPOSE: To increase the density of two-dimensional carrier gas formed in a distorted channel layer from a carrier feeding layer by a method wherein at least a compound semiconductor distorted layer, having a lattice constant equal to a substrate, is introduced into the compound semiconductor distorted layer. CONSTITUTION: In this high electron mobility semiconductor device HEMT, a compound semiconductor distorted channel layer, for example, a substrate in an i-InGaAs distorted layer 3A, compound semiconductor distortion alleviated layer having a lattice constant equal to a semiinsulating GaAs substrate 1, a channel laminated body in which at least a layer of an i-InGaAs distortion alleviating layer is introduced, and a channel laminated body 3 are provided. Also, a compound semiconductor distortion alleviating layer formed by the material having the distortion opposing to the compound semiconductor distorted channel layer such as a channel laminated body, in which at least a layer of an i-InGaP distortion alleviating layer 13B is introduced and a channel laminated boy 13, for example, are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility semiconductor device capable of passing a large current so that it can be used as a high power semiconductor device in a microwave band.

[0002] In general, in the field of mobile communication, the use of consumer communication devices such as mobile phones is becoming popular, and the application of microwave high-power devices is also active in the field of such consumer communication devices.

In mobile phones and the like, the capacity is limited because the power source is a battery, so there is a strict demand for performance improvements such as lower voltage and higher efficiency for the above high output devices.

The present invention is a high electron mobility transistor (high electron) that exhibits excellent performance in the microwave band.
ctron mobility transist
r: HEMT) to meet the above requirement.

[0005]

2. Description of the Related Art As means for increasing the output of HEMT,
In many cases, a double channel structure or a multi-channel structure is adopted to allow a large current to flow.

A material system, such as AlGaAs, which can realize a two-dimensional electron gas having a large electron concentration.
A material system represented by (carrier supply layer) / InGaAs (channel layer) is also used to utilize a strained lattice type two-dimensional electron gas.

[0007]

[Problems to be Solved by the Invention] For example, AlGaAs
In the / InGaAs strained lattice HEMT, a two-dimensional electron gas is generated in the strained InGaAs layer.

When an InGaAs layer is grown on a GaAs substrate, the InGaAs layer has a lattice constant different from that of the underlying GaAs substrate, and therefore, crystal growth is carried out while receiving strain stress with the same lattice constant as that of the underlying material.

In the strained lattice HEMT, the above-mentioned crystal growth is utilized. In that case, InGa
There is a limit to the layer thickness of the As channel layer, and dislocations occur when the thickness exceeds the critical layer thickness, so the layer thickness must be made less than that.

Therefore, the degree of freedom in selecting the InAs molar ratio and layer thickness in InGaAs is small, and for example,
When InAs = 0.3, the layer thickness must be 80 [Å] or less.

Therefore, when manufacturing a strained-lattice HEMT having a double heterojunction, when InAs = 0.3, the channel width (thickness) must be selected to be 80 [Å] or less. The ground energy level in the well is greatly increased, so the two-dimensional electron concentration is small and A
There is a problem that the electron oozing into the lGaAs becomes large and the electron mobility is lowered.

The present invention is caused by a problem when a strained lattice type two-dimensional carrier gas is used in a HEMT having a single, double or multi channel structure, that is, the strained lattice type. In order to overcome the limitation on the channel width and increase the two-dimensional carrier gas concentration generated in the strained channel layer from the carrier supply layer,
Alternatively, it is possible to suppress the carrier from seeping into the channel, and as a result, to allow a large current to flow, thereby achieving high output and improvement in various characteristics.

[0013]

In the HEMT of the present invention,
A strained-lattice type two-dimensional carrier gas, which can have a large carrier concentration, is used. However, as described above, there are problems caused by the strained channel layer.

Therefore, a semiconductor layer having a lattice constant that matches the base (substrate) and the strained channel layer are alternately laminated, or a semiconductor layer made of a material having a stress opposite to that of the strained channel layer. It is fundamental to relax the limitation of the critical layer thickness in the strained channel layer by alternately stacking the strained channel layer.

As a result, the width (thickness) of the carrier transit layer, which is the channel, is artificially increased to increase the concentration of carriers transiting from the carrier supply layer to the two-dimensional carrier gas layer, or , It is possible to suppress the exudation of the carrier and allow a large current to flow, and the characteristics are improved.

Here, as a guideline for relaxing strain, strain σt due to tensile stress or strain σc due to compressive stress depending on the difference between the lattice constant of the substrate and the lattice constant of the strained channel layer. Using dt,
σt + dc · σc ~ 0 (dt and dc are layer thickness of each material)
Choose to be degree.

The above equation may be deviated to either positive or negative. That is, as long as the above equation is within the product of (stress x critical layer thickness) corresponding to the critical layer thickness at which dislocations occur, there is no problem even if the above equation does not become zero and is slightly shifted from positive to negative. In that case, some stress remains in the entire channel layer.

From the above, the HEM according to the present invention
In T (high electron mobility semiconductor device), (1) compound semiconductor strained channel layer (for example, i-In _0.3 Ga _0.7)
A substrate (for example, semi-insulating G) is formed in the As strained channel layer 3A.
Is it characterized by comprising a channel laminate (for example, channel laminate 3) into which at least one compound semiconductor strain relaxation layer (for example, i-GaAs strain relaxation layer 3B) having the same lattice constant as that of the aAs substrate 1) is introduced? Or

(2) A compound semiconductor strain relaxation layer (for example, i-In) made of a material having strain in the opposite direction to the compound semiconductor strain channel layer in the compound semiconductor strain channel layer.
A channel laminate having at least one layer of _0.05 Ga _0.95 P strain relaxation layer 13B) (for example, channel laminate 13)
Or comprising, or

(3) In the above (1), the compound semiconductor strained channel layer on the GaAs substrate is made of InGaAs and the compound semiconductor strain relaxation layer is made of GaAs, or

(4) In the above (2), the compound semiconductor strained channel layer on the GaAs substrate is made of InGaAs and the compound semiconductor strain relaxation layer is made of InGaP having an InP molar ratio of 0.5 or less. Or
Alternatively,

(5) In the above (1), the compound semiconductor strained channel layer on the InP substrate is made of InGaAs and the compound semiconductor strain relaxation layer is made of InP, or

(6) In (2), the compound semiconductor strained channel layer on the InP substrate is made of InGaAs and the compound semiconductor strain relaxation layer is InGaP or Ga.
P, or

(7) In (2), the compound semiconductor strained channel layer on the InP substrate is made of InGaAs, and the compound semiconductor strain relaxation layer is made of InAlAs having a molar ratio of AlAs of 0.5 or more. Or

(8) In (2), the compound semiconductor strained channel layer on the InP substrate is made of InGaAs, and the compound semiconductor strain relaxation layer is made of InGaAs having a GaAs molar ratio of 0.5 to 1. Or

(9) In any one of the above (1) to (8), it is characterized in that a carrier supply layer is sandwiched between a plurality of channel laminated bodies to be laminated.

[0027]

In order to increase the HEMT current by adopting the above-mentioned means, the channel width is substantially increased without generating dislocations in the crystal despite the use of the strained channel layer. As a result, the carrier transition from the carrier supply layer to the two-dimensional carrier gas layer is increased and the carrier concentration is increased, so that a large current can be passed, and even under low voltage operation, it is easy. It can realize high output, and is suitable for devices used in fields where a battery must be used as a power source, such as mobile communication fields.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a side sectional view showing an essential part of a HEMT for explaining one embodiment of the present invention. In the figure,
1 is a substrate, 2 is a buffer layer, 3 is a channel laminate, and 3A
Is a strained channel layer, 3B is a strain relaxation layer, 4 is an electron supply layer, 5 is an electrode contact layer, 5A is a recess, 6 is a gate electrode, 7S is a source electrode, and 7D is a drain electrode. The HEMT mentioned here will be referred to as a single channel structure.

The following is an example of the main data regarding each of the illustrated parts. (1) Substrate 1 Material: Semi-insulating GaAs (2) Buffer layer 2 Material: i-GaAs Thickness: 1 [μm]

(3) Channel Stack 3 A single channel structure is formed by interposing a strain relaxation layer 3B in the strained channel layer 3A. (4) Strained channel layer 3A Material: i-In _0.3 Ga _0.7 As Thickness: 8 [nm] Stress: compression (negative strain)

(5) About strain relaxation layer 3B Material: i-GaAs Thickness: 3 [nm] (6) About electron supply layer 4 Material: n-Al _0.3 Ga _0.7 As Impurity concentration: 2 × 10 ¹⁸ [cm ^{− 3} ] Thickness: 40 [nm]

(7) Regarding the electrode contact layer 5 Material: n ⁺ -GaAs Impurity concentration: 2 × 10 ¹⁹ [cm ⁻³ ] Thickness: 0.1 [μm] (8) Regarding the gate electrode 6 Material: WSi / Au Thickness: 0.2 [μm] /0.3 [μm] Gate width: 200 [μm] The gate length is 0.25 [μm].

(9) Source electrode 7S Material: AuGe / Au Thickness: 30 [nm]] / 300 [nm]

(10) Drain electrode 7D Same as source electrode 7S

A HEMT according to an embodiment of the present invention shown in FIG.
The outline of the process for manufacturing the is described. (1) Metalorganic chemical vapor deposition
ic chemical vapor deposit
(ion: MOCVD) method, and thus the substrate 1
A buffer layer 2, a channel stack 3, an electron supply layer 4, and
The electrode contact layers 5 are grown respectively.

(2) Resist process in lithography technology and reactive ion etching (reactive i) using chlorine gas as an etching gas
The recess 5A is formed in the electrode contact layer 5 by applying the on etching (RIE) method.

(3) The WSi film and the Au film are deposited on the entire surface by applying the sputtering method.

(4) A WSi film and an Au film are milled by applying a resist process in the lithography technique and an ion milling method using Ar ions to obtain a T-shaped cross-section structure, etc. A gate electrode 6 having an arbitrary cross sectional shape is formed.

(5) Au of 30 [nm] / 300 [nm] in thickness is obtained by applying the resist process, the vapor deposition method, and the lift-off method in the lithography technique.
A source electrode 7S and a drain electrode 7D made of a Ge / Au film are formed.

(6) The source electrode 7S and the drain electrode 7D are subjected to alloying heat treatment at a temperature of 400 ° C.

In the above-mentioned embodiment, n-Al _0.3 Ga _0.7 As was used as the electron supply layer 4, which was n-I.
n _0.49 Ga _0.51 P may be substituted, and to change to a hole supply layer, for example,

Material: p-Al _0.3 Ga _0.7 As Impurity concentration: 3 × 10 ¹⁸ [cm ^-3 ] Thickness: 50 [nm], and the electrode contact layer is, for example,

Material: p ⁺ -GaAs Impurity concentration: 3 × 10 ¹⁹ [cm ^-3 ] Thickness: 0.1 [μm], and the source and drain electrodes are, for example,

Material: AuZn Thickness: 300 [nm]

In this embodiment, the same material for the substrate, that is,
Since the strain relaxation layer composed of GaAs is introduced,
It does not require crystal growth of other new materials, is extremely easy to carry out, and has about twice the thickness of conventional strained channels, thus increasing the two-dimensional electron concentration. Therefore, a large current can be realized.

FIG. 2 is a sectional side view showing the essential part of a HEMT for explaining another embodiment of the present invention. The same symbols as those used in FIG. 1 represent the same parts or the same. Meaningful, and also below the buffer layer 2,
Also, the upper part from the electron supply layer is the same as in FIG.

In (A), 12 is a buffer layer and 13
Indicates a channel laminated body, 13A indicates a strained channel layer, 13B indicates a strain relaxation layer, and 14 indicates an electron supply layer.
The HEMT mentioned here will be referred to as a double channel structure.

The following is an example of the main data regarding each of the illustrated parts. (1) for the buffer layer 12 material: i-Al _0.3 Ga _0.7 As having a thickness of 500 [nm] (2) strained channel layer 13A for channel laminate 13 3 and second layers of the strain reducing layer 13B
And are laminated to form a double channel structure.

(3) Strained channel layer 13A Material: i-In _0.2 Ga _0.8 As Thickness: 10 [nm] Stress: compression (negative strain) (4) Strain relief layer 13B Material: i-In _0.05 Ga _0.95 P Thickness: 4.5 [nm] Stress: Tensile (positive strain)

(5) About electron supply layer 14 Material: n-Al _0.3 Ga _0.7 As Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 50 [nm]

In (B), 15 is an electron supply layer and 16
Is a channel stack, 16A is a strained channel layer, 16B is a strain relaxation layer, 17 is an electron supply layer, and 18 is an electron supply layer. The HEMTs mentioned here will be referred to as a multi-channel structure.
The same symbols as those used in (A) represent the same parts or have the same meanings.

The following is an example of the main data regarding each of the illustrated parts. (1) About electron supply layer 15 Material: n-In _0.49 Ga _0.51 P Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 50 [nm] (2) About channel laminate 16 Above and below strain relaxation layer 16B Are sandwiched between the strained channel layers 16A, and the pair is laminated via the electron supply layer 17 to form a multi-channel structure.

(3) Strained channel layer 16A Material: i-In _0.2 Ga _0.8 As Thickness: 8 [nm] Stress: compression (negative strain) (4) Strain relief layer 16B Material: i-In _0.2 Ga _0.8 P Thickness: 8 [nm] Stress: Tensile (positive strain)

(5) About the electron supply layer 17 Same as the electron supply layer 15 (6) About the electron supply layer 18 Material: n-In _0.49 Ga _0.51 P Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 40 [Nm]

In each of the examples shown in FIG. 2, since the strain relaxation layer made of i-InGaP having a positive strain is used, the strain of the strained channel layer is relaxed by the alternating positive and negative strains, and the dislocation is generated. It does not occur, and in each case, compared with the case of a single layer InGaAs channel layer,
The layer thickness can be increased by 2 to 3 times or more, and
The two-dimensional carrier gas concentration can also be increased, and can be increased from 20% to about double.

FIG. 3 is a cutaway side view of the essential part of a HEMT for explaining another embodiment of the present invention. In the figure, 21 is a substrate, 22 is a buffer layer, 23 is a channel laminated body, 23A is a strained channel layer, 23B is a strain relaxation layer,
24 is an electron supply layer, 25 is an electrode contact layer, 25A is a recess, 26 is a gate electrode, 27S is a source electrode, 27
D shows the drain electrodes, respectively. The HEMTs mentioned here also have a single channel structure.

The following is an example of the main data regarding each of the illustrated parts. (1) About substrate 21 Material: semi-insulating InP (2) About buffer layer 22 Material: i-In _0.52 Al _0.48 As Thickness: 0.1 [μm]

(3) Channel laminated body 23 A single chill structure is formed by interposing a strain relaxation layer 23B in the strained channel layer 23A. (4) Strained channel layer 23A Material: i-In _0.7 Ga _0.3 As Thickness: 10 [nm] Stress: Compression (negative strain)

(5) Strain relaxation layer 23B Material: i-In _0.2 Ga _0.8 As Thickness: 8 [nm] Stress: tensile (positive strain) (6) Electron supply layer 24 Material: n-In _0.52 Al _0.48 As impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 40 [nm]

(7) Electrode contact layer 25 Material: n ⁺ -In _0.53 Ga _0.47 As Impurity concentration: 2 × 10 ¹⁹ [cm ⁻³ ] Thickness: 0.1 [μm] (8) Material for the gate electrode 26 : Al Thickness: 0.25 [μm] Gate width: 100 [μm]

(9) Source electrode 27S Material: AuGe Thickness: 300 [nm]

(10) Drain electrode 27D Same as source electrode 27S

FIG. 4 is a cutaway side view of an essential part showing a HEMT for explaining another embodiment of the present invention. The same symbols as those used in FIG. 3 represent the same parts or the same. It has meaning, and the part below the buffer layer 22 and the part above the uppermost electron supply layer are the same as those in FIG.

In (A), 33 is a channel laminate,
33A is a strained channel layer, 33B is a strain relaxation layer, and 34 is an electron supply layer. In addition, H mentioned here
EMT is a double channel structure.

The following is an example of the main data relating to the illustrated parts. (1) Regarding the channel laminate 33: three strained channel layers 33A and two strain relaxation layers 33B
And are laminated to form a double channel structure.

(3) Strained channel layer 33A Material: i-In _0.7 Ga _0.3 As Thickness: 7 [nm] Stress: compression (negative strain) (4) Strain relief layer 33B Material: i-GaAs Thickness: 4 [nm] stress: tensile (positive strain)

(5) About electron supply layer 34 Material: n-In _0.52 Al _0.48 As Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 40 [nm]

In this embodiment, the material of the strain relaxation layer 33B is i-GaAs, which is i-In _0.1 G.
a _0.9 As can be substituted, in which case the thickness is 6
[Nm] is recommended.

In (B), 35 is an electron supply layer and 36
Indicates a channel laminated body, 36A indicates a strained channel layer, 36B indicates a strain relaxation layer, and 37 indicates an electron supply layer.
The HEMT described here has a multi-channel structure, and the same symbols as those used in FIGS. 3 and 4A represent the same parts or have the same meanings.

The following is an example of the main data regarding each of the illustrated parts. (1) About electron supply layer 35 Material: n-In _0.52 Al _0.48 As Impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 50 [nm] (2) About channel laminated body 36 Above and below the strain relaxation layer 36B Are sandwiched between the strained channel layers 36A, and the pair is laminated with the electron supply layer 37 interposed therebetween to form a multi-channel structure.

(3) Strained channel layer 36A Material: i-In _0.65 Ga _0.35 As Thickness: 10 [nm] Stress: compression (negative strain) (4) Strain relief layer 36B Material: i-GaP Thickness: 3 [nm] stress: tensile (positive strain)

(5) Regarding electron supply layer 37 Material: n-In _0.52 Al _0.48 As Impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 40 [nm]

In this embodiment, i-GaP is used as the material of the strain relaxation layer 36B, which is i-In _0.49 G.
a _0.51 As can be substituted, in which case the thickness is 5
[Nm] is preferable, and i-GaAs can be substituted. In that case, the thickness is preferably 4 [nm].

In each of the examples shown in FIG. 4, since the strain relaxation layer made of i-GaP having a positive strain is used, the strain of the strained channel layer is relaxed by the alternating strain of positive and negative, and the dislocations are generated. It does not occur, and in any case,
Compared with the case of a single-layer InGaAs channel layer, the layer thickness can be increased by 2 to 3 times or more, and therefore the two-dimensional carrier gas concentration can be increased.
It can be increased from [%] to about twice.

[0075]

In the high electron mobility semiconductor device according to the present invention, the compound semiconductor strained channel layer has the same lattice constant as that of the substrate or has a strain in the opposite direction to the compound semiconductor strained channel layer. A channel laminated body having at least one compound semiconductor strain relaxation layer made of a material introduced therein is provided.

By adopting the above structure, in order to increase the current of the HEMT, the channel width is substantially increased without generating dislocations in the crystal although the strained channel layer is used. As a result, the carrier transition from the carrier supply layer to the two-dimensional carrier gas layer is increased and the carrier concentration is increased, so that a large current can be passed, and even under low voltage operation, it is easy. High output can be realized, such as mobile communication field,
It is suitable for equipment used in the field where a battery must be used as a power source.

[Brief description of drawings]

FIG. 1 is a HEM for explaining an embodiment of the present invention.
It is a principal part cutting side view showing T.

FIG. 2 is an HE for explaining another embodiment of the present invention.
It is a principal part cutting side view showing MT.

FIG. 3 is an HE for explaining another embodiment of the present invention.
It is a principal part cutting side view showing MT.

FIG. 4 is a HE for explaining another embodiment of the present invention.
It is a principal part cutting side view showing MT.

[Explanation of symbols]

 1 substrate 2 buffer layer 3 channel laminated body 3A strained channel layer 3B strain relaxation layer 4 electron supply layer 5 electrode contact layer 5A recess 6 gate electrode 7S source electrode 7D drain electrode 21 substrate 22 buffer layer 23 channel laminated body 23A strained channel layer 23B Strain relief layer 24 Electron supply layer 25 Electrode contact layer 25A Recess 26 Gate electrode 27S Source electrode 27D Drain electrode

Claims (9)

[Claims] 1. A high electron mobility semiconductor device comprising a channel stack body in which at least one compound semiconductor strain relaxation layer having a lattice constant equal to that of a substrate is introduced into a compound semiconductor strain channel layer. 2. A compound semiconductor strained channel layer is provided with a channel layered body having at least one compound semiconductor strain relaxation layer made of a material having strain opposite to that of the compound semiconductor strained channel layer. High electron mobility semiconductor device. 3. The high electron mobility semiconductor device according to claim 1, wherein the compound semiconductor strain channel layer on the GaAs substrate is made of InGaAs and the compound semiconductor strain relaxation layer is made of GaAs. 4. The compound semiconductor strained channel layer on the GaAs substrate is made of InGaAs, and the compound semiconductor strained relaxation layer is made of InGaP having a molar ratio of InP of 0.5 or less. High electron mobility semiconductor device. 5. The high electron mobility semiconductor device according to claim 1, wherein the compound semiconductor strained channel layer on the InP substrate is made of InGaAs, and the compound semiconductor strain relaxation layer is made of InP. 6. The high electron mobility semiconductor device according to claim 2, wherein the compound semiconductor strain channel layer on the InP substrate is made of InGaAs and the compound semiconductor strain relaxation layer is made of InGaP or GaP. 7. The compound semiconductor strain channel layer on the InP substrate is made of InGaAs, and the compound semiconductor strain relaxation layer is made of InAlAs having a molar ratio of AlAs of 0.5 or more. High electron mobility semiconductor device. 8. A compound semiconductor strained channel layer on an InP substrate is made of InGaAs, and a compound semiconductor strained relaxation layer has a GaAs molar ratio of 0.5 to 1 InGaA.
The high electron mobility semiconductor device according to claim 2, wherein the high electron mobility semiconductor device is made of s. 9. A carrier supply layer is sandwiched between a plurality of channel laminated bodies to be laminated.
The high electron mobility transistor according to claim 1.