JP3237459B2 - Semiconductor wafer and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer and a semiconductor device with improved carrier running characteristics and carrier leakage prevention performance.

[0002]

2. Description of the Related Art FIG. 7 is a schematic sectional view showing a conventional epitaxial wafer structure for a field effect transistor (FET) and the structure of an FET manufactured from the wafer.
The FET epitaxial wafer shown in FIG. 7A has a semi-insulating GaAs substrate 1 on which high resistance or p ^- type Al _x
A Ga _1-x As buffer layer 2 (0 <x ≦ 1) is formed, and an n-type GaAs operation layer 3 is formed thereon. In the FET shown in FIG. 7B, a source electrode 4, a gate electrode 5, and a drain electrode 6 are further formed on the surface of the n-type GaAs operation layer 3 of the wafer.

[0003] In such FETs, high output, high breakdown voltage,
The higher efficiency and lower noise improve the carrier traveling characteristics in the operation layer 3, particularly the carrier traveling characteristics near the interface with the buffer layer 2, and prevent the leakage of carriers to the buffer layer 2 (that is, leakage current). Achieved and improved by doing

For this reason, AlGaAs which is a material having a larger band gap than the GaAs operation layer 3 is used for the buffer layer 2.
And a leakage current is suppressed by using a barrier formed by the energy difference (US Pat. No. 4,157,556). However, in this structure, the traveling characteristics of the carriers in the operation layer 3, particularly the traveling characteristics of the carriers near the interface with the buffer layer 2, are different from those of the Al _x Ga _{1 -x} As buffer layer 2 and the n-type GaAs operation layer 3. It gets worse depending on the situation.

In order to improve the carrier traveling characteristics near the interface, the following techniques have been proposed.

(1) The carrier running characteristics are deteriorated in the above-mentioned US patents because of the distortion caused by the heterogeneous junction. To prevent the deterioration of the high frequency characteristics caused by the distortion, the wafer structure shown in FIG. , And the FE in FIG.
As shown in the T structure, the Al _x Ga _{1 -x} As buffer layer 7
And a GaAs buffer layer 8 are alternately stacked, and a semiconductor superlattice structure is used as the buffer layer 9 (Japanese Patent Publication No. Sho 62-141).
No. 05).

(2) In order to improve the crystallinity, the buffer layer is composed of a semiconductor layer A having a larger band gap than the operation layer,
The semiconductor layer A may be composed of alternating layers with the semiconductor layer B having a larger band gap than the semiconductor layer A, or may be composed only of the semiconductor layer A or the semiconductor layer B, and the mixed crystal composition ratio of the semiconductor layer A and the semiconductor layer B may be adjusted by the substrate. From the working layer to the working layer.

[0008]

However, the above-mentioned prior art has the following problems.

(1) In a FET using a semiconductor superlattice structure as a buffer layer, a miniband is formed due to the overlapping of wave functions of electrons generated by the superlattice structure.
It has been found that there is a problem that the energy barrier of the superlattice buffer layer with respect to the operation layer is effectively reduced, and the effect of suppressing the leakage current is significantly reduced.

(2) In the method of gradually decreasing the mixed crystal composition ratio of the semiconductor layer A and the semiconductor layer B constituting the buffer layer, the band gap is also reduced, so that the energy barrier (ΔE) between the buffer layer and the operating layer is reduced. _c , ΔE _v ) is reduced or eliminated, so that the effect of suppressing current leakage is lost.

An object of the present invention is to solve the above-mentioned problems of the prior art by adopting a novel buffer structure, to prevent an increase in leak current due to mini-band formation and a decrease in energy barrier, and to further improve carrier traveling characteristics. It is to provide a semiconductor wafer and a semiconductor device in which are improved.

[0012]

As shown in FIG. 1 (a), a semiconductor wafer according to the present invention comprises a semiconductor wafer in which a semiconductor substrate 1, a buffer layer 16 and an operation layer 3 are sequentially stacked. The semiconductor layers A15, 13, 11 having a larger band gap than the operation layer 3, and the semiconductor layers B14, 1 having a larger band gap than the semiconductor layer A.
2, 10 from the semiconductor substrate 1 toward the operation layer 3
A graded-type alternating laminated structure in which alternate layers 25 of the semiconductor layer A and the semiconductor layer B are alternately laminated at least twice or more while the thickness of each of the semiconductor layer A and the semiconductor layer B is sequentially reduced. It is. Here, the alternate layers 25 are stacked at least twice or more because the energy barrier for the operation layer is provided a plurality of times, so that the flow of electrons from the operation layer to the buffer layer, that is, the current leakage is more effectively prevented. This is because the crystal growth disorder due to the difference in lattice constant between the operation layer and the substrate and the semiconductor layer A and the semiconductor layer B cannot be reduced once.

In the semiconductor wafer of the present invention, GaAs is used for the operation layer, and Al _y Ga _{1 -y} As (0 <y <1) and the semiconductor layer B are used for the semiconductor layers A and B of the buffer layer.
Al _x Ga _1-x As (0 <y <x ≦ 1)
In _y Ga _1-y As (0 <y ≦ 1) is used for the operation layer, and GaAs and A are used for the semiconductor layers A and B of the buffer layer.
using l _x Ga _1-x As (0 <x <1), or
_{l x Ga 1-x As (} 0 <x <1) and Al _y Ga _1-y A
s (0 <x <y ≦ 1), or In _y Ga
_{Using 1-y} As (0 <y ≦ 1), In _z Al _1-z As (0 ≦ z <1) was added to the semiconductor layers A and B of the buffer layer.
1), a combination of any two material layers of InP, InAlAsP, and InGaAsP is used;
With _{As, Ga m In 1-m} P in the semiconductor layer A and the semiconductor layer B of the buffer layer (0 <m ≦ 1) and Al _n In _1-n P
(0 <n ≦ 1) may be used.

In the semiconductor wafer of the present invention, the operating layer may be composed of two or more semiconductor layers, or may have an undoped or low carrier concentration high breakdown voltage having a band gap above the operating layer over the operating layer. A layer or an ohmic contact layer may be formed, or both may be formed in the order of a high breakdown voltage layer and an ohmic contact layer.

Further, in the semiconductor wafer of the present invention, the conductivity type of the operation layer is n-type, and the conductivity type of each layer constituting the buffer layer is p ^- type or high resistance type. The buffer layer may be p-type and the conductivity type of each layer constituting the buffer layer may be n ⁻ type or high resistance type.

A semiconductor device according to the present invention is constituted by any of the semiconductor wafers described above. For example, as shown in FIG. , A gate electrode 5 and a drain electrode 6.

[0017]

For example, as in the semiconductor wafer of the present invention shown in FIG. 1, the superlattice structure is not formed by changing the thickness of the alternating layers 25 of the semiconductor layers A and B to eliminate the periodicity. , Do not form mini-bands. Then, no current leak occurs due to the exudation of the wave function. As a result, higher breakdown voltage and lower noise of the semiconductor device are brought about.

Although a bandgap difference is provided between the semiconductor layer A and the semiconductor layer B, if the bandgap of each layer is kept constant without changing, the energy barrier itself between the buffer layer 16 and the operation layer 3 becomes close to the interface. However, since it does not change, no current leak occurs.

Further, by providing the buffer layer with an energy barrier with the operating layer a plurality of times in the thickness direction, the flow of electrons from the operating layer to the buffer layer, that is, the current leakage can be more effectively suppressed. .

Further, the thickness of the semiconductor layer A and the semiconductor layer B is gradually reduced from the substrate 1 side toward the operation layer 3 so that the operation layer 3 and the substrate 1 are alternately formed with the semiconductor layer A and the semiconductor layer B. The disorder of crystal growth formed by the difference in lattice constant from 25 gradually decreases. Therefore, the crystallinity near the interface between the operation layer 3 and the buffer layer 16 is improved, and the carrier traveling characteristics of the operation layer 3 are greatly improved. As a result, higher output, higher efficiency, and lower noise of the semiconductor device are achieved, and the high-frequency characteristics are significantly improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the semiconductor wafer and the semiconductor device of the present invention are applied to an epitaxial wafer for FET and FET will be described below.

FIG. 2 is a schematic sectional view showing the structure of the FET epitaxial wafer of the first embodiment. FIG. 3 is a diagram relating to an FET fabricated from the wafer of FIG.
FIG. 1 is a schematic cross-sectional view showing a configuration of an FET, FIG. 2B is a structural view of an energy band thereof, and FIG. 1C is a view showing a composition ratio x.

As shown in FIG. 2, an epitaxial wafer for FET comprises a buffer layer 1 on a semi-insulating GaAs substrate 1.
6 and an n-type GaAs operation layer 3 are sequentially stacked. In the FET, a source electrode 4, a gate electrode 5, and a drain electrode 6 are provided on the surface of the n-type GaAs operation layer 3 as shown in FIG. Things.

The buffer layer 16 is composed of the n-type GaAs operation layer 3
P ⁻ type A, which is a semiconductor layer A having a larger band gap
l _y Ga _1-y As layer 18 and the (0 <y <1), a large semiconductor layer B further bandgap than this p ^- type A
The l _x Ga _1-x As layer 17 (0 <y <x ≦ 1) is transferred from the semi-insulating GaAs substrate 1 toward the operation layer 3 by the _Aly G
While the thicknesses of the a _1-y As layer 18 and the Al _x Ga _1-x As layer 17 are sequentially reduced, the Al _y Ga _1-y As layer 18 is reduced.
And an alternate layer 25 of Al _x Ga _{1 -x} As layer 17 are alternately stacked five times in a graded-type alternate stacked structure.

Here, the carrier concentration of the n-type GaAs operation layer 3 is 2 × 10 ¹⁷ cm ⁻³ . The Al composition ratio x of the p ⁻ -type Al _x Ga _{1 -x} As layer 17 in the buffer layer 16 is 0.3, the carrier concentration is 5 × 10 ¹⁵ cm ⁻³ , and the p ⁻ -type The Al composition ratio y of the Al _y Ga _1-y As layer 18 is 0.2, and the carrier concentration is 2 × 10 ¹⁵ cm ⁻³ . Further, each of the p ⁻ -type AlGaAs layers 17 and 18 has
The thickness of the layers is from GaAs substrate 1 to working layer 3
0.2 μm, 0.1 μm, 0.05 μm, 0.
04μm, 0.03μm, 0.02μm, 0.01μ
m, 0.005 μm, 0.0025 μm, 0.0012
μm.

With such a structure, the leak current is suppressed by the interface between the operation layer 3 and the buffer layer 16 having the graded thickness alternately laminated structure and the energy barrier formed on the buffer layer 16. In addition, since there is no periodicity of the thickness as in the conventional superlattice structure buffer layer, a mini band is not formed, and therefore, current leakage due to exudation of a wave function does not occur. Further, by using the graded-type alternating laminated structure for the buffer layer 16, the disorder of the crystallinity at the interface between the operation layer 3 and the buffer layer 16 caused by the heterogeneous junction can be further reduced, and the carrier traveling characteristics of the operation layer 3 can be reduced. And the electrical characteristics near the interface can be improved. As a result, the high-frequency characteristics of the FET can be significantly improved, and it is particularly effective as a device for portable electronic devices (mobile phones, portable information terminals, etc.) requiring low voltage operation and low power consumption. I do.

FIG. 4 shows an operation layer 2 having different carrier concentrations.
Example 2 is shown as a layer. n-type GaAs first operation layer 2
1. An n-type GaAs second operation layer 20 is stacked on the substrate 1, and an n ⁺ -type GaAs ohmic contact layer 19 is further provided thereon. FIG. 4A is a schematic diagram showing the structure of an epitaxial wafer for FET. FIG. 4B is a schematic cross-sectional view showing the configuration of an FET in which the source electrode 4 and the drain electrode 6 are provided on the ohmic contact layer 19 of the wafer and the gate electrode 5 is provided on the second operation layer 20, respectively. .

Here, the carrier concentration of the n ⁺ -type GaAs ohmic contact layer 19 is 2 × 10 ¹⁸ cm ⁻³ ,
The carrier concentration of the type GaAs first and second operation layers 20 and 21 is 2 × 10 ¹⁶ cm ⁻³ and 5 × 10 ¹⁷ cm ⁻³ , respectively. The Al composition ratio x of the p ⁻ type Al _x Ga _{1 -x} As layer 17 in the buffer layer 16 is 0.3, the carrier concentration is 2 × 10 ¹⁵ cm ⁻³ , and the p ⁻ type Al _y in the buffer layer 16 is Ga _1-y As layer 1
8 has an Al composition ratio y of 0.1 and a carrier concentration of 5 × 10 ¹⁴
cm ^-3 .

FIG. 5 shows a third embodiment, in which n-type Ga
An Al _p Ga _{1 -p} As layer 22 having a larger energy band gap is provided on the As operation layer 23, and n ⁺
FIG. 5A is a schematic cross-sectional view showing the structure of an epitaxial wafer for FET, and FIG. 5B is a diagram showing the structure of an FET in which electrodes are provided on the surface of the wafer. It is a schematic cross section.

Here, the carrier concentration of the n ⁺ -type GaAs ohmic contact layer 19 is 3 × 10 ¹⁸ cm ⁻³ and Al _p G
The a _{1 -p} As layer 22 has an Al composition ratio x of 0.5, a low carrier concentration of 1 × 10 ¹⁶ cm ⁻³ or less, a high resistance, and n-type GaAs.
The carrier concentration of the s operation layer 23 is 3 × 10 ¹⁷ cm ⁻³ , the Al composition ratio x of the p ⁻ -type Al _x Ga _{1 -x} As layer 17 in the buffer layer 16 is 0.25, and the carrier concentration is 1 × 10 ^16. High resistance at a low concentration of less than cm ^-3 , p ^- type Al _y G in the buffer layer 16
The Al composition ratio y of the a _1-y As layer 18 is 0.15, the carrier concentration is 1 × 10 ¹⁶ cm ⁻³ or less, and the resistance is high at a low concentration. The p ^- type Al _x Ga _{1 -x} As layer 17 and the p ^- type Al _y G
The stacking order of the a _1-y As layer 18 may be reversed.

FIG. 6 is a schematic sectional view showing a fourth embodiment, in which an FET in which a high-purity spacer layer 24 is inserted between the operation layer 3 and the buffer layer 16. The spacer layer 24 is inserted because the p ^- type Al _x Ga _{1 -x} As layer 17 and the n-type G
This is for eliminating disturbance at the interface with the aAs operation layer 3. In this case, operation layer 3 is n-type GaAs layer, the spacer layer 24 is high purity undoped GaAs layer, the buffer layer 16 p ^- type Al _x Ga _1-x As layer 17 and the p ^- type Al _y Ga _1-y As
The thickness of the layer 18 is a graded type alternately laminated structure.

Here, the carrier concentration of the n-type GaAs operation layer 3 is 1.5 × 10 ¹⁷ cm ⁻³ , the carrier concentration of the high-purity GaAs spacer layer 24 is 2 × 10 ¹³ cm ⁻³ , and the buffer layer 1
6, the Al composition ratio x of the p ⁻ -type Al _x Ga _{1 -x} As layer 17
Is 0.25, the carrier concentration is low and the resistance is high, and the Al composition ratio y of the p ^- type Al _y Ga _1-y As layer 18 in the buffer 16 layer is 0.15. The carrier concentration is low and the resistance is high. is there.

In each of the above embodiments, an FET or an epitaxial wafer for FET using GaAs as an active layer has been described. However, the present invention is not limited to GaAs, and other compound semiconductors such as InP and InGa
It goes without saying that the same effect is exerted also for the FET using As and InAs as the operation layers. Also, the case where the operation layer is of the n-type has been described.
The same applies to the ET or the complementary FET-IC sharing the n-type operation layer and the p-type operation layer.
Further, the present invention can be applied to an operation layer having a planar doped layer and an FET having a non-alloy ohmic contact layer.

Further, the epitaxial wafer for FET of the present invention can be easily formed by a metal organic chemical vapor deposition method or a molecular beam epitaxy method. In addition, FETs are formed from the wafer thus formed by a general semiconductor microfabrication process.
Can be made.

[0035]

According to the semiconductor wafer of the present invention, as the buffer layer, the thickness of the semiconductor layer A having a larger band gap than the operation layer and the thickness of the semiconductor layer B larger than the band gap of the semiconductor layer A are sequentially reduced. However, since a thickness graded type alternately laminated structure in which these layers are alternately laminated at least twice or more is used, no current leaks from the operation layer to the buffer layer, and the gap between the operation layer and the buffer layer Since the interface is not disturbed, the carrier traveling characteristics of the operation layer are improved.

Further, when a high breakdown voltage layer having a band gap or more and an ohmic contact layer are formed on the operation layer, or when both the high breakdown voltage layer and the ohmic contact layer are formed in this order, a higher breakdown voltage layer is formed. And high output.

In the case where a semiconductor wafer using a graded-type thickness alternately laminated structure is used for the buffer layer,
High output, high withstand voltage, high efficiency, low noise can be achieved,
High frequency characteristics are improved.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic diagrams showing the principle of application of the present invention to an FET, wherein FIG. 1A is a cross-sectional view of an FET wafer, and FIG.
FIG.

FIG. 2 is a schematic cross-sectional view showing a configuration of an FET epitaxial wafer of a first embodiment.

FIGS. 3A and 3B are schematic diagrams relating to the configuration of the FET of the first embodiment, in which FIG. 3A is a cross-sectional view of the FET, FIG. 3B is an energy band structure diagram thereof, and FIG. It is a figure which shows the change of a layer thickness direction.

FIGS. 4A and 4B are schematic diagrams relating to the configuration of the FET according to the second embodiment, in which FIG. 4A is a cross-sectional view of an FET epitaxial wafer, and FIG.

5A and 5B are schematic diagrams relating to the configuration of the FET according to the third embodiment, in which FIG. 5A is a cross-sectional view of an FET epitaxial wafer, and FIG. 5B is a cross-sectional view of the FET.

FIG. 6 is a schematic sectional view showing a configuration of an FET according to a fourth embodiment.

7A and 7B are schematic views showing a configuration of a conventional FET, wherein FIG. 7A is a cross-sectional view of an epitaxial wafer for FET,
(B) is a sectional view of the FET.

FIGS. 8A and 8B are schematic views showing a configuration of a conventional FET having a superlattice structure buffer, wherein FIG. 8A is a cross-sectional view of an epitaxial wafer for FET, and FIG. 8B is a cross-sectional view of the FET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Buffer layer 3 Operation layer 4 Source electrode 5 Gate electrode 6 Drain electrode 10, 12, 14 Semiconductor layer B 11, 13, 15 Semiconductor layer A 16 Thickness buffer layer of graded type alternate lamination structure 17 p ^- type Al _x Ga _{1 -x} As layer 18 p ⁻ -type Al _y Ga _{1 -y} As layer 19 n ⁺ -type GaAs ohmic contact layer 20 n-type GaAs second operation layer 21 n-type GaAs first operation layer 22 Al _p Ga _{1- p} As layer 23 n-type GaAs operation layer 24 undoped GaAs spacer layer 25 alternate layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-150016 (JP, A) JP-A-2-231733 (JP, A) JP-A-4-725 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/812 H01L 21/20

Claims (9)

(57) [Claims] 1. A semiconductor wafer in which a semiconductor substrate, a buffer layer, and an operation layer are sequentially laminated , and the buffer layer includes a semiconductor layer A having a larger band gap than the operation layer, and a band gap larger than the semiconductor layer A. A semiconductor layer B having a larger thickness from the semiconductor substrate to the operation layer, while reducing the thickness of each of the semiconductor layers A and B sequentially by at least two layers. In a semiconductor wafer configured with a graded-type alternating lamination structure, which is alternately laminated more than once ,
The semiconductor layer A of the buffer layer and the semiconductor layer are formed using GaAs.
The body layer _{B Al y Ga 1-y As} (0 <y <1) and Al _x G
A semiconductor wafer using a _1-x As (0 <y <x ≦ 1) . 2. A semiconductor device comprising : a semiconductor substrate, a buffer layer and an operation layer;
A next stacked semiconductor wafer and the buffer
The layer is a semiconductor layer having a larger band gap than the above-mentioned operation layer
A and a half having a larger band gap than the semiconductor layer A.
Conductor layer B from the semiconductor substrate to the operation layer.
The thickness of each of the semiconductor layers A and B is sequentially reduced.
Meanwhile, the number of alternating layers of the semiconductor layer A and the semiconductor layer B is reduced.
Thickness graded type alternately stacked two or more times alternately
In a semiconductor wafer with a layered structure,
Using In _y Ga _1-y As (0 <y ≦ 1), the buffer
GaAs and Al _x G on the semiconductor layers A and B
a _1-x As (0 <x <1) or Al _x Ga
_1-x As and Al _y Ga _1-y As use a (0 <x <y ≦ 1 )
A semiconductor wafer, 3. The semiconductor substrate, a buffer layer and an operation layer are sequentially arranged.
A next stacked semiconductor wafer and the buffer
The layer is a semiconductor layer having a larger band gap than the above-mentioned operation layer.
A and a half having a larger band gap than the semiconductor layer A.
Conductor layer B from the semiconductor substrate to the operation layer.
The thickness of each of the semiconductor layers A and B is sequentially reduced.
Meanwhile, the number of alternating layers of the semiconductor layer A and the semiconductor layer B is reduced.
Thickness graded type alternately stacked two or more times alternately
In a semiconductor wafer with a layered structure,
Using In _y Ga _1-y As (0 <y ≦ 1), the buffer
In _z Al _1-z As
(0 ≦ z <1), InP, InAlAsP, InGaAs
that we were using a combination of any two of the material layers of sP
Characteristic semiconductor wafer. 4. The semiconductor substrate, a buffer layer and an operation layer are arranged in this order.
A next stacked semiconductor wafer and the buffer
The layer is a semiconductor layer having a larger band gap than the above-mentioned operation layer.
A and a half having a larger band gap than the semiconductor layer A.
Conductor layer B from the semiconductor substrate to the operation layer.
The thickness of each of the semiconductor layers A and B is sequentially reduced.
Meanwhile, the number of alternating layers of the semiconductor layer A and the semiconductor layer B is reduced.
Thickness graded type alternately stacked two or more times alternately
In a semiconductor wafer with a layered structure,
The semiconductor layer A of the buffer layer and the semiconductor layer are formed using GaAs.
Ga _m In _1-m P body layer B (0 <m ≦ 1) and Al _n an In
Semiconductor characterized by using _1-n P (0 <n ≦ 1)
Wafer. 5. The operation layer is composed of two or more semiconductor layers.
5. The semiconductor wafer according to claim 1, wherein
Eha. 6. A bandgap for said operating layer on said operating layer.
Undoped with a band gap greater than the gap
Is a high withstand voltage layer with low carrier concentration or ohmic contact
A high-voltage layer or an ohmic layer.
6. The semiconductor wafer according to claim 1, wherein said semiconductor wafer is formed in the order of a contact layer . 7. The operating layer has a conductivity type of n-type.
The conductivity type of each layer constituting the buffer layer is p ^- type or
7. The semiconductor wafer according to claim 1, which is of a high resistance type . 8. The semiconductor device according to claim 8, wherein the conductivity type of the operation layer is p-type.
The conductivity type of each layer constituting the buffer layer is n ^- type or
7. The semiconductor wafer according to claim 1, which is of a high resistance type . 9. The half according to any one of claims 1 to 8
A semiconductor device comprising a conductor wafer, wherein
Source, gate and drain electrodes on the wafer surface
Semiconductor device provided.