JPH02205029A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02205029A JPH02205029A JP2421289A JP2421289A JPH02205029A JP H02205029 A JPH02205029 A JP H02205029A JP 2421289 A JP2421289 A JP 2421289A JP 2421289 A JP2421289 A JP 2421289A JP H02205029 A JPH02205029 A JP H02205029A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- nitride film
- silicon nitride
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 210000003323 beak Anatomy 0.000 abstract 1
- 230000008569 process Effects 0.000 description 5
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.
従来の技術
第４図は従来の半導体装置の製造方法における素子分離
領域の一般的な形成工程を示すものであり、従来の方法
では、バーズビークと呼ばれる酸化膜の入り込みが生じ
るため、マスク上でのトランジスタのゲート幅と実際の
それとに差が生じていた。Conventional technology Figure 4 shows a general process for forming an element isolation region in a conventional semiconductor device manufacturing method. There was a difference between the gate width of the transistor and the actual width.
発明が解決しようとする課題
上記のように従来法ではトランジスタのゲート幅がマス
ク上での寸法から大きくずれる等の問題から半導体装置
の微細化・高集積化を妨げる要因となっていた。本発明
ではかかる点に鑑み、バーズビークを防ぎ素子分離のた
めの酸化膜を厚くすることを可能としより微細化され、
高集積化された半導体装置の製造方法を提供することを
目的とする。Problems to be Solved by the Invention As mentioned above, in the conventional method, problems such as the gate width of the transistor largely deviating from the dimension on the mask have become factors that hinder miniaturization and high integration of semiconductor devices. In view of this point, the present invention makes it possible to thicken the oxide film for preventing bird's beak and for element isolation, and to achieve a finer structure.
An object of the present invention is to provide a method for manufacturing a highly integrated semiconductor device.
課題を解決するための手段
本発明は、ＭＯＳトランジスタを形成する領域を所定の
深さ堀りさげておき、その従来法と同様の工程により素
子分離領域を形成することにより、バーズビークのない
設計寸法どおりのトランジスタを得るための半導体装置
の製造方法である。Means for Solving the Problems The present invention enables design dimensions without bird's beak by digging down a region where a MOS transistor is to be formed to a predetermined depth and forming an element isolation region by the same process as the conventional method. This is a method of manufacturing a semiconductor device to obtain a transistor as specified.
作用
本発明悼□前記した工程を有することにより、段差を形
成し横方向にシリコン基板表面が酸化されるのを防ぎ、
バーズビークの発生を抑えることが可能となる。Effects of the present invention By having the above-described steps, steps are formed to prevent the surface of the silicon substrate from being oxidized in the lateral direction,
It becomes possible to suppress the occurrence of bird's beak.
実施例
第１図は、本発明第１の実施例における半導体装置の製
造方法を示すものである。第１図に示すようにシリコン
基板上のＭＯＳトランジスタを形成する領域を所定の深
さ堀りさげる。その後酸化時のマスクとなるシリコン窒
化膜を形成し、不必要な部分を取り除く、そして素子分
離に必要な不純物を導入する。次にシリコン窒化膜でお
おわれていない部分を酸化することにより素子分離領域
が形成される。第２図は、本発明の第２の実施例におけ
る半導体装置の製造方法で、第１の実施例における第１
図ｂ）の工程に変わる工程を示すものである。第２図に
示すようにシリコン窒化膜の下、渥り下げた溝の底部に
のみひずみを緩和するためのシリコン酸化膜を形成して
おいて、シリコン窒化膜のない所を酸化する。第３図は
、本発明の第３の実施例における半導体装置の製造方法
で、第２の実施例と同様、第１の実施例、第１のｂ）の
工程にかわる工程を示す。第３図に示すようにシリコン
窒化膜の下部に、掘り下げた溝の表面全体をおおうよう
に酸化膜を形成しておいて、シリコン窒化膜のない所を
酸化する。Embodiment FIG. 1 shows a method for manufacturing a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, a region on a silicon substrate where a MOS transistor is to be formed is dug to a predetermined depth. After that, a silicon nitride film is formed to serve as a mask during oxidation, unnecessary portions are removed, and impurities necessary for element isolation are introduced. Next, a device isolation region is formed by oxidizing the portion not covered with the silicon nitride film. FIG. 2 shows a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
This figure shows an alternative process to the process in Figure b). As shown in FIG. 2, a silicon oxide film is formed under the silicon nitride film only at the bottom of the downward groove to relieve strain, and the areas where there is no silicon nitride film are oxidized. FIG. 3 shows a method for manufacturing a semiconductor device according to a third embodiment of the present invention, and shows a step in place of step 1b) of the first embodiment, similar to the second embodiment. As shown in FIG. 3, an oxide film is formed below the silicon nitride film so as to cover the entire surface of the trench, and the areas where the silicon nitride film is not present are oxidized.
発明の詳細
な説明したように本発明によれば、従来の製造方法に少
し工程を加えるだけで実現でき、掘り下げ量を調節する
ことにより従来より深い素子分離が可能となり、半導体
装置の高集積化におけるその実用的効果は大きいDETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention can be realized by adding a few steps to the conventional manufacturing method, and by adjusting the amount of digging, it is possible to achieve deeper element isolation than in the past, resulting in higher integration of semiconductor devices. Its practical effect on
第１図は、本発明における一実門例の半導体装置の製造
方法の概略工程断面図、第２図および第３図は、本発明
の他の実施例の半導体装置の製造方法の概略工程におけ
る各々一つの工程の断面図、□４Ａ２、従来、）工導体
′装置あ製造方法−概略１胃
径断面図である。
１・・・・シリコン基板、２・・・・シリコン窒化膜、
３・・・・不純物領域、４・・・・シリコン酸化膜。FIG. 1 is a schematic process cross-sectional view of a method of manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 2 and 3 are schematic process steps of a method of manufacturing a semiconductor device according to another embodiment of the present invention. A cross-sectional view of one process, □4A2, conventional method for manufacturing a conductor' device - a schematic cross-sectional view of one stomach diameter. 1... Silicon substrate, 2... Silicon nitride film,
3... Impurity region, 4... Silicon oxide film.
Claims (1)
所定の深さに堀りさげる工程と、この後に素子分離領域
を形成する工程を特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising the steps of excavating a region on a silicon substrate in which a MOS transistor is to be formed to a predetermined depth, and then forming an element isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2421289A JPH02205029A (en) | 1989-02-02 | 1989-02-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2421289A JPH02205029A (en) | 1989-02-02 | 1989-02-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02205029A true JPH02205029A (en) | 1990-08-14 |
Family
ID=12131991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2421289A Pending JPH02205029A (en) | 1989-02-02 | 1989-02-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02205029A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5899726A (en) * | 1995-12-08 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of forming oxide isolation in a semiconductor device |
-
1989
- 1989-02-02 JP JP2421289A patent/JPH02205029A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5899726A (en) * | 1995-12-08 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of forming oxide isolation in a semiconductor device |
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