JPS63215068A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS63215068A
JPS63215068A JP4764187A JP4764187A JPS63215068A JP S63215068 A JPS63215068 A JP S63215068A JP 4764187 A JP4764187 A JP 4764187A JP 4764187 A JP4764187 A JP 4764187A JP S63215068 A JPS63215068 A JP S63215068A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
collector
region
layer
formed
side face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4764187A
Inventor
Yoshiharu Kobayashi
Tsutomu Yamaguchi
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To obtain a microscopic semiconductor device having a small parasitic capacitance and low resistance by a method wherein a collector compensating layer, the bottom face and one side face of which are contacted to an insulating film and other side face is contacted to a collector region, is provided and the positional relation of a collector lead-out layer and the like is determined by applying self-alignment.
CONSTITUTION: After an N-type buried region 26 and an N-epitaxial layer 27 have been formed on a P-type substrate 24, an oxide film 22a is formed on the exposed surface of the substrate 24, and a P-channel cut region 25 is formed by ion implantation. Then, after a nitride film 22 has been formed on the side face of the region 26 and the layer 27, an oxide film 22b is buried flatly, and a polycrystalline silicon 37 is deposited on the region which becomes the collector pick-out part on the circumference of the layers 26 and 27. As the collector compensating layer contacting to the collector region is used as the constituent element of the collector lead-out layer, the parasitic capacitance and the resistance of the title semiconductor device can be reduced. Also, the buried region 26, the channel-cut layer 25 and the collector lead-out layer 37 can be formed by applying self-alignment.
COPYRIGHT: (C)1988,JPO&Japio
JP4764187A 1987-03-04 1987-03-04 Semiconductor device and manufacture thereof Pending JPS63215068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4764187A JPS63215068A (en) 1987-03-04 1987-03-04 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4764187A JPS63215068A (en) 1987-03-04 1987-03-04 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS63215068A true true JPS63215068A (en) 1988-09-07

Family

ID=12780866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4764187A Pending JPS63215068A (en) 1987-03-04 1987-03-04 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS63215068A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5024956A (en) * 1988-01-25 1991-06-18 U.S. Philips Corporation Method of manufacturing a semiconductor device including mesa bipolar transistor with edge contacts
US5234844A (en) * 1988-03-10 1993-08-10 Oki Electric Industry Co., Inc. Process for forming bipolar transistor structure
US5434092A (en) * 1991-12-31 1995-07-18 Purdue Research Foundation Method for fabricating a triple self-aligned bipolar junction transistor
US5506157A (en) * 1994-12-20 1996-04-09 Electronics And Telecommunications Research Institute Method for fabricating pillar bipolar transistor
US5721147A (en) * 1995-09-29 1998-02-24 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors
US5814538A (en) * 1996-03-19 1998-09-29 Samsung Electronics Co., Ltd. Methods of forming BiCMOS devices having dual-layer emitter electrodes and thin-film transistors therein
US5877539A (en) * 1995-10-05 1999-03-02 Nec Corporation Bipolar transistor with a reduced collector series resistance
US5994196A (en) * 1997-04-01 1999-11-30 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654064A (en) * 1979-10-08 1981-05-13 Mitsubishi Electric Corp Semiconductor device
JPS59165455A (en) * 1983-03-10 1984-09-18 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654064A (en) * 1979-10-08 1981-05-13 Mitsubishi Electric Corp Semiconductor device
JPS59165455A (en) * 1983-03-10 1984-09-18 Toshiba Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5024956A (en) * 1988-01-25 1991-06-18 U.S. Philips Corporation Method of manufacturing a semiconductor device including mesa bipolar transistor with edge contacts
US5234844A (en) * 1988-03-10 1993-08-10 Oki Electric Industry Co., Inc. Process for forming bipolar transistor structure
US5434092A (en) * 1991-12-31 1995-07-18 Purdue Research Foundation Method for fabricating a triple self-aligned bipolar junction transistor
US5506157A (en) * 1994-12-20 1996-04-09 Electronics And Telecommunications Research Institute Method for fabricating pillar bipolar transistor
US5721147A (en) * 1995-09-29 1998-02-24 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors
US5877539A (en) * 1995-10-05 1999-03-02 Nec Corporation Bipolar transistor with a reduced collector series resistance
US5814538A (en) * 1996-03-19 1998-09-29 Samsung Electronics Co., Ltd. Methods of forming BiCMOS devices having dual-layer emitter electrodes and thin-film transistors therein
US5994196A (en) * 1997-04-01 1999-11-30 Samsung Electronics Co., Ltd. Methods of forming bipolar junction transistors using simultaneous base and emitter diffusion techniques

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