JPH02201680A - Dma data transfer circuit - Google Patents

Abstract

PURPOSE:To execute data transfer at high speed by providing a FIFO (first in first out) memory to take in an ACK (acknowledge) signal with an EOP(end of process) signal outputted from a DMA (direct memory access) control circuit as a load clock, to generate and hold data including the information of a correspondent channel. CONSTITUTION:A DMA control circuit 1 outputs the ACK signal to permit the occupation of a system bus in correspondence to any one of the plural channels. Then, when the ACK signal is outputted several times to be set in advance for each channel by a counter 3, the EOP signal is outputted. A FIFO memory 2 takes in the ACK signal with the EOP signal as the load clock, generates the data including the information of the correspondent channel and holds these data. When a data read instruction is outputted to the FIFO memory 2, an OR signal is outputted to promote prescribed interruption processing to a peripheral device in a transfer destination and the held data are transferred to the peripheral device. Thus, it can be easily confirmed with channel the generation of the interruption corresponds to. Then, a data transfer speed can be improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is used to realize high-speed data transfer between the main memory of a system and a peripheral device such as a magnetic disk device. This invention relates to a DMA data transfer circuit.

(Prior Art) Conventionally, D
M A (direct memory access
) method is known.

Control of high-speed data transfer using this DMA method is performed as follows.

First, in response to a request from a peripheral device, DM
The A control circuit requests the CPU to release the system bus. When the peripheral device acquires the right to use the bus, it outputs the address to the main memory, reads the data from the main memory, and outputs an ACK (acknowledge) signal to the peripheral device, allowing it to use the bus. Instruct them to import. As a result, the data stored in the main memory is transferred to the peripheral device.

In such an operation, the above-mentioned ACK signal is outputted consecutively the number of times set in the counter in advance, and depending on the final output, the DMA control circuit sends a series of processing to the peripheral device. An IEOP (end of process) signal indicating completion is output.

Incidentally, the output end of the EOP signal of the DMA control circuit is directly connected to an interrupt line in a peripheral device, and the peripheral device starts a predetermined interrupt process in response to input of the EOP signal.

Therefore, in a system configured to use the ACK signal in multiple channels, a counter corresponding to each ACK signal output is used to easily determine which channel the interrupt caused by the input of the EOP signal corresponds to. It was necessary to read the values of each.

(Problems to be Solved by the Invention) As described above, in the conventional DMA data transfer circuit, sufficient high-speed data transfer is required when the ACK signal for permitting exclusive use of the system lot is used for multiple channels. was difficult.

Furthermore, when a system is constructed by incorporating a large number of DMA control circuits, there is a risk that the EOP signal alone may monopolize the interrupt line.

Incidentally, an example of a circuit that can realize high-speed data transfer under the conditions described above and also unify the dedicated interrupt line using the EOP signal is the one shown in Figure 4, but this is extremely difficult. It was impractical because it required a large number of parts and the wiring connections were quite complicated.

The present invention is intended to solve the above-mentioned problems, and even when performing DMA data transfer corresponding to any one of a plurality of channels, the present invention has a simple configuration, and allows generation of an interrupt in a peripheral device to correspond to which channel. The object of the present invention is to provide a DMA data transfer circuit that can easily confirm whether the data is being transferred and improve the data transfer speed.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above-mentioned object, the DMA data transfer circuit of the present invention monopolizes the system bus in accordance with any one of a plurality of channels. 1, and when this first signal is continuously output a preset number of times for each channel, outputs a second signal.
an MA control circuit; and the first signal output from the DMA control circuit is taken in using the second signal output from the DMA control circuit as a load clock, and information about the corresponding channel is included from this signal. A FIFO memory that generates and holds data, and in response to a data read command, a third signal is sent from the FIFO memory to the peripheral device to which the data is transferred, prompting the peripheral device to perform a predetermined interrupt process.
It is designed to be output together with the data held in O memory.

(Function) Explanation of the function of the DMA data transfer circuit of the present invention). First, the DMA control circuit outputs a first signal that permits exclusive use of the system bus in correspondence with one of the plurality of channels, and this first signal is output a preset number of times for each channel. When this occurs, a second signal is output.

The FIFO memory takes in the first signal output from the DMA control circuit using the second signal as a load clock, generates data containing information of the corresponding channel from this signal, and holds this.

After that, when a data read command is output to the FIFO memory, a third signal is output from the FIFO memory to prompt the peripheral device of the delta transfer destination to perform a predetermined interrupt process. data is transferred to the peripheral device.

Therefore, according to the present invention, even when performing DMA data transfer corresponding to one of a plurality of channels, it is possible to easily determine which channel an interrupt in a peripheral device corresponds to. It is possible to easily check the data transfer rate, and it is possible to improve the data transfer speed.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a diagram for explaining the configuration of a DMA data transfer circuit according to an embodiment of the present invention.

In the figure, 1 is a DMA control circuit that controls DMA data transfer between the main memory of the system and peripheral devices, and 2 is a D
FI inserted between MA control circuit 1 and peripheral devices
FO (first in Nrst out) memory is shown.

The DMA control circuit 1 is configured to output an ACK (acknowledge) signal for granting exclusive use of the system bus to a peripheral device, corresponding to one of a plurality of channels. The DMA control circuit 1 is also equipped with a counter 3 corresponding to the ACK signal output of each channel, and the ACK signal is outputted by the corresponding counter 3 a preset number of times (counts down until it reaches 0). ) is output continuously, and EO is output according to the final output.
A P (end of process) signal is output. Further, this EOPOR signal is inputted to the load clock terminal of the FIFO memory 2 via the inverter 4.

FIG. 2 shows the operation timing in this embodiment circuit.

As shown in the figure, in this embodiment, the above load
In synchronization with the rising edge of the clock, the ACK signal from the DMA control circuit 1 is sent to the data input holding section 5 of the FIFO memory 2.
is input into the channel and retained as data containing information on the corresponding channel.

The data held in the data input holding unit 5 of the FIFO memory 2 is transferred from the CPU to the UNCKI of the FIFO memory 2.
N input terminal and OE (output enable)
The signal is output to the peripheral device in response to the input of the READ signal to the input terminal.

On the other hand, the OR (output read) output terminal of the FIFO memory 2 is connected to the interrupt line of the peripheral device, and when the READ signal is input from the CPU to the FIFO memory 2, the output terminal from the FIFO memory 2 is connected to the peripheral device. In contrast, an OR signal is output that prompts a predetermined interrupt process.

In this way, predetermined interrupt processing is started in the peripheral device. At this time, it is determined to which channel the occurrence of the interrupt corresponds based on the data output from the pig input holding section 5 of the FIFO memory 2 in a first-in, first-out manner.

In other words, as shown in Fig. 2, the interrupt that occurred at No. 1 1-1 is (ACK2) because the first data output from FO memory 2 is rFBI (J).
The second interrupt that occurs is caused by the second data output from FIFO memory 2 being rFE1(J
Therefore, it is determined that this is due to (ACKO).

Thus, according to this embodiment, it is possible to easily confirm which channel the occurrence of an interrupt in a peripheral device corresponds to, and as a result, it is possible to increase the speed of data transfer. Moreover, compared to a conventional circuit (see Figure 4) that has the same function as the device of this embodiment, the number of parts is smaller and the connections are easier, making it extremely practical to construct an MA data transfer circuit. Can be done.

Note that in the embodiment described above, the DMA data transfer circuit is configured using one DMA control circuit, but the DMA data transfer circuit is configured using one DMA control circuit.
The present invention can be similarly applied even when the A control circuit is used.

For example, as shown in FIG.
] to the data input holding unit 13 of the FIFO memory 12, the EOP signal output terminal of each DMA control circuit 11 to the load/clock terminal of the FIFO memory 12 via the OR circuit 14, and Control circuit 11
By connecting the AEN signal output terminals of two each to the data input holding section 13 of the FIFO memory 12 via the NOR circuit 15, it is possible to construct a DMA data transfer circuit having the same function as the embodiment described above. can.

Moreover, in this case, even if a plurality of DMA control circuits 11 are used, only one interrupt line is used exclusively.

[Effects of the Invention] As explained above, according to the DMA data transfer circuit of the present invention, even when performing DMA data transfer corresponding to a plurality of channels, the occurrence of interrupts in peripheral devices can be prevented with a simple configuration. It is possible to easily check whether the channel is compatible with the other channel, and it is possible to improve the data transfer speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining the configuration of a DMA data transfer circuit according to an embodiment of the present invention, and FIG. 2 is a DM data transfer circuit shown in FIG.
A diagram showing the operation timing in the data transfer circuit, FIG. 3 is a circuit diagram for explaining another embodiment of the present invention, and FIG. 4 shows the same function as the DMA data transfer circuit in FIG. 1 or 2. 1 is a circuit diagram showing the configuration of a conventional DMA data transfer circuit having the following configuration. 1...DMA control circuit 2...FIFO memory 3...Counter 4...Inverter 5...Data input holding unit. 1]

Claims (1)

[Claims] (1) Output a first signal that permits exclusive use of the system bus corresponding to one of the plurality of channels, and
a DMA control circuit that outputs a second signal when the signal is continuously output a preset number of times for each channel, and the second signal output from the DMA control circuit is used as a load clock. a FIFO memory that captures the first signal output from the DMA control circuit and generates and holds data including information of the corresponding channel from this signal, and reads data from the FIFO memory in response to a data read command. A DMA data transfer circuit characterized in that a third signal prompting a transfer destination peripheral device to perform predetermined interrupt processing is output together with data held in the FIFO memory.