JPS61187058A - Data transfer system - Google Patents

Abstract

PURPOSE:To prevent overrunning due to the overhead of a data chain operation by stopping temporarily the transfer operation or extending a time interval of transfer requests each time when data having a certain size is transferred. CONSTITUTION:Before data transfer, a byte count value which is a unit of data chain is set to a counter 20. A transfer control part 12 counts down contents of the counter 20 by one each time when one-byte data is transferred to or from a channel device. When contents of the counter 20 become 0 according as data transfer is executed, that is, when data transfer of one data length in data chain is terminated, the transfer control part 12 stops temporarily the transfer operation and generates an interrupt to a microprocessor 10. The microprocessor 10 sets the byte count value to the counter 20 again and starts the transfer control part 12 after a certain time.

Description

[Detailed Description of the Invention] [Summary] When the transfer of the input/output limit to the main storage device is completed via the channel device, the start of the next data transfer is delayed in the input/output control device. .

[Industrial application field]

The present invention is an information processing system including a main storage device, a central processing unit, a channel device, and an input/output control device connected to the channel device, in which a data area to be transferred in the main storage device has a data length of a fixed size. In an information processing system that makes it possible to transfer data between a channel device and an input/output control device using a so-called data chain function in which data is chained by The present invention relates to a data transfer method that enables efficient data transfer between a channel device and an input/output control device without increasing the amount of data.

[Conventional technology]

FIG. 3 is a diagram showing an example of the configuration of a general information processing system. In the figure, 1 is the main memory (M, S).

2 is the central processing unit (CPU), 3 is the channel device (CH
), 4 is the input/output control device (IOC), and 5 is the input/output device (
■0).

In the system shown in FIG. 3, when a large amount of data is transferred between the main storage device 1 and the input/output control device 4 via the channel device 3, the main storage device 1 generally has a small portion of the size. A so-called data chain function is used in which a large number of data areas are prepared and data is transferred by sequentially chaining these data areas.

FIG. 2 is a diagram showing an example of the configuration of a conventional input/output control device, and in the figure, 10 is a microprocessor.

11 is a data buffer, 12 is a transfer control unit, 13 is a byte counter (BC), and 14 is a subtraction circuit.

15 is an all-0 detection circuit; 16 is a control line between the channel device; 17 is a data line between the channel device;
8 is an interrupt signal (line) to the microprocessor 10, 1
9 is a transfer data line.

The conventional example shown in FIG. 2 shows a case where a microprocessor 10 performs main control of the input/output control device. first,
Before data is transferred to or from main memory via a channel, a byte count value indicating the entire transfer is set in byte counter 13 under control of the channel program.

After that, each time 1 byte of data is transferred, the subtraction circuit 1
4, the contents of the byte counter 13 are subtracted by -1. And the content of byte counter 13 is still “O”
However, when the transfer of data in a data area of a certain size in consecutive rounds on the main memory device is completed, a data chain operation is executed in the channel device, and the data on the next chained main memory device is transferred. Data transfer continues between the data area and the input/output control device.

When the all "0" detection path 15 detects that the content of the byte counter 13 has become 0, a stop instruction is issued to the transfer control unit 12 and an interrupt is issued to the microprocessor 10. . Thereafter, the microprocessor 10 executes the required processing.

[Problem that the invention seeks to solve]

In the above case, the problem is the time it takes for the channel to perform the data chain operation, and if the data area of the fixed size is small, the frequency of the data chain operation increases, resulting in a high system load. By enlarging the data area, the frequency of data chain operations can be reduced; however, the large area occupied on the main memory device has the drawback of increasing the main memory capacity.

[Means for solving problems]

In order to solve the above points, the present invention provides a main storage device (1)
, an information processing system including a central processing unit (2), a channel device (3), and an input/output control device (4) connected to the channel device, the data area to be transferred in the main storage device (1). In an information processing system that makes it possible to transfer data between the channel device (3) and the input/output control device (4) using a data chain function of chaining with a data length of a partial size, The input/output control device (4) is provided with means 1d (20) for storing the data length of the fixed size and means (22) for detecting completion of data transfer of the data nourishment. The present invention is characterized in that the transfer operation is temporarily stopped or the time interval between transfer requests is extended every time data is transferred.

[Effect]

When data transfer is performed using the data chain function, the present invention temporarily stops the transfer operation every time a data length of a certain size is transferred, which is the unit for performing the data chain, in the input/output control device. Alternatively, the time interval between transfer requests is extended, thereby making it possible to prevent overruns due to overhead of data chain operations.

〔Example〕

FIG. 1 is a diagram showing the configuration of an input/output control device according to an embodiment of the present invention. In the figure, the same numbers as those in FIG. 2 above indicate the same names, and 20 is a counter in which a byte count value is set, which is a unit for performing a data chain;
21 is a subtraction circuit, 22 is an all "0" detection circuit, and 23 is an OR circuit.

Compared to the conventional example shown in FIG. 2, the configuration is such that a counter 20, a subtraction circuit 21, and an OR circuit 23 are added.

The operation of the embodiment is as follows.

First, before performing data transfer, a byte count value indicating the total amount of data transferred is set in the byte counter 13, and furthermore, a byte count value, which is a unit in which data chain is performed, is set in count 2o. Thereafter, the transfer control unit 12 is activated.

The transfer control unit 12 issues a subtraction instruction to the subtraction circuits 14 and 21 every time 1 byte data is transferred with the channel device,
The contents of byte counter 13 and counter 20 are each subtracted by 1.

When the data is chained, the contents of the byte counter 13 and the contents of the counter 20 are naturally set at the time of initial setting, and as the data transfer is executed, the contents of the counter 2o are set to "0" first. When this occurs, that is, when the data transfer of one data length in the data chain is completed, the transfer control unit 12 temporarily stops the transfer operation and generates an interrupt to the microprocessor 10.

The microprocessor 10 determines that the byte counter 13 is “0”.
”, and if it is not “0”, set the byte count value in counter 2o again,
After waiting for a certain period of time, the transfer control unit 12 is activated.

In this way, an interrupt is generated in the microprocessor 10 for each unit data length in the data chain, and the transfer operation is temporarily stopped.

〔Effect of the invention〕

According to the present invention, it is possible to prevent overruns in data transfer operations due to overhead of data chain operations, thereby improving transfer efficiency. Furthermore, since the data length of a fixed size that is a unit of a data chain can be reduced, the capacity of the main memory can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an input/output control device according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of a conventional input/output control device, and FIG. 3 is a diagram showing a configuration example of an information processing system. It is a diagram. In FIG. 1, 10 is a microprocessor, 11 is a data buffer, 1
2 is a transfer control unit, and 13 is a byte counter. 20 is a counter 22 which is an all 0' detection circuit. Nji Izumi's entrance Hiroki Ill Tsubaki P's sounding talent false entry 4 rows without suggestion 2 country A book (read 1 electric study, breast entry and exit! JI
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Claims (1)

[Claims] An information processing system including a main storage device (1), a central processing unit (2), a channel device (3), and an input/output control device (4) connected to the channel device, the main storage device (1) The channel device (3) and the input/output control device (4) are connected using a data chain function in which the data area to be transferred is set to a fixed data length and chained.
), the input/output control device (4) includes:
means (20) for storing the data length of the constant size;
Means (22) for detecting completion of data transfer for the data length is provided, and the time interval of transfer requests generated by the input/output control device (4) is temporarily set each time data for the data length is transferred. A data transfer method characterized by being configured to extend the data.