JPH01150935A - Central processing unit - Google Patents

Abstract

PURPOSE:To improve the integration degree of a semiconductor and efficiency of a whole central processing unit by consisting of plural execution unit elements and equipping an execution unit which can simultaneously process plural instructions. CONSTITUTION:An instruction decoding unit 4 decodes the contents of data which are read simultaneously, checks whether or not they can be simultaneously carried out, and delivers its result to the execution unit. When the instructions which can be simultaneously carried out exist, the execution unit simultaneously carries them out. A memory management unit 1 exchanges information between a bus control unit and the execution unit, and controls a memory. When the integration degree of semiconductor elements increases, it is easy to increase a bus width or the size of a data buffer in the central processing unit. By increasing the execution unit elements in the execution unit, the whole efficiency can be smoothly improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a central processing unit that plays the most important role in a computer.

Traditional Technology The information processing industry is developing rapidly, and the most important and competitive one is the development of central processing units.

The configuration of the conventional central processing unit mentioned above will be described below with reference to the drawings.

FIG. 5 is a block diagram of a conventional central processing unit. Fifth
In the figure, 1 is an instruction decoding unit that controls memory, 2 is a bus control unit that controls an external bus, 5 is an execution unit that executes instructions, and 4 is a unit that decodes data and changes it into an executable format. This is an instruction decoding unit.

The operation of the central processing unit configured as described above will be explained below.

FIG. 2 explains the form of instructions stored in memory. Instructions that run a computer have different lengths depending on the content of the instruction. Simple instructions exist from 1-byte instructions, but complex instructions can be as long as 5 to 6 bytes. A part of it will be explained in FIG. ■ is 1
Explains the byte instruction. A 1-byte instruction is a typical register-related instruction in many cases. In this example, register AX is increased by 1. 2 describes a 2-byte instruction. Among 2-byte instructions, there are many instructions between registers. In the example, register AX and register B
Adding X. ■ describes a 3-byte instruction. For instructions longer than 3-byte instructions, some data is added to the basic instruction. In the example, data 8 is added to register BX. In the 4-byte instruction (2), the contents of address 1000 are added to register BX.

In actual data, various data are arranged irregularly, so the length of each instruction is different. An example is shown in FIG. In Figure 3, the length of the first instruction is 1 byte,
The length of the second instruction is 2 bytes, the length of the third instruction is 1 byte, and the length of the fourth instruction is 3 bytes.

The central processing unit sequentially reads the data lined up as shown in Figure 3 and processes them sequentially. The basic movements will be explained with reference to FIGS. 5 and 3. The data lined up as shown in Figure 3 is read into the central processing unit by the bus control unit 2 in Figure 5, and converted into the instruction length and format that can be executed by the execution unit by the instruction decode unit 4 in Figure 5. Then, the instruction is executed by the execution unit 5 in FIG. If memory processing is required, the memory management unit 1 in FIG. 5 performs the processing. (For example, refer to microprocessor manuals issued by each semiconductor company.) Problems to be Solved by the Invention However, with the above configuration, even if an attempt is made to increase the processing speed of the central processing unit, the processing time of the execution unit will greatly affect the overall processing time. There is a problem in giving. The processing speed of the bus control unit, instruction decode unit, and memory management unit, which are components other than the execution unit, can be improved by increasing the bus width or pre-reading a large amount of data.

In view of the above problems, the present invention provides a central processing unit that employs an execution unit that is composed of a plurality of execution unit elements and can simultaneously process a plurality of instructions.

Means for Solving the Problems In order to solve the above problems, the central processing unit of the present invention comprises:
It is equipped with an execution unit that is composed of a plurality of execution unit elements and can process a plurality of instructions at the same time.

Operation The present invention has the above-mentioned configuration, and the instruction decode unit 7)
You can now create multiple instructions that can be executed at the same time, and the execution unit can now execute multiple instructions at the same time.

With this configuration, as the degree of integration increases due to advances in devices, it is relatively easy to increase the internal bus width and the number of buffers for storing internal data, thereby improving the overall speed of the central processing unit. becomes easier.

Embodiment Hereinafter, a central processing unit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the central processing unit of the present invention. In Figure 1, 2 is a bus control unit that controls an external bus, and 4 is an instruction that interprets data input from the bus control unit and converts instructions so that they can be executed by multiple execution unit elements. a decoding unit,
3 is an execution unit that simultaneously executes a plurality of instructions created by the instruction decode unit using a plurality of internal execution unit elements, and l is a memory that controls the memory while communicating with the execution unit and the bus control unit. It is a management unit.

The central processing unit configured as described above will be explained below with reference to FIGS. 1, 2, 3, and 4.

FIG. 3 is an example of an instruction that is a reserve. As explained in FIG. 2, the instruction length varies depending on the contents of the instruction. Therefore, as shown in FIG. 3, the lengths of the instructions vary. The role of the central processing unit is to decode and execute the instruction sequence shown in FIG.

However, the actual instructions are packed and stored. Figure 4 shows
This shows a state in which the instruction sequence of FIG. 3 is stored. FIG. 4 describes a 4-byte central processing unit. The horizontal length of the table is 4 bytes, and 16 instructions are stored. The total number of instruction lengths in FIG. 3 is 28 bytes. The numbers in parentheses in FIG. 4 correspond to the order of the instructions in FIG. The first 4 bytes contain (1), (
2) and (3) are stored, and the next 4 bytes contain (4
) and the first byte of (5) are stored.

The bus control unit 2 in FIG. 1 reads data from memory. Since a 4-byte central processing unit reads every 4 bytes, three instructions (1), (2), and (3) in FIG. 3 are read at the same time. In the next read, the next 4 bytes are read, and as can be seen in FIG. 4, parts of (4) and (5) are read. The instruction decode unit 4 in FIG. 1 decodes the contents of data read simultaneously and checks whether they can be executed simultaneously. If there are instructions that can be executed simultaneously, the execution units execute them simultaneously. Execution unit 3 in FIG. 3 shows the case where there are four execution unit elements. The instruction decode unit decodes the instructions, checks whether the instructions can be executed simultaneously, and passes the result to the execution unit. - The memory management unit 1 in FIG. 1 controls the memory by exchanging information between the bus control unit and the execution unit.

As the degree of integration of semiconductor devices increases, it is easy to increase the bus width and the size of the data buffer within the central processing unit. By increasing the number of execution unit elements within an execution unit, the overall efficiency can be smoothly improved.

Effects of the Invention As described above, the present invention provides an instruction decode unit 7) that interprets input data and converts instructions so that they can be executed by a plurality of execution unit elements, and a plurality of execution units created by the instruction decode unit. By providing an execution unit that simultaneously executes instructions using multiple internal execution unit elements, we have developed a central processing unit that can smoothly improve the overall efficiency of the central processing unit as the degree of integration of semiconductors increases. This is something that can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of the present invention, FIGS. 2, 3, and 4 are detailed illustrations of embodiments of the present invention, and FIG. 5 is a block diagram of the main parts of the prior art. 1...Memory management unit, 2...
... Bus control unit, 3 ... Execution unit, 4 ... Instruction decode unit, 5 ...
・Traditional execution unit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1! Figure 2 ■ 1-byte instruction ■ 2-byte instruction ■ 3-byte instruction ■ q-byte instruction! life ? Address I Address? (Sae 1T)
svo sx (inner core of tooo number j color) Fig. 3 (1) Mouth] = Ko (2) Ro = = Go = = Ko (3) Mouth = = Ko (7) Mouth = = Ko (8) Mouth = =ko(9) 口==ko(10) 口■] (14) 口==ko(15) 口 2==ko(16) 口口ko

Claims (1)

[Claims] A bus control unit that controls an external bus; an instruction decode unit that interprets data input from the bus control unit and converts instructions so that they can be executed by multiple execution unit elements; and a memory management unit that controls memory while communicating with the execution unit and the bus control unit. A central processing unit characterized by: