JPH01274240A - Parallel processing processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of a parallel processing by providing a context controller which updates the content of the address selection means of an instruction to be allocated on the next execution cycle while performing the execution cycle of a selected instruction. CONSTITUTION:While the instruction stored in the buffer 4A of an instruction queue 4 is executed, an operation enable signal is supplied from the context controller 18 to a second address register 10, and when the instruction stored in the buffer 4B of the instruction queue 4 is the instruction containing the input/output of a RAM 12 or a universal barrel at a second byte, a new address supplied via a buffer 4C and an address bus 6 is written on the second address register 10. Also, the operation enable signal from the context controller 18 is supplied to first and second counters 2 and 3, then, count values are updated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a parallel processing processor such as a microprocessor having a multiprocessing configuration.

2. Description of the Related Art In recent years, software programming type microprocessors have been widely used in various fields, and their configuration includes a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a plurality of addresses. data input/output means specified by instructions stored in the program storage means; calculation means for executing data operations based on instructions sent from the program storage means; and data input/output means (data memory, input/output The device is characterized by having a data path connecting between the port (corresponding to the port) and the calculation means.

Further, a typical configuration thereof is shown in Japanese Patent Publication No. 58-33584.

Microprocessors with this software programming method can be used for a variety of purposes, but on the other hand,
When used as a controller for some devices that require high-speed processing, there are six problems: compared to dedicated controllers made of wired logic, they lack real-time processing ability. In order to increase the processing power of a microprocessor, a pipeline processing method is adopted, or a microprocessor with a multi-processing configuration as shown in U.S. Pat. has been proposed.

Problems to be Solved by the Invention However, the conventional e-line processing method described above improves the efficiency of instruction execution by prefetching instructions, but when conditional branch instructions are included, , this results in inconveniences such as the exception handling becomes complicated and the effect of read-ahead cannot be obtained.Also, in a microprocessor with a multiprocessing configuration, resources such as ALU (arithmetic logic unit) and data path are shared. In this case, multiple processing loops were executed in a time-sharing manner, and although the real-time performance of the processing improved, the processing efficiency did not improve.

In view of the above, an object of the present invention is to provide a parallel processing processor with improved processing efficiency in a microprocessor having a multiprocessing configuration.

Means for Solving the Problems In order to solve the above problems, the parallel processing processor of the present invention causes the second instruction selection means to select an instruction subsequent to the selection of an instruction by the first instruction selection means,
The execution cycles of the instructions selected by these instruction selection means are alternately assigned, and during the execution cycle of the instruction selected by one of the instruction selection means, the execution cycle of the instruction to be assigned to the next execution cycle is A context controller is provided for completely updating the contents of the first or second address selection means.

In the present invention, with the above-described configuration, if the instruction taken out from the second instruction selection means is accompanied by an index part that specifies the address of the data input/output means, the instruction taken out from the first instruction selection means is By updating the contents of the second address selection means during execution, that is, before the start of execution of the instruction taken out from the second instruction selection means, the processing efficiency of the microprocessor is substantially improved.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a parallel processing processor according to an embodiment of the present invention. The instruction selected by the programmable counter 3 is sent to an instruction queue 4 for holding and pre-reading the instruction. The instruction once held in the instruction queue 4 is sent to the instruction decoder 5, and its address index part is sent to the address bus 6. A group of control signals produced by the instruction decoder 5 is supplied via a control bus 7 to each block making up the microprocessor.

Further, a plurality of timing signals for processing by the microprocessor are generated in the timing generator 8, and these timing signals are supplied to each block via the control bus 7. address bus 6 and first programmable counter 2. Second programmable counter3. First address register9. Second address register 10. The data paths 11 are connected to each other so as to send address data to each other. The first address register 9 and the second address register 10 are RAM (including a stack area)12. Holds the address of the general-purpose parallel input/output port 13. General-purpose (The three groups of input/output lines of the parallel input/output board 13 are connected to the input/output terminal groups of the input/output terminal groups of the input/output terminal groups AO~MU15, Bo~Bus terminals, and C0NCl3, respectively. Furthermore, the input section of the MLU 16 is connected to the data path 11 via a first register 14 and a second register 15, and the output of the MLU 16 is supplied to an accumulator unit (including a group of flags) 17. The accumulator unit 1 and data path 11 are also connected by a bidirectional bus.

On the other hand, the timing signal from the timing generator 8 is also supplied to the context controller 18, and the output signal of the context controller 18 is supplied as an operation enable signal to the first programmable counter 2 and the second address register 1°. The inverted signal via the parter 19 is supplied to the second programmable counter 3 and the first address register 9.

It is assumed that the data output section of each block has a three-state configuration, and is maintained in a non-impedance state during a period when data output is not required. Further, it is assumed that necessary timing signals and control signals are supplied to each block via the control path 7.

Regarding the parallel processing processor configured as above,
The operation will be explained with reference to the block diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG.

First, Figure 2 is the external clock input terminal CLK in Figure 1.
FIG. 2B, c, n, and x respectively show the signal waveforms of the basic timing signals output from the timing generator 8. FIG. 2F shows the operation enable signal from the context controller 18.

Now, in the parallel processing processor shown in Fig. 1, the instruction RO
Once taken out from M1 and held in the instruction queue 4, the processing contents are interpreted and executed by the instruction decoder 5. The instruction queue 4 has a first buffer 4m, a second buffer 14B, and a third buffer 4C, and the first buffer 4m and the second buffer 4 form a stack in FIFO (first-in-first-out) format. The first byte of the instruction fetched by the first programmable counter 2 and the first byte of the instruction fetched by the second programmable counter 3 are
They are configured to be stored alternately.

Also, the first instruction code stored in the second buffer 4B
Judging from the byte, if the instruction involves the second byte, the second byte of the instruction is stored in the third buffer 4C. The signal shown in FIG. 2B is used as a timing signal to precharge the address decoder included in the RA 112 to determine the selected address, and the signal shown in FIG. It is used as a timing signal for reading to path 11. Also, the signal in the second diagram is the data path 11
From RAM12 or general-purpose parallel input/output port 13
The leading edge of the timing signal in Figure 2E is used as a timing signal to write data to
is the read timing, and the trailing edge is the write timing.

Here, the section B in FIG. Assuming this, in order to transfer data at a specific address in the RAM 12 to the accumulator unit 17 during interval b from time t1, that address must be held in the second address register 10 before time t1. . In the parallel processing processor of FIG. 1, time t.

In an interval a from
The operation enable signal shown in FIG. If the instruction contains information, the new address supplied via the address bus 6 to the third buffer 4C is transferred to the second buffer 4C.
write to the address register 10 of. Further, the operation enable signal from the context controller 18 is also supplied to the first programmable counter 2 and the second programmable counter 3, and each time the period a or period b in FIG. 2 arrives, the first programmable counter It is also used to update the count value of the programmable counter 2 or the second programmable counter 3.

In this way, in the parallel processing processor shown in FIG.
12 or general-purpose parallel input/output port 13, the second address register is used during execution of an instruction fetched from the second programmable counter 3 or the first programmable counter 2. By updating the contents of K, the processing efficiency of the microprocessor can be substantially improved.

By the way, in the embodiment shown in FIG.
Although a parallel processing processor having a dual processing mechanism having programmable counters has been described, it goes without saying that the present invention can be similarly applied to a parallel processing processor having a multiple processing mechanism of more than that. FIG. 3 shows another embodiment of the present invention, in which the present invention is applied to a parallel processing processor having a triple processing mechanism. Since the operation of the context controller 18 in FIG. 3 is the same as that in FIG. 1, a detailed explanation of the operation will be omitted, and a timing chart compared to FIG. 2 will be shown in FIG.

Effects of the Invention As is clear from the above description, the parallel processing processor of the present invention includes a program storage means for storing a program consisting of a group of instructions to be executed in a single order, and a specific instruction stored in the program storage means. at least first and second instruction selection means for selecting, data input/output means having a plurality of addresses, first and second address selection means for specifying addresses of the data input/output means, and sending from the program storage means. a data path that connects the data input/output means and the calculation means; a timing generator that generates an instruction execution cycle; and a first instruction selection means. Following the selection of an instruction, the second instruction selection means selects an instruction, and alternately allocates the execution cycles of the instructions selected by these instruction selection means, and also assigns execution cycles of the instructions selected by one of the instruction selection means. By providing a context controller that updates the contents of the first or second address selection means during an execution cycle based on the address information of the instruction assigned to the next execution cycle, parallel processing efficiency is improved more than ever before. It is possible to obtain a processing processor, and its effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parallel processing processor in one embodiment of the present invention, FIG. 2 is a timing chart of the main part of FIG. 1, and FIG. 3 is a parallel processing processor in another embodiment of the present invention. FIG. 4 is a timing chart of the main parts of FIG. 3. 1... Instruction ROM, 2... First programmable counter, 3... Second programmable counter, 8... Timing generator, 9...
First address register, 1o...Second address register, 11...Data path, 12...
・RAM. 13...General-purpose parallel input/output port, 16...
-MuLU, 1s...Context controller. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

[Claims] a program storage means for storing a program consisting of a group of instructions to be executed sequentially; at least first and second instruction selection means for selecting a specific instruction stored in the program storage means; and a data input having a plurality of addresses. an output means, first and second address selection means for specifying the address of the data input/output means, arithmetic means for executing a data operation based on an instruction sent from the program storage means, and the data input/output means. a data path that connects the output means and the calculation means; a timing generator that generates an instruction execution cycle; causes selection to be made, and alternately allocates execution cycles of instructions selected by these instruction selection means, and during an execution cycle of an instruction selected by one instruction selection means, an address of an instruction to be allocated to the next execution cycle. A parallel processing processor comprising: a context controller that updates the contents of the first or second address selection means based on information.