JPH04280325A - Pipeline-type processor - Google Patents

Abstract

PURPOSE:To reduce an external circuit and to make an internal processing efficient by reading a task number included in input information in the preprocessing of a pipeline processing and selecting a task based on said information. CONSTITUTION:Input data and the task number are written into an input, information storage part 15 from an external part (CPU). At the start of execution, the head address (address to which task number is stored) of the input information storage part 15 is selected and a multiplexer 20 selects read data in the input information storage part 15. The task number is read out of the input information storage part at the start of execution with such constitution, and the task number is preset in a program counter 22 as the address of a task number storage part.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processor capable of processing multiple tasks.

0002

2. Description of the Related Art For example, when a fuzzy arithmetic processor is built into a controller, personal computer, workstation, etc. to centrally control a system, a processor that can handle multiple tasks is effective. FIG. 6 shows the configuration of the main parts of a conventional pipeline type arithmetic processor that can execute a plurality of tasks. In FIG. 6, the task information storage unit 14 stores a plurality of task processing information for each bank. The input information storage unit 15 stores data input via a bus (not shown). The pipeline type processor configured in this manner stores one task processing information among a plurality of task processing information by setting the bank setting address of the task information storage unit 14 from the outside (CPU) using an external terminal for bank switching. I try to choose.

0003

[Problems to be Solved by the Invention] However, in conventional pipeline processors that can execute multiple tasks, it is necessary to constantly manage the state of the processor externally (CPU), and there is also a problem with task information storage. There was a problem in that it required many setting terminals for bank switching in the section, and only inefficient bank setting was possible.

[0004] An object of the present invention is to provide a pipelined processor that reduces the number of external circuits and improves the efficiency of internal processing.

[0005]

[Means for Solving the Problems] A pipeline processor of the present invention includes an input information storage unit that stores externally input data as task selection data and input data, and task information that stores a plurality of task processing information. a storage unit; a pipeline register that latches the task processing information and provides it as an address of the input information storage unit;
The present invention is characterized by further comprising a program counter presetting means for presetting the task selection data in the input information storage section to a program counter at the start of execution.

[0006]

In the pipeline processor of the present invention, the input information storage section stores data input from the outside as task selection data and input data. The task information storage section stores a plurality of task processing information, and the pipeline register latches the task processing information read from the task information storage section and provides it as an address to the input information storage section. And the program counter presetting means is
At the start of execution, task selection data in the input information storage section is preset to the program counter. Therefore, by writing the task selection data together with the input data in the input information storage section, the task selection data is read from the input information storage section at the start of execution and is preset in the program counter. Then, a task in the task information storage section is selected using the data as an address. Therefore, externally, only task selection data indicating which task to execute is set as input information, and there is no need to manage the processing state of the processor. Furthermore, since the assignment of a plurality of tasks can be freely set in the task information storage section, the task information storage section can be used efficiently. Furthermore, since external terminals for task switching are not required, the processor package can be made smaller.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall configuration of a pipelined processor according to an embodiment of the present invention. In FIG. 1, the input information storage unit 15 has an area for storing a task number and a plurality of input data, and when input information is written, it is stored in an external (CPU)
) is given a write address and data via the bus buffer 10, and a write control signal is given from the read/write control section 11. The output information storage unit 18 has an area for storing calculation results, and when the CPU reads the contents, a read address is selected via the bus buffer 10 and a read control signal is applied from the read/write control unit 11. It will be done. This outputs data to the data bus. The clock control circuit 12 controls the address generation circuit 13 based on the externally applied clock signal and start signal.
, provides a clear signal and a clock signal to pipeline registers 1 to 4, respectively. Address generation circuit 1
3 is an input information storage unit 15 or a task information storage unit 1 according to a control code output from the pipeline register 1.
Let the output data of No. 4 be the address of the task information storage unit 14 (the value of the program counter). The A processing section 16 performs a predetermined process in stage (2) based on the data and control code of the pipeline register 2, and provides the data and control code to the pipeline register 3. B processing section 1
7 performs a predetermined process in stage (2) based on the data and control code of the pipeline register 3, and provides the data and control code to the pipeline register 4.

Next, more specific configurations of the main parts of the pipeline type processor are shown in FIGS. 2 to 4. In FIG. 2, multiplexer 20, PC register 21, program counter 22, and address register 23 correspond to address generation circuit 13 shown in FIG.

FIGS. 3 and 4 show specific examples of the input information storage section 15 and the task information storage section 14. As shown in FIG. 3, a task number is written at address 000H of the input information storage section 15, and a plurality of input data are sequentially written from address 001H onwards. On the other hand, the task information storage unit 14
As shown in FIG. 4, in this example, the start addresses of tasks 1 to 3, processing information for task 1, processing information for task 2, and processing information for task 3 are stored, and each data has 5 bits. A control code is attached. The task start address is the first address where task processing information is stored, and the task 1 start address is 003H, the task 2 start address is 010H, and the task 3 start address is 0F0.
It shows that it is H. As task processing information,
The processing contents of each task are stored, and the processing contents are stored in processing order starting from the first address. The control code is stored as control data for each stage of the pipeline in addition to the task processing information, and flows through the pipeline together with the task start address and task processing information.

The meaning of each bit of the control code is as follows.

Bit 4-Determines whether or not to preset the program counter. 0: Preset. 1: No preset.

Bit 3: When presetting the program counter, the MUX circuit (multiplexer) 20 in front of the PC register determines whether to set data in the task information storage section or data in the input information storage section. 0: Input information storage section read data 1: Task information storage section read data bits 2, 1 - Control code used in the A processing section 16 and the B processing section 17.

[0013] Bit 0 - Indicates the end of processing. 0: Processing continues next. 1: Processing completed.

When the contents of the input information storage section 15 and the task information storage section 14 shown in FIG. 2 are as shown in FIGS. 3 and 4, a timing chart of each part in FIG. 2 is shown in FIG.

The operation of FIG. 2 will be explained below with reference to FIGS. 3 to 5. First, when a start signal is applied, the clock control circuit 12 clears the program counter 22, pipeline registers 1 and 2, etc., respectively. As a result, 000H is set to the data in the pipeline register 1, and 00000 is set as the control code. The contents of the selected address (000H), that is, the task number, are read from the input information storage section 15 at the first clock. Since bit 3 of the control code of pipeline register 1 is 0 in multiplexer 20,
Select read data from the input information storage section 15. Further, since bit 4 of the control code of the pipeline register 1 is 0, the task number read from the input information storage section 15 is preset in the program counter 22 via the PC register 21. At the subsequent second clock, the contents of the task information storage section corresponding to the value of the program counter 22 are read out via the address register 23. For example, if 001H is written as the task number in the input information storage unit 15, then the address 0 of the task information storage unit
The contents of 01H, that is, the start address of task 2 (010H)
is read out. The control code associated with this task 2 start address is transferred from pipeline register 1 to multiplexer 2.
However, since bit 4 of the control code attached to the task 2 start address is 0 and bit 3 is 1, the task 2 start address 010H passes through the multiplexer 20 and is sent to the PC.
The program counter 22 is preset again via the register 21. At the subsequent third clock, the contents of address 010H of the task information storage section, that is, the process 1 information of task 2 is read out. b of the control code accompanying this
Since it4 is 1, this read data is not preset to the program counter. Thereafter, the processing information of task 2 is sequentially read out together with the control code and flows through the pipeline (in FIG. 5, ■ to ■ represent the processing at each stage shown in FIG. 1). When the final information of the processing information of task 2 is read, the control code b
Since it0 is 1, each stage that receives this control code ends its processing, clears the circuit, and waits for the next processing to start.

As described above, by simply writing the task number and input data into the input information storage section from the outside and starting the task, the task with the specified number can be executed.

In the above embodiment, the task processing information and the start address of each task are stored in the task information storage section, and the task selection data in the input information storage section is used as the task number, and the task number specifies the address of the task start address. However, the configuration may be such that the task selection data in the input information storage section directly specifies the start address of the task processing information stored in the task information storage section.

Note that the pipeline type processor shown in the above embodiment can be used, for example, as a fuzzy arithmetic processor. In this case, for example, membership functions and rule information for each controlled object are stored as each task information in the task information storage section shown in FIG. 1, and values of input variables are written as input data in the input information storage section 15. The A processing section 16 performs a process to obtain a matching value, the B processing section 17 performs a so-called minimax operation, and the output information storage section 18 stores a so-called truncated fuzzy set. Then, an external CPU can obtain a determined value by calculating the center of gravity from the data in the output information storage section 18.

[0019]

[Effects of the Invention] According to the present invention, the following effects can be obtained.

(1) On the outside (CPU), by simply setting which task is to be executed as input information, there is no need to manage the processing state of the processor. In particular, it is effective to use a FIFO configuration for the input information storage section, since a plurality of tasks can be set regardless of the processing state of the processor.

(2) The task information storage section can be used efficiently because the assignment of a plurality of tasks can be set freely.

(3) Since external terminals for task switching are not required, the processor package can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a pipelined processor according to an embodiment.

FIG. 2 is a block diagram showing in detail the configuration of the main parts of FIG. 1;

FIG. 3 is a diagram showing a storage example of an input information storage unit.

FIG. 4 is a diagram showing a storage example of a task information storage unit.

FIG. 5 is a timing chart of the pipeline processor shown in FIGS. 1 and 2;

FIG. 6 is a configuration diagram of main parts of a conventional pipeline processor.

Claims (1)

[Claims] 1. An input information storage unit that stores externally input data as task selection data and input data; a task information storage unit that stores a plurality of task processing information; A pipeline register given as the address of the input information storage unit,
A pipeline type processor, comprising program counter presetting means for presetting task selection data in the input information storage section to a program counter at the start of execution.