JPH02199844A - Schottky gate field-effect transistor - Google Patents

Abstract

PURPOSE:To comply with a request to make a gate length finer by a method wherein an upper-stage gate in a piled-up gate is made as a parallel gate which is formed not on a substratum gate but on an insulating film for sidewall use. CONSTITUTION:An active layer 2 is formed on a semiinsulating GaAs substrate 1 by an ion implantation operation; after that, WSi as a first-stage gate metal is applied onto it, and is processed; a gate 5 is formed. Then, SiO2 7 is deposited on it; W (tungsten) as a second-stage gate 6 is deposited on it; a photoresist 10 is deposited on it. The insulating films 7 and 12 are shaved by making use of the second-stage gate 6 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor field effect transistor having a highly heat-resistant Schottky electrode.

[Conventional technology]

Schottky gate field effect transistors made of compound semiconductors have had the problem that as the gate length becomes finer, the metal resistance of the gate increases, hindering higher frequency operation and higher gain.

In the conventional dummy gate process, this problem is solved by making the gate shape wider at the top, a so-called T-shaped gate or a mushroom gate. Also.

In the gate-first process, the above problem was solved by using a heat-resistant gate material with low resistance and by stacking it with a metal with low resistance, creating a so-called stacked gate structure.

Techniques related to these include JP-A-62-9677, JP-A-82-114274, and JP-A-62'=460.
No. 73 etc. are known.

However, stacked gates are susceptible to peeling due to thermal strain (stress) due to the difference in thermal expansion coefficient between the gate material used for stacking and the underlying gate material, and shape deterioration due to the difference in etching rate during dry etching. becomes a problem, and
What is the essential solution to fine gates due to the height restriction due to the aspect ratio and the restriction that the size of the upper gate cannot be made extremely large compared to the size of the underlying gate? It wasn't.

[Problem a that the invention attempts to solve]

In the gate-first process of the conventional Schottky gate field effect transistor mentioned above, stacked gates can only serve as a lifespan for the current process to cope with the increase in gate resistance due to the shortening of the gate length. I can not cope.

An object of the present invention is to provide a gate forming technique that can meet the demand for further miniaturization of gate length.

[Means to solve the problem]

In stacked gates, as long as the upper gate is placed on top of the underlying gate, and if the upper gate is spatially separated from the lower gate, the upper gate cannot be extremely larger than the underlying gate. Deterioration of the shape due to the difference in etching rate is also unavoidable. Therefore, the size of the upper gate can be made larger. In the current field effect 1 to transistors, LDD (Light Reduction)
Doped Drain: Lightly Doped
For drain structure, a side wall of an insulated film is provided next to the gate. Therefore, by providing the upper gate on this side wall, the size of the upper gate can be made much larger than in the past, and gate resistance can be reduced. That is, in the present invention, the upper gate in the stacked gate 1- is a parallel gate formed not on the underlying gate but on the sidewall insulating film.

[Effect]

According to the present invention, on the sidewall used to separate the gate and source/drain by the self-line process,
By forming another gate.

The lateral size can be increased by the side wall compared to a normal stacked gate. In addition, since the upper gate is not supported by the lower gate, there is no height restriction due to the aspect ratio.Furthermore, since the upper gate is formed on an insulating film, it can be easily etched during dry etching during gate processing. Since no damage is applied to the device, and the upper gate is not limited in size by the lower gate, the shorter the lower gate length is, the more advantageous it is over the conventional stacked gate.

〔Example〕

Figure 1 shows GaAsM formed on a GaAs semi-insulating substrate.
An example of an ESFET is shown. In this embodiment, WSi (tungsten silicide) is used for the first stage gate 5.
Although W (tungsten) is used for the gate of each stage, it is also possible to use other high melting point metals, their silicides or nitrides, or a combination of silicon. The source/drain layer 4 is formed by selective epitaxial growth in this embodiment, but the second stage gate 6
It is also possible to form by ion implantation using as a mask.

In Figure 1, (a) is a cross-sectional view of the FET, (b) is a top view, and (c) and (d) are cross-sectional views of the connection between the first and second gates. It is.

An insulating film 7 is placed around the first stage gate 5, and this insulating film s
A second stage gate 6 is formed on top of the gate 7.

(b) As shown in the figure, the first stage gate 5 and the second stage gate 6 are connected through a contact hole outside the active layer 2. The connection method is to make the first stage gate 5 and the second stage gate 6 overlap on the outside of the active M2, as shown in the figure (c), or to make the gate 5 of the first stage and the gate 6 of the second stage overlap on the outside of the active M2, as shown in the figure (d). There is a method of making a connection by making a hole in the gate 6 of each step and pouring the wiring metal into the hole.

FIG. 2 shows the manufacturing process of this embodiment. In this embodiment, the n10 layer 4 is formed by ion implantation.

After forming the active layer 2 by ion implantation on the semi-insulating QaAs substrate 1, activation annealing is performed, and WSi, which is the first stage gate metal, is deposited on the active layer 2 at a thickness of approximately 110 nm.
0n is deposited and processed to form the gate 5. The first stage gate length is 0.1-0.2 μm, and the height is 0.1 μm.
It is.

L D D (Lightly Doped Drai
Figure (a) shows that 5iOz was deposited to a thickness of about 30 nm as a through film 12 for ion implantation to form an n' layer in the n: structure, and then ion implantation for the n' layer was performed.

On top of that, deposit S i Ox'7 to a thickness of about 170 nm,
As shown in FIG. 3(b), about 1100 nm of W (tungsten) is deposited thereon as a second stage gate, and a photoresist 10 is deposited thereon.

Since the second stage gate 6 is wider than the first stage gate 5, it can be processed using a normal optical lithography process.

The gate length is 0.4 to 0.6 μm and the height is 0.1 μm.

The sheet resistance of tungsten is about 176 that of WSi, so
The gate resistor according to the present invention is made of only WSi and has a gate length x height of 0. It can be suppressed to about 1/10 of that of IXO and 2μ. Figure (c) shows the insulating films 7 and 12 cut away using the second stage gate 6 as a mask.

Using the second stage gate 6 as a mask, a source/drain ohmic layer (n10 layer) 4 is formed by ion implantation, and after annealing, a source/drain ohmic electrode (AuGe) 8 is provided. is the figure (d).

After this, by performing a wiring process, the GaAs according to the present invention is
MESFEiT is completed.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing gate resistance by having, in addition to the gate with a fine gate length formed on the active layer, a separate gate arranged parallel to the gate.

Since the above gate is formed on the insulating film, there is an effect that damage during processing of the upper stage gate does not reach the element.

Since the upper gate is separated from the lower gate on the active layer, there is an effect that the difference in etching rate during dry etching will not be a problem even if the materials are different.

[Brief explanation of the drawing]

FIG. 1 shows a GaAs MR3FEτ according to an embodiment of the present invention, in which (a) is a cross-sectional view, (b) is a top view, and (c) is a top view. (d) is a cross-sectional view of a connecting portion of two layers of gate electrodes. FIG. 2 is a sectional view showing the fabrication process of a GaAsMε5FET according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... Active layer (1 layer), 3... N-type conductive layer (17 layers), 4... Source and drain, 5, 6... ...High melting point metal, or its silicide or nitride, 7...Insulating film (SiOi or 5
iN), 8... Ohmic electrode, 9... Contact hole, 10... Photoresist, 11... Wiring metal, 1
2...Insulating film. Kaya l concave (α) tb)

Claims (1)

[Claims] 1. An active layer, an electron supply layer to the active layer, or an electron confinement layer is provided on the surface of the compound semiconductor, and a first high melting point metal, its silicide or nitride, or silicon is deposited on the layer. After depositing to form a Schottky electrode, an insulating film is deposited, and a second high melting point metal is electrically contacted with the first high melting point metal or its silicide, nitride, or silicon on the insulating film. Alternatively, a field effect transistor comprising silicide, nitride, or silicon. 2. A Schottky gate field effect transistor, characterized in that a source and a drain are formed by performing ion implantation using the second high melting point metal or its silicide, nitride, or silicon layer according to claim 2 as a mask. manufacturing method.