JPH02185068A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce a parasitic resistance effect and to increase the process margin of manufacturing an element by forming a field-effect transistor in which the thickness of source and drain regions are larger than that of a channel region. CONSTITUTION:Oxygen ions are implanted to a P-type silicon substrate 11, and a SOI board of a structure in which a silicon oxide film 12 is buried in the silicon substrate is manufactured. Then, this SOI silicon film 13 is partly oxidized to form a silicon oxide film 17, and the thickness of the SOI silicon film 13 corresponding to the channel of a field effect transistor is reduced. The silicon oxide film 17 is removed by etching, the exposed part of the silicon film 13 is oxidized to form a gate oxide film 18, and polycrystalline silicon is, for example, deposited on the whole surface as a gate electrode 19. It is so etched back that the thickness of the polycrystalline silicon film hold a sufficient value as a gate electrode. Thus, high mobility, high punchthrough voltage resistance, and high driving force are realized, sufficient film thickness is obtained for the source, drain regions 20 to reduce its parasitic resistance and to realize the easiness of forming a contact.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device, in which the film thickness of a channel region of an element is sufficiently thinned on an SOI substrate. The present invention relates to a method of manufacturing an ultrahigh-speed field effect transistor that has the advantages of a thin film transistor and has source/drain regions with a thickness that allows easy contact formation with low parasitic resistance.

(Prior Art) As LSI devices become more highly integrated, there is an increasing demand for faster switching operations and miniaturization of field effect transistors.

One type of transistor structure that satisfies these requirements is
There is an element structure in which an SOI film is thinned so that the thickness of the channel portion of the transistor is completely depleted by SOIJ during operation of the transistor, using a transistor with an 80mm structure. Regarding the thin film transistor characteristics, see, for example, Yoshimi et al.

'High performance SOIMO8F
ET using ultra-thin 8CHfi
1m' Technical Dig, of IBDM
1987, p. 640, 1987.

The characteristics of thin film transistors are superior to those of conventional non-thin film field effect transistors, but thin SOI
When forming a field effect transistor in a film, the parasitic resistance is large because the source/drain regions are also thin films, making it impossible to fully utilize the advantages of thin film transistors, and also because the source/drain regions are thin. However, there were drawbacks such as a small margin in the element manufacturing process for forming contacts.

(Problems to be Solved by the Invention) The present invention aims to reduce the parasitic resistance effect of the source/drain in a thin 11 SOI transistor and increase the process margin of the device fabrication process by adjusting the film thickness of the source/drain region to the channel. A method of forming a field effect transistor having a thickness greater than a region is provided.

[Structure of the invention]

(Means for Solving the Problems) The present invention is an SOI transistor in which only the channel region is thinned to a desired thickness by oxidation or etching, and the source and drain are formed thicker than the channel region. In particular, since thinning of the channel region and gate formation are carried out in a self-aligned manner, there is no need to consider the alignment margin between the thin film region and the gate region, and it is possible to thicken only the source/drain region without increasing the device area. A method of manufacturing a field effect transistor is provided.

(Function) According to the present invention, as the SOI film, the source and drain can be formed sufficiently thick as well as the channel region, so a differential chair can be manufactured without causing parasitic effects or increases in parasitic resistance due to thinning of the source/drain film. Since the channel region is made thinner, it is possible to manufacture a device having characteristics of a thin film transistor. Furthermore, it is possible to form the gate electrode of the field effect transistor in self-alignment with respect to the mask used when thinning the channel region.

(Example) An embodiment of the present invention will be described below with reference to the drawings, taking a method of manufacturing an N-type channel field effect transistor as an example.

FIG. 1 is a sectional view of the process.

First, as shown in Fig. 1(a), oxygen ions are implanted into a P-type silicon substrate αυ at a concentration of 10 ions at an acceleration voltage of 400 kV, and then annealed at 1300°C to form a silicon oxide film in the silicon substrate. An SOI substrate having a structure in which Q3 is embedded is manufactured.

At this time, the film thickness of each substrate is, for example, 2oooi for the silicon oxide film α, and 2oooi for the SOI silicon film a3.
Let it be 000A.

Next, element isolation is performed using, for example, the LOC08 method. At this time, since the film thickness of the SOI silicon film α3 is about 2000λ, element isolation is performed so that each element region remains in the form of an island. After element isolation, SOI silicon film (13
For example, 200λ QS is oxidized, and then a 100λ
OA is deposited, patterned, and the silicon nitride film in the area where the gate electrode is to be formed is removed (Fig. 1(b)).
.

Next, using this silicon nitride film αG as a mask, the SOI silicon film a is partially oxidized to form a silicon oxide film αD.
The thickness of the OI silicon film 03 is reduced. The film thickness is
The thickness of the silicon film in the channel part of the field effect transistor is such that the SOI substrate is completely depleted when the device is operated, for example, when the substrate density is 5×10 eve.
In this case, the channel portion is thinned by oxidation to 1500A (FIG. 1(C)).

Next, the silicon oxide JIIQ? ) is removed by etching, and the exposed portion of the silicon film Q3 is oxidized again to form a gate oxide film Q8 having a thickness of, for example, 200 Å. After that, as the gate electrode
ooi is deposited (Fig. 1(d)).

Next, etch-back planarization is performed using, for example, a planarization method using a resist, and the polycrystalline silicon α field on the silicon crab film αe is completely removed, and the polycrystalline silicon film thickness in other parts is reduced to the gate. K etchback is performed to maintain a sufficient film thickness as an electrode (eg, 3000A or more). Thereafter, the silicon nitride film αe is removed. Next, using the gate electrode αl as a mask, impurity ions, for example arsenic, are implanted into the source/drain regions at an acceleration voltage of 140 kV to form the source/drain regions (
Figure 1(e)).

After that, as an insulating film, for example, CVD8i0. 200O
After N is deposited (21), contact holes (2) are opened in the source, drain, and gate, wiring is made of, for example, AI (to) as electrodes, and patterning is performed to obtain a field effect transistor according to an embodiment of the present invention. According to this embodiment, S.O.
In a field effect transistor formed on an I film, only the channel region is made thinner, achieving the advantages of a thin film field effect transistor such as high mobility, high punch-through breakdown voltage, and high driving force, while also reducing the source/drain region CAK. Therefore, if a sufficient film thickness is obtained, it is possible to reduce parasitic resistance and facilitate contact formation.

〔Effect of the invention〕

According to the present invention, a method for manufacturing a field effect transistor that achieves high mobility, high punch-through breakdown voltage, high driving force, reduced parasitic resistance, and easy contact formation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment according to the present invention. 11...Silicon substrate, 12...Silicon oxide film (
interlayer insulating film), 13... silicon substrate, 14... silicon oxide film (element isolation), 15... silicon oxide film, 16... silicon 9ide film, 17... silicon oxide film, 18 ...gate oxide film, 19...gate electrode,
20... Source/drain, 21... Silicon oxide film (CVDSiOz), 22-... Hole, 23... Electrode. Agent Patent Attorney Noriyuki Chika Yudo Hikaru Matsuyama 2 Figure 1Figure 1

Claims (2)

[Claims] (1) A method for forming a field effect transistor on an SOI film on an insulating film, which includes forming a mask pattern on the SOI film so that a part of the SOI film is exposed; After selectively oxidizing the mask pattern, the oxidized film is etched to form an SOI film on which the mask pattern is not formed.
A method for manufacturing a field effect transistor, comprising the step of thinning a film portion and then forming a gate oxide film and a gate electrode on the thinned SOI film. (2) The method of manufacturing a field effect transistor according to claim 1, wherein the gate electrode is formed with the mask pattern left in place, and then the gate electrode is planarized and etched to the surface of the mask pattern.