JPH02183828A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To perform the multiplication of floating points at a high speed by using the carry signal received from a carry detector to perform the shift operations of a mantissa part and the control of the increment process of an exponent part and carrying out both rounding and exceptional processes in parallel with each other. CONSTITUTION:A floating point multiplier fetches the output data received from a fixed point multiplication circuit 10 and the rounding signal RD produced by a rounding process control circuit 17 to detects whether an overflow occurs in a rounding process or not. If so, a carry detector 15 sets the carry signal CO at 1. The signal CO is inputted to a shifter 19 of a mantissa part and a multiplexer 24 of an exponent part for control of the shift process carried out after the rounding process of the mantissa part and the increment process of the exponent part. The rounding and exceptional processes can be performed in parallel with each other with use of the detector 15. Then the critical paths are set as 10 15 24 40 42. Thus the computing speed is increased for a floating point multiplier.

Description

[Detailed Description of the Invention] (Summary of the Invention) An object of the present invention is to provide a floating-point multiplier that performs multiplication on numbers in floating-point notation, and which is faster than conventional floating-point multipliers. A floating point system that includes a fixed-point multiplication circuit that performs operations on each mantissa part of a number, a circuit that performs operations on each exponent part, a circuit that performs operations on each sign part, a rounding control circuit, a shifter, an incrementer, and an exception handling circuit. The multiplier is provided with a carry detector that inputs the output data from the fixed-point multiplication circuit and the rounding signal generated by the rounding control circuit and detects whether overflow occurs in the rounding process. The structure is configured such that the shift operation of the mantissa part and the increment process of the exponent part are controlled by the carry signal of , and the rounding processing and exception processing are processed in parallel.

[Industrial application field]

The present invention relates to a floating-point arithmetic unit that performs multiplication on numerical values in floating-point notation.

Floating-point arithmetic has a wider dynamic range and higher precision than fixed-point arithmetic, and recently there has been a growing demand for floating-point arithmetic that meets various advanced arithmetic requirements. Among these, high-speed processing of multiplication, which is a basic operation, is important.

[Prior art] First, the general floating point notation r E E E
Regarding floating point data formats, IEEE has single precision (32 bits) and double precision (64 bits) data formats. In the double precision data format, the sign part S is 1 bit, the exponent part E is 11 bits, and the mantissa part F is 52 bits, and represents the numerical value 11)'2E-1"'"5(1,F). Here, bias=1023. The present invention will be described below with regard to multiplication in this double-precision data format.

A conventional floating point multiplier is shown in FIG. 10 in this figure
is a fixed-point multiplication circuit, 12 is its partial product generation and addition circuit, and 14 is an addition circuit.

Further, 16 is a shifter, 17 is a rounding control circuit, 18 is an incrementer, and 19 is a shifter. Further, 20.21 is an adder circuit, 22.23 is an incrementer, 24 is a multiplexer, 30 is an exclusive OR circuit, 40 is an exception processing circuit,
41 is a constant device, and 42 is a selector. The two floating point numbers to be multiplied are A= (-1)"2"-b'm' (1
,Fa)B= (-1)"2°-b'a'(1,Fb)
shall be. C is the floating point number of these products.

It is assumed that the floating point multiplier 10 handles only normalized numbers.

When performing multiplication, first, the mantissa multiplication (1, Fa>
(1, Fb) is performed by the fixed-point multiplication circuit 10. If the multiplication of 53 pints x 53 hints is performed, the output of the adder circuit 14 is 106 bits, and 1. xx
It has the form x... or LX, XXX... This result is output from the adder circuit 14 and input to the shifter 16. Overflow signal O from adder circuit 14
Since it is necessary to perform normalization when FI is 1 (at the above tx, xxx...), the shifter 16
Shift the focus to the right. At this time, since it is necessary to add 1 to the exponent part, the signal OFI is also input to the incrementer 22.

Next, rounding is performed to match the normalized numbers to the output data format. The rounding control circuit 17 cuts off the digits below the LSB (in this example, the 53rd bit) in the output data format, and also rounds off the digits below the LSB (in this example, the 53rd bit).
It is determined whether 1 is to be added to B, and if .beta. is to be added, the signal RD is set to 1.

Then, the incrementer 18 performs an operation of adding 1 to the LSB of the output data of the shifter 16.

At this time, if each bit of the data is all 1, an overflow occurs and 0F2=1. In this case, it is shifted by one bit to the right by the shifter 19 to become a normalized number. This OF2 is also input to the multiplexer 24.

In addition, in the rounding process control circuit 17, from the shifter 16 to the 53
The 54th bit, .
Processing to output D=O is performed. That is, in the IEEE data format, the 106 bits of the multiplication result are 2°,
2-'2-2...2-522-532-542
-55...2105, 2-
52 is the LSB of the upper 53 bit data. 2-53
is guard bit, 2-S4 is round bit, 2-55
After that, the OR's are taken and combined into one as a stay key bit. The rounding control circuit 17 uses these LSBs, guard bits, round bits, stay key bits, and sign bits l-3N to set RD to 1 according to the rounding mode RM.
Decide whether to set it to O or O.

The exponent parts of the two floating point numbers A and B to be multiplied are subjected to Ea+Eb in an adder circuit 20, and -bias is added to the result in an adder circuit 21. Therefore, the output from the adder circuit 21 is the calculation result of Ea+Eb-bias. In the incrementer 22, +1 is added using OFI, which is 1, when overflow correction by normalization processing is required. In the incrementer 23, +1 is added to the output of the incrementer 22 in advance to correct overflow due to rounding processing, and the multiplexer 24 selects the output of the incrementer 23 when 0F2=1.

The calculation of the sign parts Sa and Sb of the floating point numbers A and B is performed by exclusive OR 30, and this result becomes the sign part SN of the product C. Finally, the exception processing circuit 40 performs exception processing, and depending on the result, the selector 42 selects either the output of the shifter 19 or the output of the constant generator 41, and the output of the selector 42 is the mantissa part of the multiplication result C, The output of the multiplexer 24 becomes the exponent part, and the output of the exclusive OR 3 becomes the sign part.

When the exponent part of the product result cannot be represented by the 11 bits and therefore overflows or underflows, or when there is an invalid overlap, the exception handling circuit 40 sends the output to the selector 42 instead of the output of the shifter 19. The constant set in the constant device 41 is selected in advance.

[Problem to be solved by the invention]

This floating-point multiplier performs multiplication as described above, so the critical path is 10→16→17.
-18→24-40-42.

Among the critical paths mentioned above, the incrementer 18
Since the processing speed of the exception processing circuit 40 is slow, the overall processing speed cannot be increased. Since the incrementer 18 is an adder circuit (+1 circuit), in the worst case, the carry will propagate through all 53 pins, which takes time. The exception handling circuit 40 is also suitable for simple exception handling, IE
The process is quite complicated in EE format, so it will take some time.
Ru.

It is an object of the present invention to provide a floating point multiplier that is faster than the conventional one by improving other parts, even though the incrementer and exception handling circuit take time.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the floating point multiplier has
Taking in the output data from the fixed-point multiplication circuit 10 and the rounding signal RD generated by the rounding control circuit 17,
A carry detector 15 is provided which detects whether an overflow occurs in rounding processing and sets a carry signal CO to 1 if an overflow occurs.

This carry signal CO is input to the shifter 19 for the mantissa part and the multiplexer 24 for the exponent part, and controls the shift process after rounding of the mantissa part and the increment process of the exponent part.

[Effect]

By providing this carry detector 15, parallel processing of rounding processing and exception processing becomes possible.
The path becomes 10-15→24→40→42.

Therefore, higher speed calculations than conventional floating point multipliers are possible.

〔Example〕

FIG. 2 shows an embodiment of the present invention. As in all figures, the same parts as in other figures are given the same reference numerals.

An example of the configuration of the carry detector 15 is shown in FIG.

As shown in the figure, this is an anime game) 15a, 15c.

15d and an or gate 15b. If the output data from the adder circuit 14 is double precision according to the IEEE standard, signal name: OFI POPi...F52GR 5 digits
: 2'2'2-'2-"2-"
2-54 Sticky. AND gate 15a is F
It takes in O-F51 and produces an output of 1 when they are all 1.

The AND gate 15c takes in this output and the OR outputs of OFI and F52, and produces a 1 output when these are 1, and the AND gate 15d makes its output CO 1 when this output and RD are 1. In other words, this circuit is 0FI-4, FO=F1=...=F51=1.
RD=1 or 0Fl=0. FO=F1=...
...-F52=1. When RD=1, a carry signal co is generated. This carry signal CO is equivalent to overflow OF2 in FIG. Carry signal CO is 1
At this time, the multiplexer 24 selects the output data of the incrementer 23, and the shifter 19 performs control to execute a 1-bit right shift. On the other hand, at C0-0, the output data 22 is selected at 24, and the input data is output as is without performing a shift operation at 19.

In this way, the carry detector 15 is processed in parallel with the shifter 16 and the rounding control circuit 17, and the multiplexer 2
Since the incrementer 18 and the shifter 19 are processed in parallel with respect to the exception processing circuit 40 and the exception processing circuit 40, the floating point multiplication process is sped up as a whole.

In FIG. 4, the incrementer 18 operates after the output RD of the rounding control circuit 17 is output, and as a result, an overflow 〇F2 appears, and the incrementer 18 operates sequentially in the order of... Then, the carry detector operates with the output RD, and the carry output CO is output, and the shifter 19 and multiplexer 2
4 control signal is output, thereby incrementer 18
and the exception handling circuit 40 can operate in parallel.

(Effects of the Invention) As described above, according to the present invention, rounding processing and exception processing can be processed in parallel, which greatly contributes to speeding up floating-point multipliers.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a circuit diagram showing a specific example of a carry detector, and Fig. 4 is a block diagram showing a conventional example. It is. In Figure 1, 10 is a fixed-point multiplication circuit, 15 is a carry detector, 1 is a processing control circuit,
18 is an incrementer, a lid, 24 is a multiplexer,
22.2 crementer, 40 is an exception handling circuit, 42; 14 is 7 is rounded 19 is shi 3 is in is select Applicant Fujitsu Co., Ltd. Representative Patent Attorney Minoru Aoyagi!

Claims (1)

[Scope of Claims] 1. A fixed-point multiplication circuit that performs calculations on each mantissa part of a floating-point number to be multiplied, a circuit that performs calculations on each exponent part, a circuit that performs calculations on each sign part, a rounding process control circuit, In a floating-point multiplier equipped with a shifter, an incrementer, and an exception processing circuit, output data from a fixed-point multiplication circuit (10) and a rounding signal (RD) generated by a rounding control circuit (17) are input, and rounding is performed. A carry detector (1
5), the shift operation of the mantissa part and the increment process of the exponent part are controlled by the carry signal (CO) from the carry detector, and rounding processing and exception processing are processed in parallel. floating point multiplier.