JPH11102353A - Floating-point product-sum operating element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a floating-point product-sum operating element simple in configuration, high in performance and increased in product-sum operating speed without causing any overflown digits. SOLUTION: This element has a floating-point multiplier 101 which does not have a right shift circuit for normalization, a digit matching shifter 102 which performs floating-point addition of an intermediate result of product-sum operation and the output of the floating-point multiplier 101, a mantissa adder 103 which adds two mantissa parts having their digits matched by the digit matching shifter 102, and an intermediate result register 106 which holds the intermediate result of the product-sum operation; and normalization in the product-sum operation is omitted by using the intermediate result register 106 which can hold a 4-bit integer part since a one-bit right shift due to a mantissa part overflow after addition is not performed to speed up the product sum operation. Then the product sum operation is advanced in an unnormalized state and after the accumulation of all product items is completed, a normalizing shifter 107 which has both functions for a right and a left shift obtains the final product-sum operation result in the form of a normalized floating-point number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point multiply-accumulate unit, and more particularly, to a floating-point multiply-add unit for improving (speeding up) a floating-point multiply-add operation speed.

[0002]

2. Description of the Related Art In recent years, applications requiring a high-speed product-sum operation, such as digital signal processing and digital servo control by software, require a floating-point product-sum logic operation in order to obtain higher precision. Often.

When performing a product-sum operation using a conventional floating-point arithmetic unit, normalization and rounding after the operation are performed each time in floating-point addition for accumulation. In a conventional floating-point arithmetic unit, since only floating-point addition may be executed independently, normalization of operation words is always performed. However, in such a floating-point arithmetic unit, when addition is repeated as in a product-sum operation, both a mantissa left shift by normalization after addition and a mantissa right shift by digit alignment in the next addition occur. In some cases, both shift operations are executed unconditionally despite the fact that they can be canceled out, making it difficult to speed up the product-sum operation.

In order to solve such a problem, Japanese Patent Publication No.
Japanese Unexamined Patent Application Publication No. 61-224 discloses an invention for improving the speed of a floating-point product-sum operation by omitting the normalization of the intermediate product-sum result by making the intermediate result of the product-sum operation a double-precision denormalized number. The invention relating to the product-sum operation unit, hereinafter referred to as “conventional example”) is disclosed.

Here, the outline of the above-mentioned conventional example (“floating point multiply-accumulate unit” disclosed in the above-mentioned publication) will be specifically described with reference to FIG. In FIG. 3, a floating-point multiply-accumulate unit includes: a floating-point multiplier for calculating each product term in a multiply-accumulate operation on an input floating-point number (operand, multiplicand) 531 and an input floating-point number (operand, multiplier) 532 501; an alignment shifter 502 for floating-point addition of the intermediate result of the product-sum operation and the output of the floating-point multiplier 501; A mantissa adder 503; • an exponent adder 5 that adds “1” to the larger exponent 510 selected by the digit shifter 502 when a mantissa overflow occurs in the mantissa adder 503;
04; a 1-bit right shifter 505 that adjusts the addition result of the mantissa adder 503 by right-shifting when a mantissa overflow occurs due to the mantissa adder 503; Floating point register 50 to keep
6; and a left normalization shifter 507 for normalizing the non-normalized product-sum operation result only at the end.

Here, the mantissa overflow means that the operation result between the mantissas exceeds "2" and cannot be handled as a normalized number as it is.

In the prior art, as shown in FIG. 3, several units for performing floating-point multiplication are provided inside the floating-point multiplier 501. Specifically, the floating-point multiplier 501 has two operands to be multiplied (input floating-point number 5
A multiplier 520 for obtaining the product of the mantissas of (31, 532); a register for holding the multiplication result of the multiplier 520, wherein the product of the normalized mantissas is at most "11.1111 ..."
A register 521 in which the integer part of the register is 2 bits because it is expressed in binary notation; a 1-bit right shifter 522 for normalizing when a mantissa overflow occurs by the multiplier 520; , Two operands to be multiplied (input floating point 53
An exponent part adder 523 for adding exponent parts of (1,532); an exponent part incrementer 524 for incrementing the exponent part when a mantissa overflow occurs in the multiplier 520; Output of shifter 522 and exponent incrementer 5
And a floating point register 525 holding 24 outputs.

[0008] In the above-mentioned conventional "floating-point multiply-accumulate unit 501", the mantissa adder 503 causes a dropout, and even if a single floating-point addition requires a left shift for normalization. The floating-point operation is speeded up by treating it as double-precision non-normalized floating-point data without shifting.

[0009]

By the way, in the ordinary floating-point addition, after the addition of the mantissa part, if the mantissa part exceeds 2, the mantissa is shifted right by one bit to return to a normalized number, and the mantissa is lost. A left shift is required to return to a normalized number when the integer bits of the part become zero.

In the above-mentioned conventional "floating-point multiply-accumulate unit", the mantissa is operated in double precision to eliminate left shift due to digit loss, thereby increasing the speed. Since the number of bits is one, the right shift by one bit when the mantissa exceeds "2" cannot be omitted. In addition, since floating-point multiplication requires a result including normalization, a 1-bit right shift is also required when the mantissa exceeds “2”.

Further, in the product-sum operation, the digit alignment shifter 50 is used.
Since the mantissa digit alignment of the addition operand by 2 and the storage of the intermediate result in the floating-point register 506 are repeatedly executed, the digit alignment shifter 502, the mantissa adder 503, and the 1-bit right shifter existing in this data path are provided. The processing speed of the product-sum operation is determined by the sum of the operation speeds of the respective circuits in 504 and the like.

For example, as shown in FIG. 3, "one clock for multiplication of mantissa parts of input operands, one clock for right shift after multiplication, one clock for digit alignment and addition of mantissa parts,
Assuming that one clock is required for the right shift after the addition and one clock for the normalized left shift of the final result, each processing is pipelined, and even if the multiplication and the addition are executed in parallel, one processing is required. In order to find the product term and add it to the intermediate result, an execution time of two clocks is required each time, which hinders an increase in the product-sum operation speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to increase the sum-of-products operation speed more than in the conventional example, without overflowing digits. Another object of the present invention is to provide a floating-point multiply-accumulate unit having a high-performance and simple configuration.

[0014]

A floating-point multiply-accumulate unit according to the present invention provides a mantissa part of a multiplication result with a 2-bit integer part, and further includes a digit shifter, a mantissa adder, and an intermediate result of an addition unit. By providing a multi-bit integer part to all mantissa parts of registers and the like, the 1-bit right shift when the mantissa part exceeds "2" is omitted to speed up the product-sum operation. Thus, the above object has been achieved.

That is, a floating-point multiply-accumulate unit according to the present invention includes: a floating-point multiplier having no right shift circuit for normalization; and A multiplication result register capable of holding an integer part of bits; a floating-point adder that aligns two floating-point numbers that are not normalized, performs floating-point addition, and outputs the result without normalization; An addition result register that receives an output of the floating-point adder and can hold an integer part of a plurality of bits in a mantissa; a normalization shifter that normalizes the content of the addition result register to obtain a final product-sum operation result; Denormalizing the product-sum operation by sequentially adding each multiplication result output from the floating-point multiplier and the content of the addition result register by the floating-point adder It is performed in the state, which the "matters specifying the invention" Wo (claim 1), thereby to achieve the above object. In other words, with this configuration, the 1-bit right shift due to the overflow of the mantissa can be omitted, and the product-sum operation can be speeded up.

Further, the floating-point multiply-accumulate unit according to the present invention, when the most significant bit of the mantissa part of the addition result register becomes "1", uses the normalization shifter as needed to execute the multiply-accumulate operation. By normalizing the intermediate result, it is possible to prevent the mantissa part of the intermediate result from overflowing. In this case, a high-performance floating-point multiply-accumulate unit that does not overflow can be realized.

Further, the floating-point multiply-accumulate unit according to the present invention includes the intermediate product-sum result input to the floating-point adder according to the value of the most significant bit of the mantissa part of the addition result register. , Or from the normalization shifter ”(claim 3). This makes it possible to realize a high-performance floating-point multiply-accumulate unit with a simple configuration and no overflow.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of a floating-point multiply-accumulate unit according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of a first embodiment of a floating-point multiply-accumulate unit according to the present invention, in which normalization is performed only after a multiply-accumulate operation. It shows.

In FIG. 1, the floating-point multiply-accumulate unit includes: a floating-point multiplication for obtaining each product term in a multiply-accumulate operation on an input floating-point number (operand) 531 and an input floating-point number (operand) 532 A digit shifter 102 for performing floating-point addition of an intermediate result of the product-sum operation and an output of the floating-point multiplier 101; and adding two mantissa parts digit-aligned by the digit shifter 102. A mantissa adder 103; an intermediate result register for holding an intermediate result of the product-sum operation, and an intermediate result register capable of holding a 4-bit integer part because it does not shift right by one bit due to an overflow of the mantissa after addition. 106; a normalization shifter 107 for normalizing the unnormalized product-sum operation result only last, wherein the mantissa part held in the intermediate result register 106 is “2 or more” Because if there is the case of "less than 1", the normalization shifter 10 with both the right shift and left shift function corresponding to each
7 and.

Further, the floating-point multiplier 101 has several units therein for performing floating-point multiplication. Specifically, two operands (floating point numbers) to be multiplied 53
A multiplier 120 for calculating the product of the mantissas of 1,532; a register for holding the multiplication result of the multiplier 120; the product of the normalized mantissas is a maximum of "11.1111 ..." (binary notation) ), A register 125 in which the integer part of the mantissa of the register is 2 bits, and an exponent adder 123 that adds the exponents of the two operands 531 and 532 to be multiplied. Have.

The most significant feature of this embodiment is that neither the multiplier nor the adder has a 1-bit right shifter for normalizing the mantissa overflow. If the right shifter is not provided, as the product-sum operation is continued, the integer part of the mantissa becomes large, and if the number of digits of the mantissa that can be held by the intermediate result register 106 is exceeded, the upper bits are lost and a malfunction occurs. Therefore, it is necessary to predict how many values the mantissa can take at most.

In the case of normalized floating-point multiplication, the value that the mantissa of the product can take in one multiplication is:
It is between "1.0000 ..." and "11.1111 ...".

Next, an operation of adding floating points having mantissa parts in this range will be described. If the exponents of the two operands (input floating-point numbers) 531 and 532 to be added are different, one of the mantissas is shifted to the right by digit shift. That is, since the value is small if the mantissa is considered alone, when considering the maximum value of the mantissa for floating-point addition, the case where the exponent is the same and the mantissa is the maximum may be considered.

As described above, since the maximum value of the mantissa of the multiplication result is "11.1111 ...", the addition result when both addition operands have the maximum mantissa is "111.111".
1 ... ".

In the second addition in the multiply-accumulate operation, the multiplication result whose mantissa is "11.1111 ..." and the mantissa are "111.11
Since the first addition result of "11 ..." is added, the maximum value is "1011.1111 ...".

Similarly, the result of the third addition is “1111.111
If the integer part of the mantissa is 4 bits, the third addition result, that is, the 1-bit right shift for normalizing the mantissa overflow, is omitted until the product-sum operation of the fourth product term is omitted. The upper bits are not lost.

For example, in a three-dimensional graphics operation, since the product-sum operation of the fourth product term is diversified, the floating-point product-sum operation unit according to the present embodiment is used to limit the product-sum operation to the fourth product term. By performing the operation, a floating-point multiply-accumulate operation can be realized at high speed.

The floating-point multiply-accumulate unit of this embodiment is
The fact that the speed can be further increased as compared with the product-sum operation speed of the floating-point product-sum operation unit of the conventional example shown in FIG. 3 will be described below.

As in the conventional example, in the multiply-accumulate operation, the steps from the mantissa digit alignment of the addition operand by the digit alignment shifter 102 to the storage of the intermediate result in the floating point register 106 are repeatedly executed. In the floating point multiply-accumulate unit, the digit shifter existing in the data path
If only 102 and the mantissa adder 103 can operate, the product-sum operation can be repeatedly executed, and the operation speed of the product-sum operation is not limited as in the conventional example because a one-bit right shift occurs every time.

For example, as shown in FIG. 1, assuming that "one clock is required for multiplication, one clock is required for digit alignment and mantissa addition, and one clock is required for normalized left shift of the final result", it is the same as the conventional example. In order to find one product term under the condition of (1) and add it to the intermediate result, it is possible to execute the process with one clock every time.

As described above, the floating-point multiply-accumulate unit of the first embodiment provides a 2-bit integer part to the mantissa part of the multiplication result, and further adds a digit shifter 102 of the addition unit.
By giving a multi-bit integer part to all mantissa parts such as the mantissa adder 103 and the intermediate result register 106,
Omit the 1-bit right shift when the mantissa exceeds 2,
Since the normalization during the product-sum operation is omitted, the product-sum operation can be speeded up, which is different from the conventional example.

(Second Embodiment) The floating-point multiply-accumulate unit according to the first embodiment does not perform any normalization during the multiply-accumulate operation, but only after the end of the multiply-add operation.
This is an example in which normalization is performed by 107 (see FIG. 1). When the number of product terms can be limited to, for example, four, the configuration as shown in FIG. 1 is sufficient. However, when performing a product-sum operation of five or more product terms, a circuit obtained by slightly modifying the circuit configuration of FIG. This can be dealt with by a configuration, and more specifically, by adding a selector for normalizing the intermediate result as needed.

FIG. 2 is a circuit diagram of a floating-point multiply-accumulate unit according to a second embodiment of the present invention, showing an example in which intermediate results are normalized as necessary. In FIG. 2, units having the same functions as those of the above-described constituent units in FIG. 1 are denoted by the same reference numerals, and a description thereof will be omitted.
The description of the floating-point multiply-accumulate unit according to the embodiment will be given.

In FIG. 2, the difference from FIG. 1 is that the product-sum intermediate result to be provided to the alignment shifter 102 in accordance with the most significant bit of the mantissa of the intermediate result register 106 is "whether obtained from the intermediate result register 106 or That is, a selector 230 for selecting “whether to obtain from the chemical shifter 107” is added. Components other than the selector 230 are the same as those in the first embodiment shown in FIG.

By adding the selector 230, normalization can be performed only when the intermediate result of the product-sum operation causes a mantissa overflow, so that it is not necessary to limit the number of product terms. Can prevent the mantissa part from overflowing, thereby realizing a high-performance floating-point multiply-accumulate unit with a simple configuration, and making the floating-point multiply-add unit of the present embodiment more flexible. Can be applied.

[0037]

The floating point multiply-accumulate unit according to the present invention comprises:
As described in detail above, a multi-bit integer part is given to the mantissa register of the multiplication result, and a multi-bit integer part is added to all the mantissa parts of the adder digit shifter, the mantissa adder, and the intermediate result register. By providing, the 1-bit right shift when the mantissa exceeds “2” is omitted, so that the product-sum operation speed can be increased as compared with the conventional example.

When the most significant bit of the mantissa of the addition result register becomes "1", the intermediate result of the multiply-accumulate operation is normalized using a normalization shifter, and the mantissa of the intermediate result overflows. Therefore, a high-performance floating-point multiply-accumulate unit can be realized.

Further, according to the value of the most significant bit of the mantissa part of the addition result register, the intermediate product-sum result input to the floating-point adder is "whether to obtain from the addition result register or to obtain from the normalization shifter. ”, A high-performance floating-point multiply-accumulate unit with a simple configuration and no overflow can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a floating-point multiply-accumulate unit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the floating-point multiply-accumulate unit according to the present invention.

FIG. 3 is a circuit configuration diagram of a conventional floating-point multiply-add unit.

[Explanation of symbols]

 101 Floating point multiplier 102 Digit alignment shifter 103 Mantissa adder 106 Intermediate result register 107 Normalization shifter 120 Multiplier 123 Exponent adder 125 Register 230 Selector

Claims (3)

[Claims] 1. A floating point multiplier having no right shift circuit for normalization, a multiplication result register receiving an output of the floating point multiplier and capable of holding a plurality of bits of an integer part in a mantissa, A floating-point adder that performs digit alignment of two floating-point numbers that have not been processed, performs floating-point addition, and outputs the result without normalization, and receives an output of the floating-point adder, and outputs a multi-bit integer in a mantissa. An addition result register capable of holding a portion, and a normalization shifter for normalizing the contents of the addition result register to obtain a final product-sum operation result, wherein each of the multiplication results output from the floating point multiplier is floated. A floating-point multiply-accumulate unit that performs a multiply-accumulate operation in a denormalized state by successively adding with a decimal point adder. 2. When the most significant bit of the mantissa of the addition result register becomes 1, the intermediate result of the product-sum operation is normalized by using the normalization shifter as needed.
2. The floating point multiply-accumulate unit according to claim 1, wherein the mantissa of the intermediate result is prevented from overflowing. 3. According to the value of the most significant bit of the mantissa part of the addition result register, an intermediate product-sum result input to the floating-point adder is obtained from the addition result register or the normalization shifter. 3. The floating-point multiply-accumulate unit according to claim 2, further comprising a selector for selecting "whether or not".