JPS58186840A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the execution time of floating-point operation, by performing the correcting arithmetic of an exponent part at a postnormalizing stage with regard to all combinations which occur possibly at a precedent stage. CONSTITUTION:Byte adders 14-29 performs the correcting operation of the exponent part in parallel to the operation of the mantissa part of a parallel adder 7 and latches the operation result in registers 30-45, respectively. A selector 46 once receiving the numbers of Os succeeding from the high-order digit a the mantissa part from a decoder 10 selects and outputs the value of one of the registers 30-45. Namely, the selector 46 selects and outputs the correction contents coincident with the correction number of the exponent part received from the decoder 10. The final result is obtained by putting the exponent part after the correction together with the postnormalized mantissa part. In this case, the complement part and mantissa part of the final result are outputted almost similarly. Therefore, the operation of the exponent part is completed at the precedent stage, so the total operation time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to an arithmetic device that speeds up a floating-point arithmetic operation by performing correction operations for an exponent part caused by bost normalization in parallel.

Prior art floating point operations can perform extremely large numbers with high precision. Furthermore, a floating point number consists of a sign (to), an exponent part which is a power of 16, and a mantissa part which is a hexadecimal number.The length of these numbers is fixed, for example, one word length. There are three formats: short precision, 2-word long precision, and 4-word extended precision. That is, the short-precision floating-point number shown in FIG. 1(a), the high-precision floating-point number shown in FIG. 1(b), and the
For both extended precision floating point numbers in c), the first 1 bit is the sign of the mantissa, where 1° represents the negative sign and "OI+" represents the positive sign. 6 decimal digits, long precision bits 8 to 63 and 14 hexadecimal digits
16 digits with extended precision of bits 8 to 63.72 to 127
Each has 28 base digits. In addition, in the mantissa part, the decimal point is located to the left of the most significant digit.

Next, the exponent part represents the number that should be a power of 16 in bits 1 to 7, and as shown in FIG. Specify 63. That is, the top row of Figure 2 is +63, the middle row is +7,
The lower row shows the exponent of -64.

FIG. 3 depicts a prior art floating point adder/subtractor. A register 1 and B register 2 are registers that latch the first and second floating point operands, respectively.

The preshifter (PS) 3 has the function of determining the magnitude of the exponent parts of the first and second operands prior to execution of floating point addition/subtraction, and selecting the larger exponent part and the mantissa of the smaller operand. It has the function of shifting the part to the right to match the digit of the larger operand. For example, the first
The exponent parts of the operand and second operand are each +5.
5, when +53, the second is the difference (2 digits) between both exponents.
This will shift the mantissa of the operand to the right.

C register cow and ]) register 5 are respectively the above ps3
This register receives and latches the mantissa part of the operand with the larger exponent part and the mantissa part after digit alignment with the smaller exponent part.

E register 6 is a register for receiving and latching the larger exponent part from PS3.

PA7 is a parallel adder that performs addition and subtraction of the mantissa parts of the first and second operands latched in the 0 register 4 and the D register 5.

7 register 8 is a register that latches the result of P A, 7 above.

The G register 9 is a register that latches the exponent part of the E register 6 as is.

Dll! The OIQ is a decoder that checks the number of consecutive O's from the top of the calculation result latched in the F register 8 and outputs the boss normalized number and the corrected number of the exponent part of the calculation result.

PSHII is a post shifter that shifts the calculation result to the left based on the Horst normalized number output from the Dxo 10.

The BA 12 is a byte adder that corrects the exponent part based on the exponent part correction number outputted from the DEa 10 as well.

H register 3 is a register that latches the final results output from PSHII and BA12.

FIG. 4 is an operation time chart at the bottom normalization stage of FIG. 3.

In the parallel adder 7, the digit-aligned first and second
Addition and subtraction are performed on the mantissa parts of the operands, and the results are latched into the F register 8.

In the conventional device, normalization is performed after the operation of the parallel adder 7 (bost normalization). For example, when the operation result is the exponent part r + 55J, the mantissa part roo1234...-1, this information is sent to the decoder 10. is timing t1
(FIG. 4(a)), the decoder 10 outputs the number 12 of consecutive 0s in the mantissa part from the upper part and the correction number 1-2 in the exponent part to the byte adder 12 and the boss shifter 11 at the timing. It is output at t2 (Fig. 4(b)'). The post-shifter 11 shifts the operation result received from the F register 8 to the left by two digits based on the boss normalization number "2" received from the decoder 10, and then outputs it to the H register 13 at timing t (Fig. 4). (O)). Decoder 10
The time from timing t2 at which the boss normalized number is received to timing t3 at which it is output to the H register 13 is about 1 machine cycle.

On the other hand, when the byte adder 12 receives the boss normalization i r2J from the decoder 1o at timing t2, the byte adder 12 receives the G
Input the larger value "+55" in the exponent part from register 9, perform addition of r+55J and 1-2, and output the operation result to the exponent part of register H and 3 at timing t4 (Figure 4). (d)). The time (t) from timing t2 when the decoder 1o receives the boss normalized number to timing t4 when it is output to the H register 13 is about 1 machine cycle. Therefore, the exponent part of the H register 13 is
The signal is latched approximately one machine cycle later than the mantissa, and the proportion of this delay time in the machine cycle is relatively large. As described above, the conventional technology has the disadvantage that it takes time to correct the exponent part after latching the calculation result in the y register 8. A boss normal rice station is required after the flkm calculation stage, and this There is a drawback that most of the delay in the boss normalization stage is spent on calculating the exponent part based on the above correction value nimo.

OBJECT OF THE INVENTION In order to eliminate such conventional drawbacks, an object of the present invention is to provide a data processing system that can significantly shorten the delay time required after a mantissa operation is completed and shorten the execution time of a floating point operation. The purpose of this invention is to provide a processing device.

In order to achieve the above object, in the data processing device of the present invention, a plurality of exponent part arithmetic units are provided in the floating point arithmetic unit, and the plurality of exponent part arithmetic units are operated simultaneously in parallel with the operation of the mantissa part, At the same time as the mantissa calculation ends, one of the outputs of the exponent calculator is selected based on the value indicating the number of consecutive O digits in the upper part of the mantissa of the calculation result, and the exponent part generated by post-normalization is corrected. It is characterized by immediately terminating the calculation. That is, in the present invention,
In order to speed up the arithmetic unit, the prediction logic is strengthened, and the correction of the exponent part performed in the boss normalization stage is calculated for all possible combinations in the previous stage. As a result, floating-point addition and subtraction conventionally required, for example, approximately 4 cycles, whereas in the present invention, results can be obtained in approximately 5 cycles.

Embodiment of the Invention FIG. 5 is a block diagram of a floating point arithmetic unit showing an embodiment of the invention, and FIG. 6 is an operation time chart of the boss normalization stage of FIG.

A new feature according to the invention is that a plurality of byte adders 14 to
29, registers 30 to 45 for latching the results, and a selector 46 for selecting the contents thereof. The plurality of byte adders 14 to 29 perform correction of the exponent part at the previous stage, which should normally be performed at the post-normalization stage, and as many byte adders as there are for all possible combinations are provided.

Let M to N be the correction values of the exponent that may occur after the mantissa calculation. These values are + for floating point addition/subtraction operations.
1 to -6, and +1 to -1 for high-precision calculations.
4. As shown in FIG. 1, short-precision floating point data has a mantissa of only 3 bytes (6 digits), and a guard digit is added to the calculation, resulting in a total of 7 digits.

Therefore, the exponent part is corrected up to -6, and +1 is for the case where a digit is lost as a result of addition and the mantissa part is shifted one digit to the right. In addition, in long precision, the mantissa has 7 bytes (14 digits), and the guard digits total 15 digits.

Therefore, the exponent part needs to be corrected to -14.

Note that the guard digit is provided to reduce the decrease in accuracy due to shifting. For example, if the mantissa part is ro
When o1234j is 6 digits, it is shifted 2 digits to the left by the postshifter 11 to become J1234J, resulting in 4 digits and the precision decreases.To compensate for this, one more digit is added, and the mantissa is roo12345J and 7 digits from the beginning. Keep it.

In addition, in the case of overflow digits, when an overflow (carry) occurs from the most significant digit as a result of mantissa calculation, unless one digit is reserved above the most significant digit, the carry value will be erased. Therefore, add +1 digit above the 0 digit from the beginning. The +1 digit is then shifted one digit to the right in post shifter 11 and normalized.

In the pre-shifter 3, after determining the magnitude of the exponent part of the [-2] second operand, the larger value of the exponent part is output to the E register 6. Multiple byte adders 14-2
9 receives the exponent part (e.g. r+55J) latched in the E register 6 as one input, and inputs a value between +1 and -6 for short precision and +1 and -14 for long precision. Input to the other side and perform addition and subtraction respectively. The output of each byte adder 14 to 29 is stored in a register (GPI to ()14)
Latched at 30-45. The selector 46 selects the contents of the registers 30-45 based on the output of the decoder 1°.

To explain the series of operations shown in FIG. 5, at the same time, a plurality of byte accelerators 14 to 29 perform correction operations that may occur after the exponent part. All combinations of are calculated in the mantissa calculation stage.

The result of the above prediction operation is latched into the registers 30 to 45 at the same time as the result of the operation of the mantissa part is latched into the F register 8. Next, in the post-normalization stage, the decoder 10 examines the mantissa operation result latched in the F register 8 and outputs the actually necessary correction value. Based on the output of the decoder 10, the selector 46 selects the contents of the register latching the result of the byte adder predicting the true correction value.

The calculation result of the parallel adder 7 is, for example, an exponent part [155,
:I' is the mantissa part 1-001234...'', and when these pieces of information are output from the F register 8 to the decoder 10 at timing t (Fig. 0(a)), the decoder 10 The number of O's in the mantissa part consecutive from the upper part is "2",
The correction number "-2" for the exponent part is output to the selector 46 and the boss shifter 11 at timing t2 (FIG. 6(b)). Based on the Boston normalized number r2J received from the decoder 10, the Boston 7 data 11 calculates the operation result r'0O1234 inputted from the F register 8 based on α1).
Shift left by 2 digits to r 1234-・
...-1, and then outputs at timing t3 (6th
Figure (0)).

On the other hand, +M k byte adders 14 to 29 G: Jl
, the exponent part correction calculation is performed in parallel with the calculation of the mantissa part of the parallel adder 7, and in the case of FIG. 5, the exponent part "+55" and "+1" ~
Perform 16 additions and subtractions of r−1jl, and the result is r+
56J~"+41J is latched into a plurality of registers 30 to 45, respectively. When the selector 46 receives the boss normalized number [2-1" from the decoder 10 at timing t2, it latches one of the plurality of registers 30 to 45. selects the value of one register 33 and outputs it at timing t3 (
Figure 6(d)). In other words, the register 30 is
1” correction, register 31 is rOJ correction, register 3
2 latches the results of r-11 correction and register 33 latches the results of "-2" correction, so selector 4
6 is the correction number of the exponent received from the decoder 10 "-2"
" Select and output the correction contents that match.

The most N-connected i is 02) in the post-normalized mantissa part. It is obtained by combining the exponent parts after the above correction.

In the present invention, as shown in FIG. 6(c)Cd), the timing t when the post-normalized number is received from the decoder
2, the timing t3 at which the boss shifter 11 outputs the result of the shift operation and the timing t3 at which the selector 46 selects and outputs one of the correction results are almost the same, so the complement and mantissa of the final result are The parts will be output almost simultaneously. In the past, most of the delay time in the boss normalization stage was spent calculating the exponent part, but in the present invention, since the calculation of the exponent part is completed in the previous stage, only one selection is required. It only takes time, and the total calculation execution time is shortened.

FIG. 7 is a diagram showing the correspondence between the output result of the parallel adder 7 in FIG. 5, the shift (shift) ffl of the mantissa part and the correction amount of the exponent part, that is, the Hyde adder to be selected. In FIG. 7, the -1 digit represents an overflow digit, and G represents a guard digit. Note that the output of the adder input to the decoder 10 can also be predicted directly from the C register 4 and D register 5, which are input registers of the adder, and input to the decoder IIKO1○.

Also, according to FIG. 7, 16 byte adders are required, but BA○ can be omitted because the correction value is 0, and there is a means to reduce the number of required adders in this way. However, if all the calculation results of the mantissa part are O, the exponent part is not corrected because it is treated as a significance exception.

In the 7th adder output digit, X is a number other than ○, that is, 1
~F, and Y represents an arbitrary number, that is, Q - F. Therefore, when the second output from the top is obtained for both short precision and long precision, the tentative &i has already been normalized. , there is no need to perform the expansion in the post-shifter 11, and there is no need to select the corrected value of the exponent part in the selector 46.Furthermore, in both the short precision and the multi-tank 7, the output of the lowest stage, that is, the mantissa part is When the number reaches 0, the exponent part is also meaningless, so no correction is made. Above 2
With two exceptions, correction of the mantissa in the boss shifter 11 (7th
(third column from the right in the figure) and also corrects the exponent part selected by the selector 46 (second column from the stone in FIG. 7). Note that the rightmost column in FIG. 7 shows byte adders 14 to 29 corresponding to correction of the selected exponent part. In other words, in the top row of short precision, numbers other than O are overflowing digits (
-1), a one-digit right shift is performed to correct the mantissa, and a +1 result is selected to correct the exponent, and 14 of BAP l is selected as the byte adder at this time. In the third short precision, the overflow digit (-1) and the second-most digit (0) of the mantissa are 0, and there is a number other than O in the next digit, so the correction of the mantissa requires a left shift of 1. The digit is corrected, and the result of -1 is selected for the exponent part correction, and 16 of BAl is selected as the byte adder at this time. Hereafter, in the same way, the mantissa is shifted to the left by 6 digits and the exponent by -6 for short precision, and the mantissa is shifted to the left by 14 digits and the exponent by -14 for high precision. ing.

Note that the present invention is applicable to all calculations that require a bottom normalization operation. For example, this includes floating point multiplication and division. However, in the case of multiplication and division, only two byte adders are required, so in terms of performance, the effect is not great in the case of addition and subtraction.

As described in detail, according to the present invention, the delay required after a mantissa operation is completed can be significantly shortened, so that the execution time of a floating-point operation can be shortened.

[Brief explanation of the drawing]

Figure 1 is a data format diagram of a floating point number, Figure 2 is a diagram showing the expression of the exponent part of Figure 1, Figure 3 is a block diagram of a conventional floating point adder/subtractor, and Figure 4 is a diagram of the exponent part of Figure 3. FIG. 5 is a block diagram of a floating point adder/subtractor showing an embodiment of the present invention; FIG.
47 is a time chart of the boss normalization operation shown in FIG. 5, and FIG. 47 is a diagram showing the correspondence between the output of the parallel adder shown in FIG. 5 and the correction amounts of the mantissa and exponent parts. 06) 1.2: Operand register, 3: Pre-shifter, 4.
．． 5: Arithmetic input register, 6 Second register, 7: Parallel adder, 8: F register, 10: Decoder, 11: Boss shifter, 14-29: Byte adder, 3 Q-4.
5: Correction register, 46: Selector 0 Patent applicant Hitachi, Ltd. Attorney Patent attorney Masaaki Isomura 1, 1st
Figure 2 Figure 4 Figure 6 Figure t2 Figure 5

Claims (1)

[Claims] In a floating point arithmetic unit that calculates the exponent part and the mantissa part separately, multiple exponent part arithmetic units are provided that operate in parallel with the mantissa part calculation, and as soon as the mantissa part calculation is completed, the calculation result continues to the upper part. A data processing device characterized in that, based on a value indicating the number of 0 digits, one of the calculation results of the plurality of exponent part calculation units is selected as the exponent part.