JPH0217865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronized circuit, and more particularly to a phase synchronized circuit that generates a signal synchronized with information read from a magnetic recording device used in an information processing device.

Conventionally, the synchronization signal, which is the output of a phase synchronization circuit that generates a synchronization signal synchronized with the information read from a magnetic recording device, is such that when there is a "0" or drop in the information, the frequency of the synchronization signal that follows it changes instantaneously. It gets lower. Therefore, when there is a sudden shift in the read information, this information is often not sampled and an error occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase synchronization circuit that can suppress fluctuations in a sampling clock for sampling information as small as possible even when there is a dropout or the like in sequentially changing input information.

In order to achieve the above object, a phase synchronized circuit according to the present invention constitutes a part of an information reproducing circuit of a magnetic recording device, and in a phase synchronized circuit that self-synchronizes and samples information, it synchronizes with information from the magnetic recording device. a phase detector that detects a phase difference with a signal; a low-pass filter that receives the output of the phase detector; a voltage-controlled oscillator that controls an oscillation frequency according to the output of the low-pass filter; and a voltage-controlled oscillator that receives the voltage-controlled oscillation output. a delay line that outputs the delayed output as a test signal and further delays the test signal to output secondary and tertiary sampling clocks; and a data detection circuit that reads the output of the phase detector using the test signal. , and a selection circuit for selectively outputting the second or third sampling clock based on the output of the data detection circuit.

According to the above configuration, even if the information is zero or dropped, instantaneous changes in the synchronization signal can be prevented, and the information read from the magnetic recording device can be accurately reproduced and transmitted. The purpose is completely achieved.

The present invention will be explained in more detail below with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of a phase locked circuit according to the present invention.

In the figure, 1 is a phase detector, 2 is an LPF (low pass filter), and 3 is a voltage controlled oscillator. These circuits are known as phase locked loops. The synchronizing signal a, which is the output of the voltage controlled oscillator 3, has different delay times (phases) due to the delay line 4.
It is divided into three-phase signals b, c, and d, which are the next, second, and third-order sampling clocks. These are referred to as a test signal b, a preceding signal c, and a standard signal d.

Information e from a magnetic recording device (not shown) is connected to a phase detector 1 together with a synchronizing signal f, and its output, a phase difference signal g, is connected to an LPF 2 and a drop detection circuit 6.

This drop detection circuit 6 is a data detection circuit that detects that the information e is "0", and is composed of a falling trigger D-type flip-flop, and the phase difference signal g is connected to the D input of the drop detection circuit 6. be done. The test signal b is connected to the CP input of the drop detection circuit 6, and when the information e is "0" or a drop, the Q output h of the drop detection circuit 6 is "0",
Q output i becomes "1".

The output i is input to an OR circuit 5 consisting of AND elements 5a, 5b and an OR element 5c, and the AND element 5
A is ANDed with the preceding signal c at a. On the other hand, the Q output h is similarly ANDed with the standard signal d in the AND element 5b. These AND outputs are further logically summed in OR element 5c.

FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1. Waveform A is the input information signal e, B,
C and D represent the test signal b, preceding signal c, and standard signal d, respectively, E the phase detector output g, F the Q output h of the drop detection circuit, and G the synchronization signal f. In waveform A, when the input information e is "1", the phase detector output g is read into the drop detection circuit 6 by the test signal b, and the Q output h becomes "1" {waveform B}. Therefore, Q output h
Accordingly, the OR circuit selects the standard signal d of waveform D and outputs the synchronizing signal f of waveform T. Also, when input information e is “0” or dropped, check signal b
As a result, g ("0") is read into the drop detection circuit 6, so the output i becomes "1", and the preceding signal c is selected this time to output the synchronizing signal f.

That is, as is clear from the above description, when the input information is "1", the standard signal d is generated, and when the input information is "0" or dropped, the preceding signal c is generated as the synchronizing signal f. This operation is similar even when the input information is shifted from the position where it should originally exist to the next pulse position.

As explained above in detail, the phase locked circuit according to the present invention generates a synchronization signal preceding the primary synchronization signal instead of the primary synchronization signal when the input information that changes sequentially is zero or drops. Alternatively, even in the case of a drop, the synchronizing signal is output, so that changes in the frequency of the synchronizing signal can be kept as small as possible.

Therefore, even if the read information suddenly shifts, the input information can be accurately reproduced and transmitted.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a phase locked circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1. 1... Phase detector, 2... LPF (low pass filter), 3... Voltage controlled oscillator, 4... Delay line, 5...
OR circuit, 6...Drop detection circuit, a...Control voltage line, b...Test signal line, c...Preceding signal line, d...Standard signal line, e...Information line, f...Synchronization signal line, g...Phase difference signal line , h...Q output line, i... output line.

Claims (1)

[Claims] 1. In a phase synchronization circuit that self-synchronizes and samples information, which constitutes a part of an information reproducing circuit of a magnetic recording device, a phase detector detects a phase difference between information from the magnetic recording device and a synchronization signal;
a low-pass filter that receives the output of the phase detector as an input; a voltage-controlled oscillator that controls the oscillation frequency according to the output of the low-pass filter; a delay line that delays a test signal to output secondary and tertiary sampling clocks; a data detection circuit that reads the output of the phase detector using the test signal; and a data detection circuit that reads the output of the phase detector using the test signal; and a selection circuit that selects the next sampling clock and outputs it as the synchronization signal.