JPS5918756Y2 - automatic phase control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an automatic phase control device for controlling the phase of reception timing of a synchronous modem used for data transmission.

FIG. 1 is a block diagram showing a conventional automatic phase control device for reception timing, and FIGS. 2 and 3 are timing charts thereof.

First, 1 in FIG. 1 is an oscillation circuit.

This oscillation circuit 1 is the source of generating reception timing.

The output of this oscillator circuit 1 is sent to a frequency divider circuit 2, where
The reception timing is created by dividing the frequency to a predetermined frequency.

The output of this frequency dividing circuit 2 is output to a sample pulse selection circuit 3.

This is for determining the timing for extracting phase comparison information from the output of the sample pulse selection circuit 2.

The sample pulse from the sample pulse selection circuit 3 is output to a register 4, and the register 4 generates phase comparison information C using this sample pulse.

On the other hand, 5 is a differentiation circuit that differentiates the input wave a and generates a pulse b at its rising point.

The pulse b obtained by this differentiating circuit 5 is output to a phase comparator circuit 6.

The phase comparator circuit 6 compares the pulse b with the information C from the register 4, and changes the phase of the output of the frequency divider circuit 2 based on the result.

As mentioned above, the lowercase alphabet a in FIG. 1 is an input introduced into the differentiating circuit 5, and is a lock wave including phase and frequency jitter.

Further, b is the pulse obtained by the differentiating circuit 5, C is the output of the register 4, that is, phase comparison information, and d is the output produced by the frequency dividing circuit 2, which is the reception timing.

Further, e is a clock having the same period as the input a which is synchronized with the reception timing d.

2a to 2C and 3a to 3C respectively show input a, pulse b, and phase comparison information C in FIG. If you are behind, Figure 3 shows the situation if you are ahead.

Next, the operation will be explained.

In the case of FIG. 1, the input a and the reception timing d are adjusted to the sample pulse selection circuit by aligning the input a with the position of the pulse b obtained by the differentiating circuit 5 at the rising point of the phase comparison information C output from the register 4. This is to match the phase relationship determined in step 3.

That is, in FIG. 1, the input a is differentiated by the differentiating circuit 5 to create a pulse b (FIG. 2 b) corresponding to the rising point of the human power a, and this pulse b is sent to the phase comparator circuit 6.

Further, the frequency divider circuit 2 divides the frequency of the high-speed pulse generated by the oscillation circuit 1 to create a reception timing d, and at the same time creates a clock e having the same period as the input a and sends it to the register 4.

Then, the sample pulse selection circuit 3 detects the changing point of the clock e and shifts it by a desired phase.
It is sent to register 4 as a sample pulse.

The register 4 samples the clock e using the pulse from the sample pulse selection circuit 3 to create phase comparison information C having the same cycle as the input a, shifted by a desired phase from the reception timing, and sends it to the phase comparison circuit 6.

This phase comparison circuit 6 compares the pulse b and the phase comparison information C, and as shown in FIG. assumes that the reception timing d is delayed in phase with respect to the input a, and controls the frequency divider circuit 2 to advance the reception timing d and the phase comparison information C by a predetermined amount Δfalse.

Furthermore, as shown in FIG. 3, if the pulse b is in the "L" region with the phase comparison information C shown in FIG. 3C, it is assumed that the phase of the reception timing d is ahead of the input a ,
The phase comparator circuit 6 controls the frequency divider circuit 2 to delay the reception timing d and the phase comparison information C by Δ.

By the way, in the conventional automatic phase control device as described above, the phase correction width is uniformly determined as △θ.
A steady phase shift such that △θ11) (i.e.,
It is effective for frequency shift), but △02 (△ island 〉1
It cannot cope with a steady phase shift such as △θ1),
The reception timing d causes out-of-synchronization.

The only way to prevent this situation is to increase △^, but conventionally, the reception timing d is always corrected by △θ, so if △θ is made too large, the jitter of the reception timing itself becomes large. However, there was a drawback that caused a decrease in reliability during demodulation.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method, and by giving weight to the amount of correction △θ according to the size of the phase shift between input a and reception timing d, a considerably large steady state An object of the present invention is to provide an automatic phase control device that can cope with large phase shifts and reduce constant phase jitter in reception timing.

Embodiments of the automatic phase control device of this invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of one embodiment.

In FIG. 4, parts that are the same as those in FIG. 1 are given the same reference numerals, explanations thereof are omitted to avoid duplication, and parts different from those in FIG. 1 will be mainly described.

In FIG. 4, the oscillation circuit 1, frequency divider circuit 2, sample pulse selection circuit 3, register 4, differentiation circuit 5, and phase comparator circuit 6 are completely the same as in FIG.

However, the shift register 7 is connected to the input terminal of the differentiating circuit 5.
The difference is that this is newly added.

This shift register 7 is a shift register for shifting the input a, outputting it to the differentiating circuit 5, and converting the pulse b obtained by the differentiating circuit 5 into a pulse train.

Next, the operation of the automatic phase control device of this invention constructed as described above will be described with reference to the time charts shown in FIGS. 5 to 7.

First, FIGS. 5a to 5C and FIGS. 6a to 6C respectively show input a, pulse b, and phase comparison information C in FIG. If the reception timing is constantly delayed by △θ (one period of the differential pulse train) with respect to the received signal, then Fig. 6 shows that the reception timing is constantly delayed by 3△θ.
Indicates if progress is being made.

Now, in FIG. 4, input a enters the shift register 7.

Also, the differentiating circuit 5 inputs a from the contents of the shift register 7.
Create a train of n (5 in this example) pulses indicating the rising points of .

Then, the frequency divider circuit 2 divides the high-speed pulse generated by the oscillation circuit 1 to create the reception timing d, and at the same time, the input a
A clock e synchronized with the reception timing d is generated and sent to the register 4 with the same period.

On the other hand, the sample pulse selection circuit 3 outputs a sample pulse at a point shifted by a desired phase from the change point of the clock e, and sends it to the register 4.

This register 4 samples the clock e using the pulse from the sample pulse selection circuit 3, creates phase comparison information C having the same cycle as the input a shifted by the reception timing and a desired phase, and sends it to the phase comparison circuit 6.

This phase comparison circuit 6 compares pulse b and phase comparison information C, and pulse b is 1 in the rH, region of phase comparison information C.
If there are m pieces (1+m=n) in the "L" area, (1
-m) Control the frequency divider circuit 2 to advance the phase by Δθ.

In this case, the minimum correction amount Δθ must be selected to be temporally equal to the period of the pulse train.

In the state already shown in FIG. 5, since the pulse b is 1-m=1, the phase comparator circuit 6 advances the phase of the frequency divider circuit 2 by Δθ.

If this phase delay is temporary, pulse b and phase comparison information C will have a different relationship at the next clock change point, but if a steady phase delay of △θ is added to this, then (In other words, if the frequency of the received signal is high), even at the next change point of clock e, pulse b and phase comparison information C
have the same phase relationship and become stable in the state shown in FIG.

Moreover, in the state shown in FIG. 6, the pulse b is lm=-3
Therefore, the phase comparator circuit 6 changes the phase of the frequency divider circuit 2 by 3△
Delay by θ.

In this case, similarly to the above, if the phase lead of 3Δθ is steady (that is, if the frequency of the received signal is low), the state shown in FIG. 6 will be stabilized.

In this way, in this embodiment, the stationary 5△θ of the received waveform
Advance, 3△θ advance, △θ advance, △θ delay, 3△θ delay,
It has 6 types of stable states corresponding to 5△θ delay,
In an intermediate state among these six types of states, two adjacent states are repeated.

The reception timing jitter in this case is Δθ.

In the above example, n25 is used, but n can be any natural number if necessary. In that case, the circuit is (
It has n+1) types of stable states.

In the above example, a pulse train is output as the output of the differentiating circuit 5, that is, as the pulse b, but FIG. ), outputs time information equivalent to n△θ, applies advance control in the rH region of phase comparison information C, and conversely outputs time information equivalent to n△θ.
In this region, delay control may be applied to cancel the difference.

As described above, according to this invention, by weighting the amount of phase correction depending on the size of the phase shift,
Since multiple stable states are provided for a steady phase shift, the steady timing remains small and can follow a large phase shift.

Therefore, it is possible to cope with a fairly large steady phase shift, and to reduce the constant phase jitter of reception timing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional automatic phase control device, and Figs. 2a to 2C show phase relationships when the reception timing is ahead of the received signal in the above automatic phase control device. Time charts, Figures 3A to 3C are time charts showing the phase relationship when the reception timing is ahead of the reception signal in the automatic phase control device as above, and Figure 4 is the automatic phase control device of this invention. Block diagrams showing the configuration of one embodiment of the control device, and FIGS. 5A to 5C are stable states when the reception timing is constantly delayed by Δθ with respect to the reception signal in the automatic phase control device described above. 6A to 6C are time charts showing a stable state when the reception timing is steadily advanced by 3Δθ with respect to the reception signal in the automatic phase control device, respectively. FIGS. 7a to 7c are time charts showing waveforms when signals of different formats are used as phase control information in the automatic phase control device as described above.

Claims (3)

[Scope of utility model registration request] (1) A shift register that shifts the input, a differentiation circuit that differentiates the input shifted by this shift register to obtain a pulse train, an oscillation circuit, and divides the output of this oscillation circuit to create reception timing and at the same time A frequency dividing circuit that creates a clock synchronized with the reception timing with the same period, a sample pulse selection circuit that outputs a sample pulse at a point shifted by a desired phase from the change point of the clock output from this frequency dividing circuit, and this A shift register that samples the clock output from the frequency divider circuit using the sample pulse output from the sample pulse selection circuit and generates phase comparison information of the same period as the above reception timing and the input shifted by the desired phase; a phase comparison circuit that compares the comparison information with the pulse output from the differentiation circuit and controls the frequency division circuit by weighting the amount of phase correction according to the reception timing and the magnitude of the phase shift of the phase comparison information; Automatic phase control device. (2) Registration of a utility model characterized in that a pulse train having a period temporally equal to the minimum correction amount and a clock having the same period as an input synchronized with internally generated timing are used as information for weighting the amount of phase correction. An automatic phase control device according to claim 1. (3) A utility model characterized in that a pulse having a time length that is an integral multiple of the minimum correction amount and a clock having the same period as an input synchronized with the internally generated timing are used as information for weighting the phase correction amount. An automatic phase control device according to claim 1.