JPS593715A - Data demodulating device - Google Patents

Abstract

PURPOSE:To facilitate demodulation by causing oscillations at a frequency equal to a write frequency and generating pulural out-of-phase signals, finding phase differences from read pulses, and selecting a signal with the best phase and separating data. CONSTITUTION:The oscillations 6 are caused at the frequency equal to the write frequency and plural signals 8-10 which are out of phase with one another are generated by a signal generator 7 from the oscillation output. The read pulse signal 1 and one of the plural signals 8-10 are supplied to a phase detector 2, whose detection output is sent to a selector 11. The selector 11 sends out a signal of te best phase relation among the signals 8-10 as a data separation signal 5 on the basis of the output of the phase detector 2. Consequently, an inexpensive demodulating device with good performance is composed of simple circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data demodulating device with a simple and inexpensive configuration that correctly reproduces data from a high-density magnetic storage device without being affected by peak shifts caused by magnetic interference.

(Usually referred to as a floppy disk device (hereinafter referred to as FDI))
The read pulse read from the data bit is a combination of a data pulse indicating the recorded data and a clock pulse indicating the head of the data bit. In order to read the data recorded on the FDD, it is necessary to extract only the data pulse from the read pulse, which is a combination of the two types of pulses.

Therefore, a signal (data separation signal) is generated that separates the range that can be read as data from the read pulse read from the FDD, that is, the range that is the data pulse, and this signal is used to separate only the data pulse from the read pulse. Separate and replay data. Magnetic storage devices such as FDDs, especially in the case of high-density recording, suffer from magnetic interference.
The recorded pulse interval is not constant, and a slight deviation, so-called peak shift, occurs. Therefore, the data separation signal is
It is necessary to always follow the read pulse and generate it in synchronization so as not to be affected by peak shift. In other words, the data separation signal must always be generated at an optimal phase with respect to the read pulse. Normally, this optimal phase is one in which the data pulse is near the center of the data separation signal, and conventionally, when generating such a signal, a data demodulator with a circuit as shown in Figure 1 was used. devices have been used. This is a phase-locked loop (PLL).
), 1 is the read pulse read from the FDD, 2 is the phase detector, and 5 is the low-pass F wave filter (LPF).
and an amplifier, 4 a voltage controlled oscillator (VCO), and 5 a data separation signal. The phase detector 2 detects the phase of the data separation signal 5 with respect to the read pulse 1 from F'DD, and the detected phase difference is converted into a voltage change by the LPF and amplifier 3, thereby controlling the VCO 4 to detect the read pulse. The data separation signal 5 is made to have an optimal phase with respect to the signal 1. FIG. 2 is a signal waveform diagram explaining the above operation, in which (a) shows the read pulse 1 and (b) shows the data separation signal 5. In the case of this figure, the initial data separation signal 50 phase is slightly ahead of the optimum phase with respect to the read pulse 1. This phase advance is detected by the phase detector 2, and this detection output is converted into a voltage control signal by an LPF or an amplifier and given to the VCO 4. In this case, the voltage control signal works to lower the oscillation frequency of the VCO 4. , second
As shown in the figure, the data separation signal (b) gradually synchronizes to the optimum phase with respect to the read pulse (a).

Most of the PLL-based data demodulation circuit shown in FIG. 1 is usually an analog circuit, and in order to obtain a data separation signal generation circuit with good performance, the circuit becomes complicated and the cost becomes high. Further, since the VCO controls the oscillation frequency by the voltage value, it is easily influenced by the power supply voltage, etc., and it is difficult to adjust the power supply voltage, LPF, amplifier, etc.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance, low-cost data demodulation device that does not have the above-mentioned drawbacks.

In order to achieve the above object, the present invention includes an oscillator that oscillates at a frequency equal to the write frequency of a storage device, a signal generator that generates multiple types of signals with different phases from the output of this oscillator, and an oscillator output and a lead. A phase detector for detecting a phase difference between pulses and a selection circuit for selecting an optimal phase from among a plurality of types of output from a signal generator according to the output of the phase detector and outputting the selected signal as a data separation signal. did. A phase shift occurs due to a so-called peak shift, but since the reading frequency of the storage device is equal to the writing frequency, if phase control is not performed by frequency control as in the conventional PLL, but by using the present invention, It can be configured with a simple digital circuit, reducing cost.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 6 is a diagram showing one embodiment of the present invention, and FIG. 4 is an operation explanatory diagram showing signals of each part. In FIG. 3, 6 is an oscillator with an output frequency equal to the write frequency, and 7 is a plurality of types of signals 8, 9, and 10 (
In Figure 4, (a), 'b), (c) respectively.
11 is a read pulse 1.
and one output signal 8 of the signal generator 7 ((a) in Fig. 4).
) is given to the phase detector 2, and the optimal phase is determined as the data separation signal 5 for the read pulse 1 (indicated by (d) in FIG. 4) from among the signals 8, 9, and 10 according to the detected output. (9 in Figure 3. (b) in Figure 4: This is a selection circuit that selects 1. The signal shown as (a) in Figure 4 is divided into three parts A, B, and C. The phase detector detects in which part of A, B, or C the read pulse shown as (d) is located.In part (a) of FIG. There are parts A, B, and C, respectively, because the phase relationship between the data separation signal and the read pulse is defined from the level change point of the data separation signal to the level change point, and the no-i level period is also the low-level period. This is because they have the same meaning. In the case shown in Figure 4, the lead nozzle (d) is in the part B, so the signal with the optimal phase as the data separation signal is (b). The selection circuit 11 selects the signal (b) (signal 9 in FIG. 3) as the data separation signal 5 and outputs it.
If the read pulse is in part A, signal (a) is selected, and if it is in part C, signal (C) is selected. If A and B, B,! :C, When there is a read pulse between C and A, the same signal as when it was at either part, for example, the signal (a), (
You may decide to select the signals (a) and (C) as the data separation signals, or you may decide to select the signals (a) and (b) as the data separation signals.
), (c) and a different phase (for example, the intermediate phase of each)
It is also possible to prepare the following signals and select each one. In the embodiment shown in FIG. 3, signals with three types of phases are used as targets to be selected as data separation signals, but the number of signals may be four or more types, for example. However, in that case, it goes without saying that it is necessary to perform phase detection according to the type. The key is to prepare in advance multiple types of signals that have a frequency equal to the write frequency and differ only in phase, and then select and use the one with the optimal phase for the read pulse as the data separation signal. be.

As explained above, according to the present invention, the data separation signal generation circuit, which conventionally has been constructed mostly from analog circuits and thus tends to be expensive, can be constructed from a simple digital circuit, resulting in inexpensive and high-performance data demodulation. A device is obtained.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram illustrating the operation of an example of a conventional data separation signal generation circuit. 1... Read pulse 2... Phase detector 5... Data separation signal 6... Excavator 7.・Signal generator 8.9.10...Signals 11 with equal frequencies and different phases...Selective circuit agent Patent attorney Bo 1) Li Xin 1st 2nd Figure $3 Diagram 4

Claims (1)

[Claims] A data demodulator that generates a data separation signal for separating and reproducing data from a composite pulse of a data pulse and a clock pulse read from a storage device includes an oscillator having an output frequency equal to the write frequency of the storage device, and an oscillator output from the oscillator output. a signal generator that generates a plurality of types of signals each having a different phase; a phase detector that detects a phase difference between the oscillator output and the composite pulse; and a plurality of outputs of the signal generator according to the output of the phase detector. a selection circuit that selects one of the signals and outputs it as the data separation signal.