JPH0217829B2 - - Google Patents

Info

Publication number
JPH0217829B2
JPH0217829B2 JP57196802A JP19680282A JPH0217829B2 JP H0217829 B2 JPH0217829 B2 JP H0217829B2 JP 57196802 A JP57196802 A JP 57196802A JP 19680282 A JP19680282 A JP 19680282A JP H0217829 B2 JPH0217829 B2 JP H0217829B2
Authority
JP
Japan
Prior art keywords
sorting
output
data
bit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57196802A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5987575A (ja
Inventor
Yoshinobu Myano
Koji Hashiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19680282A priority Critical patent/JPS5987575A/ja
Publication of JPS5987575A publication Critical patent/JPS5987575A/ja
Publication of JPH0217829B2 publication Critical patent/JPH0217829B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/14Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP19680282A 1982-11-11 1982-11-11 デ−タ並び換え回路 Granted JPS5987575A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19680282A JPS5987575A (ja) 1982-11-11 1982-11-11 デ−タ並び換え回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19680282A JPS5987575A (ja) 1982-11-11 1982-11-11 デ−タ並び換え回路

Publications (2)

Publication Number Publication Date
JPS5987575A JPS5987575A (ja) 1984-05-21
JPH0217829B2 true JPH0217829B2 (index.php) 1990-04-23

Family

ID=16363887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19680282A Granted JPS5987575A (ja) 1982-11-11 1982-11-11 デ−タ並び換え回路

Country Status (1)

Country Link
JP (1) JPS5987575A (index.php)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3917522B2 (ja) 2001-02-28 2007-05-23 富士通株式会社 フーリェ変換装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57134773A (en) * 1981-02-13 1982-08-20 Fujitsu Ltd Testing method for fourier transforming device

Also Published As

Publication number Publication date
JPS5987575A (ja) 1984-05-21

Similar Documents

Publication Publication Date Title
US4897837A (en) Test circuit having selective by pass arrangement for test data
JPH0760400B2 (ja) 論理回路の診断方法
US4913557A (en) Intergrated logic circuit having testing function circuit formed integrally therewith
US4389723A (en) High-speed pattern generator
JPH0217829B2 (index.php)
US5136701A (en) Processing unit containing DMA controller having concurrent operation with processor wherein addresses and data are divided into two parts
JPH01110274A (ja) 試験回路
US2807002A (en) Delay selection matrices
US5321641A (en) Pseudo random pattern generation circuit
JP2924030B2 (ja) クロック信号選択回路
JPH05128898A (ja) 半導体記憶装置
JP3003328B2 (ja) クロック信号回路
JP2643576B2 (ja) 高速フーリエ変換用番地発生回路
KR930008038B1 (ko) 메모리 제어회로
KR100199190B1 (ko) 데이타 포착회로
JPH0227686B2 (ja) Jozankairo
JPH04217121A (ja) パラレル/シリアル変換回路
Bass et al. Multiplier architecture for digital filters
JPH0628151A (ja) シリアルデータのパラレルラッチ回路
JPH02139957A (ja) 半導体集積回路
JPH05143289A (ja) 加算回路
JPH06130135A (ja) スキャンパステスト方式の半導体集積回路
JPH0540602A (ja) レジスタフアイルのスキヤン方式
JPS63232620A (ja) 出力回路
JPS62103733A (ja) ビツト重み変換装置