JPH02177369A - Manufacture of silicon diaphragm - Google Patents
Manufacture of silicon diaphragmInfo
- Publication number
- JPH02177369A JPH02177369A JP22418988A JP22418988A JPH02177369A JP H02177369 A JPH02177369 A JP H02177369A JP 22418988 A JP22418988 A JP 22418988A JP 22418988 A JP22418988 A JP 22418988A JP H02177369 A JPH02177369 A JP H02177369A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buried layer
- type
- silicon substrate
- diaphragm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 42
- 239000010703 silicon Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000866 electrolytic etching Methods 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 20
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Pressure Sensors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、量産性が良く、安価で、精度のよいシリコン
ダイアフラムの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a silicon diaphragm that is mass-producible, inexpensive, and accurate.
〈従来の技術〉
第4図は従来より一般に使用されている従来例の構成説
明図で、半導体圧力センサに使用されている例を示す。<Prior Art> FIG. 4 is an explanatory diagram of the configuration of a conventional example that has been commonly used in the past, and shows an example used in a semiconductor pressure sensor.
第4図(イ)は半導体圧力センサの平面図、(ロ)は半
導体圧力センサの横断面図を示す。FIG. 4(A) shows a plan view of the semiconductor pressure sensor, and FIG. 4(B) shows a cross-sectional view of the semiconductor pressure sensor.
図において、1はn形のシリコン単結晶で作られたダイ
ヤフラムであり、凹部2を有し、更に凹部2の形成によ
り単結晶の厚さの薄くなった起歪部3とその周辺の固定
部4とを有している。In the figure, reference numeral 1 denotes a diaphragm made of n-type silicon single crystal, which has a concave part 2, and a strain-generating part 3 in which the thickness of the single crystal has become thinner due to the formation of the concave part 2, and a fixed part around it. 4.
固定部4は連通孔5を有する基板6にガラス薄膜7を介
して陽極接合などにより固定されている。The fixing part 4 is fixed to a substrate 6 having a communication hole 5 via a glass thin film 7 by anodic bonding or the like.
起歪部3は単結晶の(100)面とされ、その上にはそ
の中心を通る結晶軸<001>方向で起歪部3と固定部
4との境界付近に例えば剪断形ゲージなどの感圧素子8
が不純物の拡散により伝導形がP形として矩形状に形成
されている。The strain-generating portion 3 is a (100) plane of a single crystal, and a sensor such as a shear type gauge is placed on the surface near the boundary between the strain-generating portion 3 and the fixed portion 4 in the <001> direction of the crystal axis passing through its center. Pressure element 8
is formed into a rectangular shape with the conductivity type being P type due to the diffusion of impurities.
この感圧素子8はその長平方向に電源端(図示せず)が
形成され、ここに電圧或いはt汰が印加される。印加圧
力Pがダイヤフラノ、1に与えられると、これによって
生じた例えば剪断応力τに対応した電圧が感圧素子8の
長手方向のほぼ中央に形成された出力@i(図示せず)
に得られる。This pressure sensitive element 8 has a power source end (not shown) formed in its longitudinal direction, to which a voltage or voltage is applied. When an applied pressure P is applied to the diaphragm 1, a voltage corresponding to, for example, shear stress τ generated by this is generated at an output @i (not shown) approximately in the longitudinal center of the pressure sensitive element 8.
can be obtained.
これによって、印加圧力Pに対応した電圧が出力端に得
られる。As a result, a voltage corresponding to the applied pressure P is obtained at the output end.
ところで、この様なダイアフラムを製造するには各種の
方法があるが、一般には(a>等方性のケミカルエツチ
ングにより製造するか(b)fl方性のケミカルエツチ
ングにより製造するかの方法がとられるが、このほかに
(c)n+シリコン基板にn形のエピタキシャル層を積
みn形のエピタキシャル層をエツチングストップ層とし
て電解エツチングによりn”シリコン基板に孔開けをす
る製造方法もある。By the way, there are various methods for manufacturing such a diaphragm, but generally, the two methods are (a) manufacturing by isotropic chemical etching or (b) manufacturing by fl-tropic chemical etching. However, there is also a manufacturing method (c) in which an n-type epitaxial layer is stacked on an n+ silicon substrate and a hole is formed in the n'' silicon substrate by electrolytic etching using the n-type epitaxial layer as an etching stop layer.
〈発明が解決しようとする問題点〉
しかしながら、この様な従来の半導体圧力センサの製造
方法は以十に説明するような問題がある。<Problems to be Solved by the Invention> However, such a conventional method for manufacturing a semiconductor pressure sensor has problems as described below.
(イ)第1の製造方法(a)によりダイアフラムの凹部
の加工を行うとその寸法精度を出すことが容易ではなく
、シリコンの中の不純物の濃度差を利用したエツチング
ストップ層を設けてダイアフラムの厚さを制御する方式
を採用しても半径方向の寸法精度が悪い。(b) When processing the concave portion of the diaphragm using the first manufacturing method (a), it is not easy to achieve dimensional accuracy. Even if a thickness control method is adopted, dimensional accuracy in the radial direction is poor.
(ロ)第2の製造方法(b)によりダイアフラムの凹部
の加工を行う場合は寸法117度は良いが、ダイアプラ
ムの起歪部の形状が4角形、8角形などに限定され、面
と面とが交差するところに角部が出来てこの部分に応力
集中が作用し高応力下での使用が難しい。(b) When machining the concave portion of the diaphragm using the second manufacturing method (b), a dimension of 117 degrees is good, but the shape of the strain-generating portion of the diaphragm is limited to a quadrangle, an octagon, etc. A corner is formed where the two intersect, and stress concentration acts on this part, making it difficult to use under high stress.
(ハ)第3の製造方法(C)によりダイアフラムの凹部
の加工を行う場合は高濃度のn+シリコン基板が入手し
難く、またダイアフラムの凹部の半径方向の寸法精度が
充分でない。(C) When processing the concave portion of the diaphragm using the third manufacturing method (C), it is difficult to obtain a high concentration n+ silicon substrate, and the dimensional accuracy of the concave portion of the diaphragm in the radial direction is not sufficient.
などの間頭がある。There is a head between such things.
本発明は、この問題点を解決するものである。The present invention solves this problem.
本発明の目的は、証産性が良く、安価で、精度のよいシ
リコンダイアフラムの製造方法を提供するにある。An object of the present invention is to provide a method for manufacturing a silicon diaphragm with good reliability, low cost, and high precision.
く問題点を解決するための手段〉
この目的を達成するために、本発明は、測定圧力により
変位する起歪部の形にパターニングされた高濃度のn形
シリコンの埋込み層をP形シリコン基板の一方の面に形
成し、
前記埋込み層の上にエピタキシャル成長をさせてn形エ
ピタキシャル層を形成し、
該n形エピタキシャル層を貫通し前記埋込み層に接続し
該埋込み層の周縁部に沿ってリング状に高濃度のn形シ
リコンの拡散層を形成し、前記P形シリコン基板の前記
埋め込み層に対応する部分に異方性エツチングにより前
記埋込み層の深さまで凹部を形成し、
前記p形シリコン基板と前記n形エピタキシャル層との
間に逆バイアス電圧を印加した状態でエツチング液に対
してn形エピタキシャル層を正な位に保持して前記埋込
み層を電解エツチングして除去し前記起歪部を形成した
ことを特徴とするシリコンダイアフラムの製造方法を採
用したものである。Means for Solving the Problems In order to achieve this object, the present invention provides a buried layer of highly concentrated n-type silicon patterned in the shape of a strain-generating portion that is displaced by a measuring pressure on a p-type silicon substrate. forming an n-type epitaxial layer on one surface of the buried layer, epitaxially growing it on the buried layer, and forming a ring along the peripheral edge of the buried layer by penetrating the n-type epitaxial layer and connecting to the buried layer. forming a highly concentrated n-type silicon diffusion layer, forming a recessed portion of the p-type silicon substrate corresponding to the buried layer by anisotropic etching to the depth of the buried layer; The n-type epitaxial layer is held in a positive position with respect to the etching solution while a reverse bias voltage is applied between the buried layer and the n-type epitaxial layer, and the buried layer is electrolytically etched to remove the strain-generating portion. A method for manufacturing a silicon diaphragm is adopted.
く作 用〉
P形シリコン基板に高濃度のn形の埋込み層を形成し、
この上にさらにn形のエピタキシャル層を成長させ、こ
のn形のエピタキシャル層に高濃度のn形の埋込み層の
周縁部に沿って埋込み層に達するリング状の高濃度のn
形の拡散層を形成し、この後p形シリコン基板に異方性
エツチングによりこの埋込み層に通じる凹部を形成し、
さらにp形シリコン基板とn形エピタキシャル層との間
に逆バイアス電圧を印加した状態でエツチング液に対し
てn形エピタキシャル層を正電位に保持して埋込み層を
電解エヅチングして除去し起歪部を形成する。Effect〉 A highly concentrated n-type buried layer is formed on a p-type silicon substrate,
An n-type epitaxial layer is further grown on this layer, and a ring-shaped high-concentration n-type layer is formed on this n-type epitaxial layer to reach the buried layer along the periphery of the high-concentration n-type buried layer.
After that, a concave portion communicating with this buried layer is formed in the p-type silicon substrate by anisotropic etching,
Furthermore, with a reverse bias voltage applied between the p-type silicon substrate and the n-type epitaxial layer, the n-type epitaxial layer is held at a positive potential with respect to the etching solution, and the buried layer is electrolytically etched to remove the strain-generating portion. form.
〈実施例〉
第1図は本発明の一実施例の要部構成説明図で、半導体
圧力センサとして使用せる例について説明する。<Embodiment> FIG. 1 is an explanatory diagram of the main part configuration of an embodiment of the present invention, and an example in which it can be used as a semiconductor pressure sensor will be described.
第1図(イ)はp形のウェハ状のシリコン基板10に外
形が円形パターンになるように円形の不純物を高濃度(
n+)で拡散して埋込み層11を形成する拡散工程を示
す。FIG. 1(a) shows a p-type wafer-shaped silicon substrate 10 doped with circular impurities at a high concentration (
A diffusion process of forming the buried layer 11 by diffusing with n+) is shown.
この拡散]工程で形成された埋込み層の上に第1図(ロ
)に示す様に円形のエピタキシャル成長を行い円形エピ
タキシャル層12を形成する。On the buried layer formed in this diffusion step, circular epitaxial growth is performed to form a circular epitaxial layer 12, as shown in FIG. 1(b).
第1図(ハ)のゲージ形成工程では、この第1図(ロ)
で形成されたエピタキシャル層12の上にp形のゲージ
13を拡散などにより形成し、その上を窒化膜などの絶
縁膜14で覆ってゲージ13を保護すると共にシリコン
基板10の底面を同様に窒化膜などの絶縁膜15で覆い
、次の異方性エツチング工程でのマスクとする。In the gauge forming process of Fig. 1 (c), this Fig. 1 (b)
A p-type gauge 13 is formed by diffusion or the like on the epitaxial layer 12 formed by the process, and is covered with an insulating film 14 such as a nitride film to protect the gauge 13, and the bottom surface of the silicon substrate 10 is also nitrided. It is covered with an insulating film 15 such as a film, and serves as a mask for the next anisotropic etching process.
素子分離の為の高濃度のP形アイソレーション拡散によ
りアイソレーション層131を形成する。An isolation layer 131 is formed by high concentration P type isolation diffusion for element isolation.
さらに、円形エピタキシャル層12を貫通し埋込み層1
1に接続し埋込み層11の周縁部に沿ってリング状に高
濃度の円形シリコンの拡散層よりなる電極16を形成し
ておく。Further, the buried layer 1 penetrates through the circular epitaxial layer 12.
An electrode 16 made of a circular high-concentration silicon diffusion layer is formed in a ring shape along the peripheral edge of the buried layer 11.
第1図(ニ)は、異方性エツチングの工程を示す、この
工程では埋込み層11に対応するシリコン基板10の連
通孔17を作る部分の絶縁膜15を四角形にパターンニ
ングして開口し、n+の埋込み層11の深さまで水酸化
カリウム(KOH)のエツチング液を用いて異方性エツ
チングを行い、シリコン基板10に断面が矩形の連通孔
】7を形成する。FIG. 1(D) shows the anisotropic etching process. In this process, the insulating film 15 is patterned into a rectangular shape and opened in a portion of the silicon substrate 10 corresponding to the buried layer 11 where a communication hole 17 is to be made. Anisotropic etching is performed using an etching solution of potassium hydroxide (KOH) to the depth of the n+ buried layer 11 to form a communicating hole 7 having a rectangular cross section in the silicon substrate 10.
第1図(ホ)は電解エツチングの工程を示す。FIG. 1(e) shows the electrolytic etching process.
この工程では、tix6を介して円形エピタキシャル層
12とp形のシリコン基板10との間に逆バイアスの直
流電圧E、とE2を印加し、さらに弗化水素(HF )
又は弗化アンモニウムなどのエツチング液の中に白金の
電極18を設けてこの電極18を(−)i、円形エピタ
キシャル層12を(+)4Itとして直流電圧E、を印
加して等方性の電解エツチングを行う。In this step, reverse bias DC voltages E and E2 are applied between the circular epitaxial layer 12 and the p-type silicon substrate 10 via tix6, and hydrogen fluoride (HF) is applied.
Alternatively, a platinum electrode 18 is provided in an etching solution such as ammonium fluoride, and a DC voltage E is applied with the electrode 18 set to (-)i and the circular epitaxial layer 12 set to (+)4It to perform isotropic electrolysis. Perform etching.
この電解エツチングにより、n+形の埋込み層11がエ
ツチングされて円形の凹部19とされ、この凹部19に
対向する円形エピタキシャル層12の部分が円形の起歪
部20となる第1図(へ)に示すダイアフラム21が形
成されるや第2図に完成平面図を示す。By this electrolytic etching, the n+ type buried layer 11 is etched to form a circular recess 19, and the portion of the circular epitaxial layer 12 facing this recess 19 becomes a circular strain-generating portion 20, as shown in FIG. Once the diaphragm 21 shown is formed, a completed plan view is shown in FIG.
以上の製造方法によりVJ造された半導体圧力センサは
、圧力Pが連通孔17、凹部19を介して導入され、こ
れにより起歪部20が歪んでゲージ13でこの歪みが電
気信号として検出される。In the semiconductor pressure sensor manufactured by VJ using the above manufacturing method, pressure P is introduced through the communication hole 17 and the recess 19, thereby the strain-generating portion 20 is distorted, and this distortion is detected by the gauge 13 as an electrical signal. .
この結果、凹部1つを形成するための円形のn4の埋込
み層11をP形のシリコン基板10の(−)衡としての
自己な様作用により凹部の奥のn+の埋込み層まで等方
性の電解エツチングし、凹部のfil uのサイドエツ
チングがないので、ダイアフラムの起歪部20の半径方
向の寸法精度が良く、また入手の困難なn4シリコン基
板を使う必要もなく、さらにウェハ単位でダイアフラム
加]二を行うことができるので量産化加工が可能となる
など各種の効果がある。As a result, the circular n4 buried layer 11 for forming one recess is isotropically extended to the n+ buried layer deep inside the recess due to the self-like action of the P-type silicon substrate 10 as a (-) balance. Since it is electrolytically etched and there is no side etching of the film in the recessed part, the dimensional accuracy of the strain-generating part 20 of the diaphragm in the radial direction is good, there is no need to use N4 silicon substrates that are difficult to obtain, and the diaphragm can be processed on a wafer basis. ] 2, it has various effects such as mass production processing becomes possible.
更に、円形エピタキシャル層12を貫通し埋込み層1】
に接続し埋込み層11の周縁部に沿ってリング状に高濃
度の円形シリコンの拡散層を形成したので、電極がリン
グ状に形成でき、エツチング電流のかたよりがなくなり
、エツチングむらなく、n+の埋込み層重1を等方性の
電解エツチングで確実に除去出来るので、ダイアフラム
の起歪部20の半径方向の寸法精度がより向上されたも
のが得られる。Furthermore, it penetrates the circular epitaxial layer 12 and the buried layer 1]
Since a highly concentrated circular silicon diffusion layer is formed in a ring shape along the periphery of the buried layer 11, the electrode can be formed in a ring shape, the etching current is uniform, the etching is uniform, and the N+ buried layer is formed. Since the layer weight 1 can be reliably removed by isotropic electrolytic etching, it is possible to obtain a strain-generating portion 20 of the diaphragm with improved radial dimensional accuracy.
第3図は本発明の他の実施例の要部構成説明図である。FIG. 3 is an explanatory diagram of the main part configuration of another embodiment of the present invention.
本実施例においては、埋込み層11の外周近くを電解エ
ツチングしている場合に、n4の94部】6がエツチン
グされてしまうのを防止するように、埋込み層11に十
字部111を設けたものである。In this embodiment, a cross section 111 is provided in the buried layer 11 to prevent portion 94]6 of n4 from being etched when electrolytic etching is performed near the outer periphery of the buried layer 11. It is.
なお、第1図(ホ)の電解エツチングの代りに超音波研
削加工などの機械加工を必要に応じて利用することもで
きる。In addition, instead of the electrolytic etching shown in FIG. 1(e), machining such as ultrasonic grinding may be used as required.
〈発明の効果〉
以上説明したように、本発明は、測定圧力により変位す
る起歪部の形にパターニングされた高濃度のn形シリコ
ンの埋込み層をp形シリコン基板の一方の面に形成し、
前記叩込み層の上にエピタキシャル成長をさせてn形エ
ピタキシャル層を形成し、
該n形エピタキシャル層を貫通し前記埋込み層に接続し
該叩込み層の周縁部に沿ってリング状に高濃度のn形シ
リコンの拡散層を形成し、前記P形シリコン基板の前記
埋め込み層に対応する部分にy4方性エツチングにより
前記埋込み層の深さまで凹部を形成し、
前記p形シリコン基板と前記n形エピタキシャル層との
間に逆バイアス電圧を印加した状態でエツチング液に対
してn形エピタキシャル層を正電位に保持して前記埋込
み層を電解エツチングして除去し前記起歪部を形成した
ことを特徴とするシリコンダイアプラムの製造方法を採
用した。<Effects of the Invention> As explained above, the present invention forms a buried layer of highly concentrated n-type silicon on one surface of a p-type silicon substrate, which is patterned in the shape of a strain-generating portion that is displaced by measurement pressure. , forming an n-type epitaxial layer by epitaxial growth on the implanted layer, penetrating the n-type epitaxial layer and connecting to the buried layer, and forming a high concentration layer in a ring shape along the periphery of the implanted layer; forming a diffusion layer of n-type silicon; forming a recessed portion to the depth of the buried layer in a portion of the p-type silicon substrate corresponding to the buried layer by y4-directional etching; The strain-generating portion is formed by electrolytically etching and removing the n-type epitaxial layer by holding the n-type epitaxial layer at a positive potential with respect to the etching solution while applying a reverse bias voltage between the n-type epitaxial layer and the etching solution. A manufacturing method for silicon diaphragms was adopted.
この結果、凹部を形成するための円形のn+の埋込み層
をp形のシリコン基板の(−)極としての自己電極作用
により凹部の奥のn+の埋込み層まで等方性の電解エツ
チングし、凹部の側壁のサイドエツチングがないので、
ダイアフラムの起歪部の半径方向の寸法精度が良く、ま
た入手の困難なn+シリコン基板を使う必要らなく、さ
らにウェハ単位でダイアプラム加工を行うことができる
ので厘産化加工が可能となるなど各種の効果がある。As a result, the circular n+ buried layer for forming the recess is isotropically etched to the n+ buried layer deep inside the recess by the self-electrode action of the p-type silicon substrate as the (-) pole. There is no side etching on the side wall of the
The strain-generating part of the diaphragm has good radial dimensional accuracy, and there is no need to use N+ silicon substrates, which are difficult to obtain.Furthermore, diaphragm processing can be performed on a wafer basis, making it possible to process on-demand production. There is an effect.
更に、n形エピタキシャル層を貫通し埋込み層に接続し
埋込み層の周縁部に沿ってリング状に高濃度のn形シリ
コンの拡散層を形成したので、電極がリング状に形成で
き、エツチング電流のかたよりがなくなり、エツチング
むらなく、n+の埋込み層を等方性の電解エツチングで
確実に除去出来るので、ダイアフラムの起歪部の半径方
向の寸法精度がより向上されたものが得られる。Furthermore, a high concentration n-type silicon diffusion layer was formed in a ring shape along the periphery of the buried layer, penetrating the n-type epitaxial layer and connected to the buried layer, so that the electrode could be formed in a ring shape and the etching current could be reduced. Since the n+ buried layer can be reliably removed by isotropic electrolytic etching without any uneven etching, it is possible to obtain a diaphragm with improved radial dimensional accuracy of the strain-generating portion.
従って、本発明によれば、量産性が良く、安着llIで
、精度のよいシリコンダイアフラムの’IIl’ft!
方法を実現することが出来る。Therefore, according to the present invention, the silicon diaphragm has 'IIl'ft' which is easy to mass-produce, is reliable, and has good precision.
The method can be implemented.
第1図は本発明の1実施例の製造方法を示す工程図、第
2図は第1図の完成平面図、第3図は本発明の他の実施
例の要部構成説明図で、(イ)は平面図、(ロ)は正面
図、第4図は従来の製造方法で製造された半導体圧力セ
ンサの構成を示す構成図である。
1.21・・・ダイアフラム、2.19・・・凹部、3
.20・・・起歪部、5.17・・・連通孔、8・・・
感圧素子、10・・・シリコン基板、11・・・埋込み
層、】11・・・十字部、12・・・n形エピタキシャ
ル層、13・・・ゲージ、131・・・アイソレーショ
ン層、14.15・・・絶縁膜、16・・・電極、工8
・・・電極。
第斗図FIG. 1 is a process diagram showing the manufacturing method of one embodiment of the present invention, FIG. 2 is a completed plan view of FIG. 1, and FIG. (A) is a plan view, (B) is a front view, and FIG. 4 is a configuration diagram showing the configuration of a semiconductor pressure sensor manufactured by a conventional manufacturing method. 1.21...diaphragm, 2.19...recess, 3
.. 20... Strain part, 5.17... Communication hole, 8...
Pressure sensitive element, 10... Silicon substrate, 11... Buried layer, ] 11... Cross portion, 12... N-type epitaxial layer, 13... Gauge, 131... Isolation layer, 14 .15... Insulating film, 16... Electrode, Engineering 8
···electrode. Number 1
Claims (1)
た高濃度のn形シリコンの埋込み層をp形シリコン基板
の一方の面に形成し、 前記埋込み層の上にエピタキシャル成長をさせてn形エ
ピタキシャル層を形成し、 該n形エピタキシャル層を貫通し前記埋込み層に接続し
該埋込み層の周縁部に沿ってリング状に高濃度のn形シ
リコンの拡散層を形成し、 前記p形シリコン基板の前記埋め込み層に対応する部分
に異方性エッチングにより前記埋込み層の深さまで凹部
を形成し、 前記p形シリコン基板と前記n形エピタキシャル層との
間に逆バイアス電圧を印加した状態でエッチング液に対
してn形エピタキシャル層を正電位に保持して前記埋込
み層を電解エッチングして除去し前記起歪部を形成した
ことを特徴とするシリコンダイアフラムの製造方法。[Claims] A buried layer of highly concentrated n-type silicon patterned in the shape of a strain-generating portion that is displaced by measurement pressure is formed on one surface of a p-type silicon substrate, and epitaxial growth is performed on the buried layer. forming an n-type epitaxial layer, penetrating the n-type epitaxial layer and connecting to the buried layer, and forming a ring-shaped highly doped n-type silicon diffusion layer along the periphery of the buried layer; A recess was formed in a portion of the p-type silicon substrate corresponding to the buried layer by anisotropic etching to the depth of the buried layer, and a reverse bias voltage was applied between the p-type silicon substrate and the n-type epitaxial layer. 1. A method of manufacturing a silicon diaphragm, characterized in that the buried layer is removed by electrolytic etching while the n-type epitaxial layer is held at a positive potential with respect to an etching solution to form the strain-generating portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22418988A JPH02177369A (en) | 1988-09-07 | 1988-09-07 | Manufacture of silicon diaphragm |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22418988A JPH02177369A (en) | 1988-09-07 | 1988-09-07 | Manufacture of silicon diaphragm |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02177369A true JPH02177369A (en) | 1990-07-10 |
Family
ID=16809917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22418988A Pending JPH02177369A (en) | 1988-09-07 | 1988-09-07 | Manufacture of silicon diaphragm |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02177369A (en) |
-
1988
- 1988-09-07 JP JP22418988A patent/JPH02177369A/en active Pending
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